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Start of Pipeline - (1 min 10 sec in block)
node - (1 min 9 sec in block)
node block - (1 min 7 sec in block)
stage - (33 sec in block)Git Clone
stage block (Git Clone) - (31 sec in block)
sh - (0.73 sec in self)rm -rf *.xml
sh - (4.7 sec in self)rm -rf Cores-SweRV-EL2
sh - (25 sec in self)git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-SweRV-EL2 Cores-SweRV-EL2
stage - (7.1 sec in block)Verilog Convert
stage block (Verilog Convert) - (4.4 sec in block)
dir - (2.6 sec in block)Cores-SweRV-EL2
dir block - (1.7 sec in block)
sh - (1 sec in self)RV_ROOT=$(pwd) configs/veer.config -set=fpga_optimize=1 -target=default -set=btb_size=128
stage - (3.4 sec in block)Simulation
stage block (Simulation) - (1.3 sec in block)
getContext - (0.56 sec in self)
stage - (2.7 sec in block)Utilities
stage block (Utilities) - (1 sec in block)
getContext - (0.5 sec in self)
stage - (18 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (15 sec in block)
getContext - (0.85 sec in self)
parallel - (12 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (11 sec in block)
stage - (10 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (9.5 sec in block)
getContext - (1.2 sec in self)
stage - (2.7 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1 sec in block)
getContext - (0.55 sec in self)
stage - (2.5 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (1 sec in block)
getContext - (0.45 sec in self)
stage - (1.9 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (1 sec in block)
getContext - (0.51 sec in self)
stage - (2.3 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.6 sec in block)
junit - (0.83 sec in self)**/*.xml