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+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Cores-VeeR-EH1 -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'lsu_addr' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:161]
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'lsu_rdata' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:162]
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'lsu_wdata' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:163]
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'lsu_rv3store' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:164]
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'lsu_we' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:165]
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'lsu_req' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:166]
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'lsu_ack' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:167]
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'lsu_atop' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:168]
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'lsu_be' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:169]
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'ifu_paddr' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:172]
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'ifu_fetch_req' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:173]
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'ifu_fetch_ack' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:174]
ERROR: [Synth 8-11365] for the instance 'u_veer' of module 'veer' declared at '/var/jenkins_home/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1/design/veer.sv:23', named port connection 'ifu_instr_rdata' does not exist [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:175]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/Cores-VeeR-EH1.sv:10]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_top' [/eda/processor_ci/internal/fpga_top.sv:8]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 299, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.