Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s rv_core core/rtl/rv_alu.v core/rtl/rv_alu_ctrl.v core/rtl/rv_branch_predict.v core/rtl/rv_branch_test.v core/rtl/rv_core.v core/rtl/rv_ctrl.v core/rtl/rv_data_mem.v core/rtl/rv_div.v core/rtl/rv_dpram.v core/rtl/rv_forward.v core/rtl/rv_hzd_detect.v core/rtl/rv_imm_gen.v core/rtl/rv_instr_mem.v core/rtl/rv_mem_map.v core/rtl/rv_mul.v core/rtl/rv_rf.v core/rtl/rv_instr_mem.v core/rtl/rv_data_mem.v
core/rtl/rv_instr_mem.v:18: error: 'rv_instr_mem' has already been declared in this scope.
core/rtl/rv_instr_mem.v:18:      : It was declared here as a module.
core/rtl/rv_instr_mem.v:40: error: Module rv_instr_mem was already declared here: core/rtl/rv_instr_mem.v:18

core/rtl/rv_data_mem.v:20: error: 'rv_data_mem' has already been declared in this scope.
core/rtl/rv_data_mem.v:20:      : It was declared here as a module.
core/rtl/rv_data_mem.v:46: error: Module rv_data_mem was already declared here: core/rtl/rv_data_mem.v:20