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Start of Pipeline - (46 sec in block)
node - (45 sec in block)
node block - (45 sec in block)
stage - (2.5 sec in block)Git Clone
stage block (Git Clone) - (2 sec in block)
sh - (0.47 sec in self)rm -rf *.xml
sh - (0.45 sec in self)rm -rf F03x
sh - (0.92 sec in self)git clone --recursive --depth=1 https://github.com/klessydra/F03x F03x
stage - (5.5 sec in block)Simulation
stage block (Simulation) - (4.9 sec in block)
dir - (4.6 sec in block)F03x
dir block - (4.3 sec in block)
sh - (4.1 sec in self)/eda/oss-cad-suite/bin/ghdl -a --std=08 klessydra-f0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-f0-3th/PKG_RiscV_Klessydra.vhd klessydra-f0-3th/TMR_REG_PKG.vhd klessydra-f0-3th/CMP-TMR_REG.vhd klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd klessydra-f0-3th/RTL-Debug_Unit.vhd klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd klessydra-f0-3th/STR-Klessydra_top.vhd
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.87 sec in block)F03x
dir block - (0.63 sec in block)
sh - (0.41 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (34 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (33 sec in block)
parallel - (33 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (32 sec in block)
stage - (32 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (32 sec in block)
lock - (31 sec in block)digilent_arty_a7_100t
lock block - (30 sec in block)
stage - (28 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (28 sec in block)
dir - (27 sec in block)F03x
dir block - (27 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (26 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p F03x -b digilent_arty_a7_100t
stage - (1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.43 sec in block)
getContext - (0.17 sec in self)
stage - (0.7 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (0.77 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.55 sec in block)
junit - (0.3 sec in self)**/*.xml