Console Output

Download View as plain text
Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/Flute
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf *.xml
[Pipeline] sh
+ rm -rf Flute
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/bluespec/Flute Flute
Cloning into 'Flute'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Flute/Flute
[Pipeline] {
[Pipeline] echo
FPGA > Simulation
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Flute/Flute
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/Flute/Flute -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkAXI4_Deburster_A.v
Trying to read file: /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkAXI4_Deburster_A.v
Trying to read file: /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkBoot_ROM.v
Trying to read file: /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkBranch_Predictor.v
Cache-related signals in mkNear_Mem.v
Possible cache file: mkMMU_Cache.v
Cache-related signals in mkMMU_Cache.v
Cache-related signals in mkCPU.v
Cache-related signals in mkFBox_Top.v
Cache-related signals in mkNear_Mem.v
Cache-related signals in mkFBox_Core.v
Cache-related signals in mkRISCV_MBox.v
Possible cache file: mkMMU_Cache.v
Cache-related signals in mkMMU_Cache.v
Cache-related signals in mkCPU.v
Cache-related signals in mkNear_Mem.v
Cache-related signals in mkRISCV_MBox.v
Possible cache file: mkMMU_Cache.v
Cache-related signals in mkMMU_Cache.v
Cache-related signals in mkCPU.v
Cache-related signals in mkNear_Mem.v
Cache-related signals in mkRISCV_MBox.v
Possible cache file: mkMMU_Cache.v
Cache-related signals in mkMMU_Cache.v
Cache-related signals in mkCPU.v
Possible cache file: mkLLCache.v
Cache-related signals in mkLLCache.v
Possible cache file: mkCache.v
Cache-related signals in mkCache.v
Possible cache file: mkI_MMU_Cache.v
Cache-related signals in mkI_MMU_Cache.v
Cache-related signals in mkFBox_Top.v
Cache-related signals in mkNear_Mem.v
Cache-related signals in mkFBox_Core.v
Cache-related signals in mkLLPipeline.v
Possible cache file: mkD_MMU_Cache.v
Cache-related signals in mkD_MMU_Cache.v
Cache-related signals in mkRISCV_MBox.v
Possible cache file: mkDMA_Cache.v
Cache-related signals in mkCPU.v
Cache-related signals in mkRISCV_FBox.v
Cache-related signals in mkFBox_Top.v
Cache-related signals in mkNear_Mem.v
Cache-related signals in mkFBox_Core.v
Cache-related signals in mkRISCV_MBox.v
Possible cache file: mkMMU_Cache.v
Cache-related signals in mkMMU_Cache.v
Cache-related signals in mkCPU.v
Cache-related signals in mkRISCV_FBox.v
Cache-related signals in mkFBox_Top.v
Cache-related signals in mkNear_Mem.v
Cache-related signals in mkFBox_Core.v
Cache-related signals in mkRISCV_MBox.v
Possible cache file: mkMMU_Cache.v
Cache-related signals in mkMMU_Cache.v
Cache-related signals in mkCPU.v
Cache-related signals in mkNear_Mem.v
Cache-related signals in mkRISCV_MBox.v
Possible cache file: mkMMU_Cache.v
Cache-related signals in mkMMU_Cache.v
Cache-related signals in mkCPU.v
Cache-related signals in mkRISCV_FBox.v
Cache-related signals in mkFBox_Top.v
Cache-related signals in mkNear_Mem.v
Cache-related signals in mkFBox_Core.v
Cache-related signals in mkRISCV_MBox.v
Possible cache file: mkMMU_Cache.v
Cache-related signals in mkMMU_Cache.v
Cache-related signals in mkCPU.v
Cache-related signals in mkNear_Mem.v
Cache-related signals in mkRISCV_MBox.v
Possible cache file: mkMMU_Cache.v
Cache-related signals in mkMMU_Cache.v
Cache-related signals in mkCPU.v
Possible cache file: mkLLCache.v
Cache-related signals in mkLLCache.v
Possible cache file: mkCache.v
Cache-related signals in mkCache.v
Possible cache file: mkI_MMU_Cache.v
Cache-related signals in mkI_MMU_Cache.v
Cache-related signals in mkFBox_Top.v
Cache-related signals in mkNear_Mem.v
Cache-related signals in mkFBox_Core.v
Cache-related signals in mkLLPipeline.v
Possible cache file: mkD_MMU_Cache.v
Cache-related signals in mkD_MMU_Cache.v
Cache-related signals in mkRISCV_MBox.v
Cache-related signals in mkCPU.v
Cache-related signals in FIFO1.v
Possible cache file: mkLLCache.v
Cache-related signals in mkLLCache.v
Possible cache file: mkCache.v
Cache-related signals in mkCache.v
Possible cache file: mkI_MMU_Cache.v
Cache-related signals in mkI_MMU_Cache.v
Cache-related signals in SyncFIFOLevel.v
Cache-related signals in mkFBox_Top.v
Cache-related signals in FIFO20.v
Cache-related signals in SizedFIFO0.v
Cache-related signals in mkNear_Mem.v
Cache-related signals in mkFBox_Core.v
Cache-related signals in mkLLPipeline.v
Cache-related signals in FIFO2.v
Cache-related signals in FIFOL1.v
Possible cache file: mkD_MMU_Cache.v
Cache-related signals in mkD_MMU_Cache.v
Cache-related signals in mkRISCV_MBox.v
Possible cache file: mkMMU_Cache.v
Cache-related signals in mkMMU_Cache.v
Cache-related signals in FIFO1.v
Cache-related signals in SyncFIFO.v
Cache-related signals in FIFO20.v
Cache-related signals in SizedFIFO0.v
Cache-related signals in FIFO2.v
Cache-related signals in FIFOL1.v
Cache-related signals in SyncFIFO0.v
Cache-related signals in FIFO10.v
Results saved to /jenkins/processor_ci_utils/labels/Flute.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
Resource [digilent_arty_a7_100t] did not exist. Created.
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Flute/Flute
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Flute -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/Flute/Flute/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-36] 'v__h1235' is not declared [/var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkTop_HW_Side.v:203]
ERROR: [Synth 8-36] 'TASK_testplusargs___d11' is not declared [/var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkTop_HW_Side.v:206]
ERROR: [Synth 8-36] 'TASK_testplusargs___d12' is not declared [/var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkTop_HW_Side.v:208]
ERROR: [Synth 8-36] 'tohost_addr__h618' is not declared [/var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkTop_HW_Side.v:209]
ERROR: [Synth 8-36] 'TASK_testplusargs___d15' is not declared [/var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkTop_HW_Side.v:210]
ERROR: [Synth 8-36] 'v__h1235' is not declared [/var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkTop_HW_Side.v:220]
ERROR: [Synth 8-439] module 'uart_rx' not found [/eda/processor-ci-controller/modules/uart.sv:260]
ERROR: [Synth 8-6156] failed synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/Flute.sv:7]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_top' [/eda/processor_ci/internal/fpga_top.sv:8]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 299, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE