Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s Core -I src/core src/core/alu.v src/core/alu_control.v src/core/core.v src/core/forwarding_unit.v src/core/immediate_generator.v src/core/mux.v src/core/registers.v src/core/mdu.v src/core/bmu.v src/core/csr_unit.v src/core/fpu.v src/core/ir_decomp.v
src/core/alu.v: No such file or directory
error: Unable to find the root module "Core" in the Verilog source.
     : Perhaps ``-s Core'' is incorrect?
1 error(s) during elaboration.
Segmentation fault (core dumped)