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+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-11365] for the instance 'ptop' of module 'processorci_top' declared at '/eda/processor_ci/rtl/Grande-Risco-5.sv:9', named port connection 'sck' does not exist [/eda/processor_ci/internal/fpga_top.sv:45]
ERROR: [Synth 8-11365] for the instance 'ptop' of module 'processorci_top' declared at '/eda/processor_ci/rtl/Grande-Risco-5.sv:9', named port connection 'cs' does not exist [/eda/processor_ci/internal/fpga_top.sv:46]
ERROR: [Synth 8-11365] for the instance 'ptop' of module 'processorci_top' declared at '/eda/processor_ci/rtl/Grande-Risco-5.sv:9', named port connection 'mosi' does not exist [/eda/processor_ci/internal/fpga_top.sv:47]
ERROR: [Synth 8-11365] for the instance 'ptop' of module 'processorci_top' declared at '/eda/processor_ci/rtl/Grande-Risco-5.sv:9', named port connection 'miso' does not exist [/eda/processor_ci/internal/fpga_top.sv:48]
ERROR: [Synth 8-11365] for the instance 'ptop' of module 'processorci_top' declared at '/eda/processor_ci/rtl/Grande-Risco-5.sv:9', named port connection 'rw' does not exist [/eda/processor_ci/internal/fpga_top.sv:51]
ERROR: [Synth 8-11365] for the instance 'ptop' of module 'processorci_top' declared at '/eda/processor_ci/rtl/Grande-Risco-5.sv:9', named port connection 'intr' does not exist [/eda/processor_ci/internal/fpga_top.sv:52]
ERROR: [Synth 8-11365] for the instance 'ptop' of module 'processorci_top' declared at '/eda/processor_ci/rtl/Grande-Risco-5.sv:9', named port connection 'rx' does not exist [/eda/processor_ci/internal/fpga_top.sv:55]
ERROR: [Synth 8-11365] for the instance 'ptop' of module 'processorci_top' declared at '/eda/processor_ci/rtl/Grande-Risco-5.sv:9', named port connection 'tx' does not exist [/eda/processor_ci/internal/fpga_top.sv:56]
ERROR: [Synth 8-6156] failed synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/rtl/reset.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_top' [/eda/processor_ci/internal/fpga_top.sv:5]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 297, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.