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Start of Pipeline - (18 min in block)
node - (18 min in block)
node block - (18 min in block)
stage - (2.4 sec in block)Git Clone
stage block (Git Clone) - (1.9 sec in block)
sh - (0.46 sec in self)rm -rf Grande-Risco-5
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/JN513/Grande-Risco-5 Grande-Risco-5
stage - (1.8 sec in block)Simulation
stage block (Simulation) - (1.3 sec in block)
dir - (0.93 sec in block)Grande-Risco-5
dir block - (0.63 sec in block)
sh - (0.44 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s Grande_Risco5 src/core/alu.v src/core/alu_control.v src/core/core.v src/core/forwarding_unit.v src/core/immediate_generator.v src/core/mux.v src/core/registers.v
stage - (18 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (18 min in block)
parallel - (18 min in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (10 min in block)colorlight_i9
stage block (colorlight_i9) - (10 min in block)
lock - (10 min in block)colorlight_i9
lock block - (6 min 13 sec in block)
stage - (5 min 54 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (5 min 53 sec in block)
dir - (5 min 52 sec in block)Grande-Risco-5
dir block - (5 min 52 sec in block)
echo - (0.34 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (5 min 51 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Grande-Risco-5 -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)Grande-Risco-5
dir block - (15 sec in block)
echo - (0.15 sec in self)Flashing FPGA colorlight_i9.
sh - (15 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Grande-Risco-5 -b colorlight_i9 -l
stage - (2 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.7 sec in block)
echo - (0.22 sec in self)Testing FPGA colorlight_i9.
dir - (1 sec in block)Grande-Risco-5
dir block - (0.69 sec in block)
sh - (0.47 sec in self)PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" python /eda/processor-ci-communication/run_tests.py
parallel block (Branch: digilent_nexys4_ddr) - (18 min in block)
stage - (18 min in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (18 min in block)
lock - (18 min in block)digilent_nexys4_ddr
lock block - (12 min in block)
stage - (11 min in block)Synthesis and PnR
stage block (Synthesis and PnR) - (11 min in block)
dir - (11 min in block)Grande-Risco-5
dir block - (11 min in block)
echo - (0.34 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (11 min in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Grande-Risco-5 -b digilent_nexys4_ddr
stage - (7 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (6.5 sec in block)
dir - (6.2 sec in block)Grande-Risco-5
dir block - (5.9 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_nexys4_ddr.
sh - (5.6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Grande-Risco-5 -b digilent_nexys4_ddr -l
stage - (1.9 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (1.6 sec in block)
echo - (0.23 sec in self)Testing FPGA digilent_nexys4_ddr.
dir - (1 sec in block)Grande-Risco-5
dir block - (0.68 sec in block)
sh - (0.45 sec in self)PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" python /eda/processor-ci-communication/run_tests.py
stage - (0.79 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.55 sec in block)
junit - (0.28 sec in self)**/test-reports/*.xml