Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s Grande_Risco5 src/core/alu.v src/core/alu_control.v src/core/core.v src/core/forwarding_unit.v src/core/immediate_generator.v src/core/mux.v src/core/registers.v
src/core/core.v:82: error: Unable to bind wire/reg/memory `is_different_branch_address' in `Grande_Risco5'
src/core/core.v:84:      : A symbol with that name was declared here. Check for declaration after use.
src/core/core.v:82: error: Unable to elaborate r-value: (is_different_branch_address)&(takebranch)
2 error(s) during elaboration.