Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s Grande_Risco5 src/core/alu.v src/core/alu_control.v src/core/core.v src/core/forwarding_unit.v src/core/immediate_generator.v src/core/mux.v src/core/registers.v
error: Unable to find the root module "Grande_Risco5" in the Verilog source.
     : Perhaps ``-s Grande_Risco5'' is incorrect?
1 error(s) during elaboration.