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Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/Hazard3
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf Hazard3
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/Wren6991/Hazard3 Hazard3
Cloning into 'Hazard3'...
Submodule 'example_soc/libfpga' (https://github.com/Wren6991/libfpga.git) registered for path 'example_soc/libfpga'
Submodule 'scripts' (https://github.com/Wren6991/fpgascripts) registered for path 'scripts'
Submodule 'test/formal/riscv-formal' (https://github.com/Wren6991/riscv-formal.git) registered for path 'test/formal/riscv-formal/riscv-formal'
Submodule 'test/sim/embench/embench-iot' (https://github.com/Wren6991/embench-iot.git) registered for path 'test/sim/embench/embench-iot'
Submodule 'test/sim/riscv-compliance/riscv-arch-test' (https://github.com/wren6991/riscv-arch-test.git) registered for path 'test/sim/riscv-compliance/riscv-arch-test'
Submodule 'test/sim/riscv-tests/riscv-tests' (https://github.com/Wren6991/riscv-tests.git) registered for path 'test/sim/riscv-tests/riscv-tests'
Cloning into '/var/jenkins_home/workspace/Hazard3/Hazard3/example_soc/libfpga'...
Cloning into '/var/jenkins_home/workspace/Hazard3/Hazard3/scripts'...
Cloning into '/var/jenkins_home/workspace/Hazard3/Hazard3/test/formal/riscv-formal/riscv-formal'...
Cloning into '/var/jenkins_home/workspace/Hazard3/Hazard3/test/sim/embench/embench-iot'...
Cloning into '/var/jenkins_home/workspace/Hazard3/Hazard3/test/sim/riscv-compliance/riscv-arch-test'...
Cloning into '/var/jenkins_home/workspace/Hazard3/Hazard3/test/sim/riscv-tests/riscv-tests'...
Submodule path 'example_soc/libfpga': checked out '9d50e12e01efb59c45f4f71ff5d650a7fb7c6acc'
Submodule path 'scripts': checked out '841ed3ec1717ce490587b1ad7456bc77faf9a2f3'
From https://github.com/Wren6991/riscv-formal
 * branch            c12efe293f5f7788c36155675e1d609d7dc15290 -> FETCH_HEAD
Submodule path 'test/formal/riscv-formal/riscv-formal': checked out 'c12efe293f5f7788c36155675e1d609d7dc15290'
Submodule path 'test/sim/embench/embench-iot': checked out 'bfbfbbf71a681ab09dcfb33195e9225156a569c7'
From https://github.com/wren6991/riscv-arch-test
 * branch            099a70167993378fe25fe1e668207fc4ea3c0fb0 -> FETCH_HEAD
Submodule path 'test/sim/riscv-compliance/riscv-arch-test': checked out '099a70167993378fe25fe1e668207fc4ea3c0fb0'
Submodule path 'test/sim/riscv-tests/riscv-tests': checked out 'debd6eccdce79083fbc055e48271781b379029ed'
Submodule 'env' (https://github.com/riscv/riscv-test-env.git) registered for path 'test/sim/riscv-tests/riscv-tests/env'
Cloning into '/var/jenkins_home/workspace/Hazard3/Hazard3/test/sim/riscv-tests/riscv-tests/env'...
Submodule path 'test/sim/riscv-tests/riscv-tests/env': checked out '4fabfb4e0d3eacc1dc791da70e342e4b68ea7e46'
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Hazard3/Hazard3
[Pipeline] {
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s example_soc/fpga/fpga_icebreaker.v example_soc/fpga/fpga_orangecrab_25f.v example_soc/fpga/fpga_ulx3s.v example_soc/fpga/pll_25_40.v example_soc/fpga/pll_25_50.v example_soc/libfpga/arith/radix2_mult.v example_soc/libfpga/arith/wallace_adder.v example_soc/libfpga/arith/wallace_mult.v example_soc/libfpga/busfabric/ahbl_arbiter.v example_soc/libfpga/busfabric/ahbl_crossbar.v example_soc/libfpga/busfabric/ahbl_splitter.v example_soc/libfpga/busfabric/ahbl_to_apb.v example_soc/libfpga/busfabric/apb_splitter.v example_soc/libfpga/cdc/async_fifo.v example_soc/libfpga/cdc/gearbox.v example_soc/libfpga/cdc/gray_counter.v example_soc/libfpga/cdc/gray_decode.v example_soc/libfpga/cdc/sync_1bit.v example_soc/libfpga/common/activity_led.v example_soc/libfpga/common/blinky.v example_soc/libfpga/common/clkdiv_frac.v example_soc/libfpga/common/ddr_out.v example_soc/libfpga/common/debounce_ctr.v example_soc/libfpga/common/delay_ff.v example_soc/libfpga/common/dffe_out.v example_soc/libfpga/common/fpga_reset.v example_soc/libfpga/common/memdump.v example_soc/libfpga/common/nbit_sync.v example_soc/libfpga/common/onehot_encoder.v example_soc/libfpga/common/onehot_mux.v example_soc/libfpga/common/onehot_priority.v example_soc/libfpga/common/onehot_priority_dynamic.v example_soc/libfpga/common/popcount.v example_soc/libfpga/common/pullup_input.v example_soc/libfpga/common/reset_sync.v example_soc/libfpga/common/skid_buffer.v example_soc/libfpga/common/sync_fifo.v example_soc/libfpga/common/tristate_io.v example_soc/libfpga/mem/ahb_async_sram.v example_soc/libfpga/mem/ahb_async_sram_halfwidth.v example_soc/libfpga/mem/ahb_cache_readonly.v example_soc/libfpga/mem/ahb_cache_writeback.v example_soc/libfpga/mem/ahb_sync_sram.v example_soc/libfpga/mem/cache_mem_directmapped.v example_soc/libfpga/mem/cache_mem_set_associative.v example_soc/libfpga/mem/sram_sync.v example_soc/libfpga/mem/sram_sync_1r1w.v example_soc/libfpga/mem/behav/sram_async.v example_soc/libfpga/peris/spi/spi_mini.v example_soc/libfpga/peris/spi/spi_regs.v example_soc/libfpga/peris/spi_03h_xip/spi_03h_xip.v example_soc/libfpga/peris/spi_03h_xip/spi_03h_xip_regs.v example_soc/libfpga/peris/uart/uart_mini.v example_soc/libfpga/peris/uart/uart_regs.v example_soc/libfpga/video/dvi_clock_driver.v example_soc/libfpga/video/dvi_serialiser.v example_soc/libfpga/video/dvi_timing.v example_soc/libfpga/video/dvi_tx_parallel.v example_soc/libfpga/video/smoldvi_tmds_encode.v example_soc/libfpga/video/tmds_encode.v example_soc/soc/example_soc.v example_soc/soc/peri/hazard3_riscv_timer.v hdl/hazard3_core.v hdl/hazard3_cpu_1port.v hdl/hazard3_cpu_2port.v hdl/hazard3_csr.v hdl/hazard3_decode.v hdl/hazard3_frontend.v hdl/hazard3_instr_decompress.v hdl/hazard3_irq_ctrl.v hdl/hazard3_pmp.v hdl/hazard3_power_ctrl.v hdl/hazard3_regfile_1w2r.v hdl/hazard3_triggers.v hdl/arith/hazard3_alu.v hdl/arith/hazard3_branchcmp.v hdl/arith/hazard3_mul_fast.v hdl/arith/hazard3_muldiv_seq.v hdl/arith/hazard3_onehot_encode.v hdl/arith/hazard3_onehot_priority.v hdl/arith/hazard3_onehot_priority_dynamic.v hdl/arith/hazard3_priority_encode.v hdl/arith/hazard3_shift_barrel.v hdl/debug/cdc/hazard3_apb_async_bridge.v hdl/debug/cdc/hazard3_reset_sync.v hdl/debug/cdc/hazard3_sync_1bit.v hdl/debug/dm/hazard3_dm.v hdl/debug/dm/hazard3_sbus_to_ahb.v hdl/debug/dtm/hazard3_ecp5_jtag_dtm.v hdl/debug/dtm/hazard3_jtag_dtm.v hdl/debug/dtm/hazard3_jtag_dtm_core.v example_soc/libfpga/test/ahb_cache_readonly/tb.v example_soc/libfpga/test/ahb_cache_writeback/tb.v test/formal/bus_compliance_1port/tb.v test/formal/bus_compliance_2port/tb.v test/formal/common/ahbl_master_assertions.v test/formal/common/ahbl_slave_assumptions.v test/formal/common/sbus_assumptions.v test/formal/frontend_fetch_match/tb.v test/formal/instruction_fetch_match/tb.v test/formal/riscv-formal/riscv-formal/cores/VexRiscv/VexRiscv.v test/formal/riscv-formal/riscv-formal/insns/insn_add.v test/formal/riscv-formal/riscv-formal/insns/insn_addi.v test/formal/riscv-formal/riscv-formal/insns/insn_addiw.v test/formal/riscv-formal/riscv-formal/insns/insn_addw.v test/formal/riscv-formal/riscv-formal/insns/insn_and.v test/formal/riscv-formal/riscv-formal/insns/insn_andi.v test/formal/riscv-formal/riscv-formal/insns/insn_auipc.v test/formal/riscv-formal/riscv-formal/insns/insn_beq.v test/formal/riscv-formal/riscv-formal/insns/insn_bge.v test/formal/riscv-formal/riscv-formal/insns/insn_bgeu.v test/formal/riscv-formal/riscv-formal/insns/insn_blt.v test/formal/riscv-formal/riscv-formal/insns/insn_bltu.v test/formal/riscv-formal/riscv-formal/insns/insn_bne.v test/formal/riscv-formal/riscv-formal/insns/insn_c_add.v test/formal/riscv-formal/riscv-formal/insns/insn_c_addi.v test/formal/riscv-formal/riscv-formal/insns/insn_c_addi16sp.v test/formal/riscv-formal/riscv-formal/insns/insn_c_addi4spn.v test/formal/riscv-formal/riscv-formal/insns/insn_c_addiw.v test/formal/riscv-formal/riscv-formal/insns/insn_c_addw.v test/formal/riscv-formal/riscv-formal/insns/insn_c_and.v test/formal/riscv-formal/riscv-formal/insns/insn_c_andi.v test/formal/riscv-formal/riscv-formal/insns/insn_c_beqz.v test/formal/riscv-formal/riscv-formal/insns/insn_c_bnez.v test/formal/riscv-formal/riscv-formal/insns/insn_c_j.v test/formal/riscv-formal/riscv-formal/insns/insn_c_jal.v test/formal/riscv-formal/riscv-formal/insns/insn_c_jalr.v test/formal/riscv-formal/riscv-formal/insns/insn_c_jr.v test/formal/riscv-formal/riscv-formal/insns/insn_c_ld.v test/formal/riscv-formal/riscv-formal/insns/insn_c_ldsp.v test/formal/riscv-formal/riscv-formal/insns/insn_c_li.v test/formal/riscv-formal/riscv-formal/insns/insn_c_lui.v test/formal/riscv-formal/riscv-formal/insns/insn_c_lw.v test/formal/riscv-formal/riscv-formal/insns/insn_c_lwsp.v test/formal/riscv-formal/riscv-formal/insns/insn_c_mv.v test/formal/riscv-formal/riscv-formal/insns/insn_c_or.v test/formal/riscv-formal/riscv-formal/insns/insn_c_sd.v test/formal/riscv-formal/riscv-formal/insns/insn_c_sdsp.v test/formal/riscv-formal/riscv-formal/insns/insn_c_slli.v test/formal/riscv-formal/riscv-formal/insns/insn_c_srai.v test/formal/riscv-formal/riscv-formal/insns/insn_c_srli.v test/formal/riscv-formal/riscv-formal/insns/insn_c_sub.v test/formal/riscv-formal/riscv-formal/insns/insn_c_subw.v test/formal/riscv-formal/riscv-formal/insns/insn_c_sw.v test/formal/riscv-formal/riscv-formal/insns/insn_c_swsp.v test/formal/riscv-formal/riscv-formal/insns/insn_c_xor.v test/formal/riscv-formal/riscv-formal/insns/insn_div.v test/formal/riscv-formal/riscv-formal/insns/insn_divu.v test/formal/riscv-formal/riscv-formal/insns/insn_divuw.v test/formal/riscv-formal/riscv-formal/insns/insn_divw.v test/formal/riscv-formal/riscv-formal/insns/insn_jal.v test/formal/riscv-formal/riscv-formal/insns/insn_jalr.v test/formal/riscv-formal/riscv-formal/insns/insn_lb.v test/formal/riscv-formal/riscv-formal/insns/insn_lbu.v test/formal/riscv-formal/riscv-formal/insns/insn_ld.v test/formal/riscv-formal/riscv-formal/insns/insn_lh.v test/formal/riscv-formal/riscv-formal/insns/insn_lhu.v test/formal/riscv-formal/riscv-formal/insns/insn_lui.v test/formal/riscv-formal/riscv-formal/insns/insn_lw.v test/formal/riscv-formal/riscv-formal/insns/insn_lwu.v test/formal/riscv-formal/riscv-formal/insns/insn_mul.v test/formal/riscv-formal/riscv-formal/insns/insn_mulh.v test/formal/riscv-formal/riscv-formal/insns/insn_mulhsu.v test/formal/riscv-formal/riscv-formal/insns/insn_mulhu.v test/formal/riscv-formal/riscv-formal/insns/insn_mulw.v test/formal/riscv-formal/riscv-formal/insns/insn_or.v test/formal/riscv-formal/riscv-formal/insns/insn_ori.v test/formal/riscv-formal/riscv-formal/insns/insn_rem.v test/formal/riscv-formal/riscv-formal/insns/insn_remu.v test/formal/riscv-formal/riscv-formal/insns/insn_remuw.v test/formal/riscv-formal/riscv-formal/insns/insn_remw.v test/formal/riscv-formal/riscv-formal/insns/insn_sb.v test/formal/riscv-formal/riscv-formal/insns/insn_sd.v test/formal/riscv-formal/riscv-formal/insns/insn_sh.v test/formal/riscv-formal/riscv-formal/insns/insn_sll.v test/formal/riscv-formal/riscv-formal/insns/insn_slli.v test/formal/riscv-formal/riscv-formal/insns/insn_slliw.v test/formal/riscv-formal/riscv-formal/insns/insn_sllw.v test/formal/riscv-formal/riscv-formal/insns/insn_slt.v test/formal/riscv-formal/riscv-formal/insns/insn_slti.v test/formal/riscv-formal/riscv-formal/insns/insn_sltiu.v test/formal/riscv-formal/riscv-formal/insns/insn_sltu.v test/formal/riscv-formal/riscv-formal/insns/insn_sra.v test/formal/riscv-formal/riscv-formal/insns/insn_srai.v test/formal/riscv-formal/riscv-formal/insns/insn_sraiw.v test/formal/riscv-formal/riscv-formal/insns/insn_sraw.v test/formal/riscv-formal/riscv-formal/insns/insn_srl.v test/formal/riscv-formal/riscv-formal/insns/insn_srli.v test/formal/riscv-formal/riscv-formal/insns/insn_srliw.v test/formal/riscv-formal/riscv-formal/insns/insn_srlw.v test/formal/riscv-formal/riscv-formal/insns/insn_sub.v test/formal/riscv-formal/riscv-formal/insns/insn_subw.v test/formal/riscv-formal/riscv-formal/insns/insn_sw.v test/formal/riscv-formal/riscv-formal/insns/insn_xor.v test/formal/riscv-formal/riscv-formal/insns/insn_xori.v test/formal/riscv-formal/riscv-formal/insns/isa_rv32i.v test/formal/riscv-formal/riscv-formal/insns/isa_rv32ic.v test/formal/riscv-formal/riscv-formal/insns/isa_rv32im.v test/formal/riscv-formal/riscv-formal/insns/isa_rv32imc.v test/formal/riscv-formal/riscv-formal/insns/isa_rv64i.v test/formal/riscv-formal/riscv-formal/insns/isa_rv64ic.v test/formal/riscv-formal/riscv-formal/insns/isa_rv64im.v test/formal/riscv-formal/riscv-formal/insns/isa_rv64imc.v test/formal/riscv-formal/riscv-formal/tests/coverage/riscv_rv32i_insn.v test/formal/riscv-formal/riscv-formal/tests/coverage/riscv_rv32ic_insn.v test/formal/riscv-formal/riscv-formal/tests/coverage/riscv_rv64i_insn.v test/formal/riscv-formal/riscv-formal/tests/coverage/riscv_rv64ic_insn.v test/formal/riscv-formal/tb/hazard3_rvfi_wrapper.v test/sim/tb_cxxrtl/tb.v test/sim/tb_cxxrtl/tb_multicore.v test/formal/riscv-formal/riscv-formal/checks/rvfi_causal_check.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_channel.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_cover_check.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_csrw_check.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_dmem_check.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_hang_check.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_ill_check.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_imem_check.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_insn_check.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_liveness_check.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_pc_bwd_check.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_pc_fwd_check.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_reg_check.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_testbench.sv test/formal/riscv-formal/riscv-formal/checks/rvfi_unique_check.sv test/formal/riscv-formal/riscv-formal/cores/VexRiscv/dmemcheck.sv test/formal/riscv-formal/riscv-formal/cores/VexRiscv/imemcheck.sv test/formal/riscv-formal/riscv-formal/cores/VexRiscv/wrapper.sv test/formal/riscv-formal/riscv-formal/cores/picorv32/complete.sv test/formal/riscv-formal/riscv-formal/cores/picorv32/cover.sv test/formal/riscv-formal/riscv-formal/cores/picorv32/dmemcheck.sv test/formal/riscv-formal/riscv-formal/cores/picorv32/honest.sv test/formal/riscv-formal/riscv-formal/cores/picorv32/imemcheck.sv test/formal/riscv-formal/riscv-formal/cores/picorv32/wrapper.sv test/formal/riscv-formal/riscv-formal/cores/rocket/cover.sv test/formal/riscv-formal/riscv-formal/cores/rocket/coverage.sv test/formal/riscv-formal/riscv-formal/cores/rocket/muldivlen.sv test/formal/riscv-formal/riscv-formal/cores/rocket/rocketrvfi.sv test/formal/riscv-formal/riscv-formal/cores/rocket/wrapper.sv test/formal/riscv-formal/riscv-formal/cores/serv/cover.sv test/formal/riscv-formal/riscv-formal/cores/serv/sbram.sv test/formal/riscv-formal/riscv-formal/cores/serv/wrapper.sv test/formal/riscv-formal/riscv-formal/tests/coverage/coverage.sv test/formal/riscv-formal/riscv-formal/tests/semantics/top.sv
example_soc/soc/example_soc.v:17: Include file hazard3_config.vh not found
example_soc/soc/example_soc.v:16: syntax error
I give up.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
Stage "Utilities" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
[Pipeline] stage
[Pipeline] { (Test digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 23c8ced1-04aa-4063-9020-7f09156cff5c
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:47)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 2
Finished: FAILURE