Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/rtl/fifo.sv:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/rtl/memory.sv:1]
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 8192 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Timer' [/eda/processor-ci-controller/rtl/timer.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'Timer' (0#1) [/eda/processor-ci-controller/rtl/timer.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/rtl/controller.sv:1]
INFO: [Synth 8-6157] synthesizing module 'ahb_to_wishbone' [/eda/processor_ci/internal/ahblite_to_wishbone.sv:1]
Parameter ADDR_WIDTH bound to: 32 - type: integer
Parameter DATA_WIDTH bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ahb_to_wishbone' (0#1) [/eda/processor_ci/internal/ahblite_to_wishbone.sv:1]
WARNING: [Synth 8-689] width (1) of port connection 'HRESP' does not match port width (2) of module 'ahb_to_wishbone' [/eda/processor_ci/rtl/Hazard3.sv:173]
INFO: [Synth 8-6157] synthesizing module 'hazard3_cpu_1port' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_cpu_1port.v:12]
Parameter RESET_VECTOR bound to: 0 - type: integer
Parameter MTVEC_INIT bound to: 0 - type: integer
Parameter EXTENSION_A bound to: 1 - type: integer
Parameter EXTENSION_C bound to: 1 - type: integer
Parameter EXTENSION_M bound to: 1 - type: integer
Parameter EXTENSION_ZBA bound to: 1 - type: integer
Parameter EXTENSION_ZBB bound to: 1 - type: integer
Parameter EXTENSION_ZBC bound to: 1 - type: integer
Parameter EXTENSION_ZBS bound to: 1 - type: integer
Parameter EXTENSION_ZBKB bound to: 1 - type: integer
Parameter EXTENSION_ZIFENCEI bound to: 0 - type: integer
Parameter EXTENSION_XH3BEXTM bound to: 0 - type: integer
Parameter EXTENSION_XH3IRQ bound to: 0 - type: integer
Parameter EXTENSION_XH3PMPM bound to: 0 - type: integer
Parameter EXTENSION_XH3POWER bound to: 0 - type: integer
Parameter CSR_M_MANDATORY bound to: 1 - type: integer
Parameter CSR_M_TRAP bound to: 1 - type: integer
Parameter CSR_COUNTER bound to: 0 - type: integer
Parameter U_MODE bound to: 0 - type: integer
Parameter PMP_REGIONS bound to: 0 - type: integer
Parameter PMP_GRAIN bound to: 0 - type: integer
Parameter PMP_HARDWIRED bound to: 0 - type: integer
Parameter PMP_HARDWIRED_ADDR bound to: 0 - type: integer
Parameter PMP_HARDWIRED_CFG bound to: 0 - type: integer
Parameter DEBUG_SUPPORT bound to: 1 - type: integer
Parameter BREAKPOINT_TRIGGERS bound to: 0 - type: integer
Parameter NUM_IRQS bound to: 1 - type: integer
Parameter IRQ_PRIORITY_BITS bound to: 0 - type: integer
Parameter MVENDORID_VAL bound to: 0 - type: integer
Parameter MIMPID_VAL bound to: 0 - type: integer
Parameter MHARTID_VAL bound to: 0 - type: integer
Parameter REDUCED_BYPASS bound to: 0 - type: integer
Parameter MULDIV_UNROLL bound to: 1 - type: integer
Parameter MUL_FAST bound to: 0 - type: integer
Parameter MUL_FASTER bound to: 1 - type: integer
Parameter MULH_FAST bound to: 1 - type: integer
Parameter FAST_BRANCHCMP bound to: 1 - type: integer
Parameter RESET_REGFILE bound to: 0 - type: integer
Parameter BRANCH_PREDICTOR bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'hazard3_core' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_core.v:8]
Parameter RESET_VECTOR bound to: 0 - type: integer
Parameter MTVEC_INIT bound to: 0 - type: integer
Parameter EXTENSION_A bound to: 1 - type: integer
Parameter EXTENSION_C bound to: 1 - type: integer
Parameter EXTENSION_M bound to: 1 - type: integer
Parameter EXTENSION_ZBA bound to: 1 - type: integer
Parameter EXTENSION_ZBB bound to: 1 - type: integer
Parameter EXTENSION_ZBC bound to: 1 - type: integer
Parameter EXTENSION_ZBS bound to: 1 - type: integer
Parameter EXTENSION_ZBKB bound to: 1 - type: integer
Parameter EXTENSION_ZCB bound to: 0 - type: integer
Parameter EXTENSION_ZCMP bound to: 0 - type: integer
Parameter EXTENSION_ZIFENCEI bound to: 0 - type: integer
Parameter EXTENSION_XH3BEXTM bound to: 0 - type: integer
Parameter EXTENSION_XH3IRQ bound to: 0 - type: integer
Parameter EXTENSION_XH3PMPM bound to: 0 - type: integer
Parameter EXTENSION_XH3POWER bound to: 0 - type: integer
Parameter CSR_M_MANDATORY bound to: 1 - type: integer
Parameter CSR_M_TRAP bound to: 1 - type: integer
Parameter CSR_COUNTER bound to: 0 - type: integer
Parameter U_MODE bound to: 0 - type: integer
Parameter PMP_REGIONS bound to: 0 - type: integer
Parameter PMP_GRAIN bound to: 0 - type: integer
Parameter PMP_HARDWIRED bound to: 0 - type: integer
Parameter PMP_HARDWIRED_ADDR bound to: 0 - type: integer
Parameter PMP_HARDWIRED_CFG bound to: 0 - type: integer
Parameter DEBUG_SUPPORT bound to: 1 - type: integer
Parameter BREAKPOINT_TRIGGERS bound to: 0 - type: integer
Parameter NUM_IRQS bound to: 1 - type: integer
Parameter IRQ_PRIORITY_BITS bound to: 0 - type: integer
Parameter IRQ_INPUT_BYPASS bound to: 1'b0
Parameter MVENDORID_VAL bound to: 0 - type: integer
Parameter MIMPID_VAL bound to: 0 - type: integer
Parameter MHARTID_VAL bound to: 0 - type: integer
Parameter MCONFIGPTR_VAL bound to: 0 - type: integer
Parameter REDUCED_BYPASS bound to: 0 - type: integer
Parameter MULDIV_UNROLL bound to: 1 - type: integer
Parameter MUL_FAST bound to: 0 - type: integer
Parameter MUL_FASTER bound to: 1 - type: integer
Parameter MULH_FAST bound to: 1 - type: integer
Parameter FAST_BRANCHCMP bound to: 1 - type: integer
Parameter RESET_REGFILE bound to: 0 - type: integer
Parameter BRANCH_PREDICTOR bound to: 1 - type: integer
Parameter MTVEC_WMASK bound to: -3 - type: integer
Parameter W_ADDR bound to: 32 - type: integer
Parameter W_DATA bound to: 32 - type: integer
INFO: [Synth 8-6157] synthesizing module 'hazard3_muldiv_seq' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_muldiv_seq.v:20]
Parameter RESET_VECTOR bound to: 0 - type: integer
Parameter MTVEC_INIT bound to: 0 - type: integer
Parameter EXTENSION_A bound to: 1 - type: integer
Parameter EXTENSION_C bound to: 1 - type: integer
Parameter EXTENSION_M bound to: 1 - type: integer
Parameter EXTENSION_ZBA bound to: 1 - type: integer
Parameter EXTENSION_ZBB bound to: 1 - type: integer
Parameter EXTENSION_ZBC bound to: 1 - type: integer
Parameter EXTENSION_ZBS bound to: 1 - type: integer
Parameter EXTENSION_ZBKB bound to: 1 - type: integer
Parameter EXTENSION_ZCB bound to: 0 - type: integer
Parameter EXTENSION_ZCMP bound to: 0 - type: integer
Parameter EXTENSION_ZIFENCEI bound to: 0 - type: integer
Parameter EXTENSION_XH3BEXTM bound to: 0 - type: integer
Parameter EXTENSION_XH3IRQ bound to: 0 - type: integer
Parameter EXTENSION_XH3PMPM bound to: 0 - type: integer
Parameter EXTENSION_XH3POWER bound to: 0 - type: integer
Parameter CSR_M_MANDATORY bound to: 1 - type: integer
Parameter CSR_M_TRAP bound to: 1 - type: integer
Parameter CSR_COUNTER bound to: 0 - type: integer
Parameter U_MODE bound to: 0 - type: integer
Parameter PMP_REGIONS bound to: 0 - type: integer
Parameter PMP_GRAIN bound to: 0 - type: integer
Parameter PMP_HARDWIRED bound to: 0 - type: integer
Parameter PMP_HARDWIRED_ADDR bound to: 0 - type: integer
Parameter PMP_HARDWIRED_CFG bound to: 0 - type: integer
Parameter DEBUG_SUPPORT bound to: 1 - type: integer
Parameter BREAKPOINT_TRIGGERS bound to: 0 - type: integer
Parameter NUM_IRQS bound to: 1 - type: integer
Parameter IRQ_PRIORITY_BITS bound to: 0 - type: integer
Parameter IRQ_INPUT_BYPASS bound to: 1'b0
Parameter MVENDORID_VAL bound to: 0 - type: integer
Parameter MIMPID_VAL bound to: 0 - type: integer
Parameter MHARTID_VAL bound to: 0 - type: integer
Parameter MCONFIGPTR_VAL bound to: 0 - type: integer
Parameter REDUCED_BYPASS bound to: 0 - type: integer
Parameter MULDIV_UNROLL bound to: 1 - type: integer
Parameter MUL_FAST bound to: 0 - type: integer
Parameter MUL_FASTER bound to: 1 - type: integer
Parameter MULH_FAST bound to: 1 - type: integer
Parameter FAST_BRANCHCMP bound to: 1 - type: integer
Parameter RESET_REGFILE bound to: 0 - type: integer
Parameter BRANCH_PREDICTOR bound to: 1 - type: integer
Parameter MTVEC_WMASK bound to: -3 - type: integer
Parameter W_ADDR bound to: 32 - type: integer
Parameter W_DATA bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'hazard3_muldiv_seq' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_muldiv_seq.v:20]
INFO: [Synth 8-6157] synthesizing module 'hazard3_branchcmp' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_branchcmp.v:16]
Parameter RESET_VECTOR bound to: 0 - type: integer
Parameter MTVEC_INIT bound to: 0 - type: integer
Parameter EXTENSION_A bound to: 1 - type: integer
Parameter EXTENSION_C bound to: 1 - type: integer
Parameter EXTENSION_M bound to: 1 - type: integer
Parameter EXTENSION_ZBA bound to: 1 - type: integer
Parameter EXTENSION_ZBB bound to: 1 - type: integer
Parameter EXTENSION_ZBC bound to: 1 - type: integer
Parameter EXTENSION_ZBS bound to: 1 - type: integer
Parameter EXTENSION_ZBKB bound to: 1 - type: integer
Parameter EXTENSION_ZCB bound to: 0 - type: integer
Parameter EXTENSION_ZCMP bound to: 0 - type: integer
Parameter EXTENSION_ZIFENCEI bound to: 0 - type: integer
Parameter EXTENSION_XH3BEXTM bound to: 0 - type: integer
Parameter EXTENSION_XH3IRQ bound to: 0 - type: integer
Parameter EXTENSION_XH3PMPM bound to: 0 - type: integer
Parameter EXTENSION_XH3POWER bound to: 0 - type: integer
Parameter CSR_M_MANDATORY bound to: 1 - type: integer
Parameter CSR_M_TRAP bound to: 1 - type: integer
Parameter CSR_COUNTER bound to: 0 - type: integer
Parameter U_MODE bound to: 0 - type: integer
Parameter PMP_REGIONS bound to: 0 - type: integer
Parameter PMP_GRAIN bound to: 0 - type: integer
Parameter PMP_HARDWIRED bound to: 0 - type: integer
Parameter PMP_HARDWIRED_ADDR bound to: 0 - type: integer
Parameter PMP_HARDWIRED_CFG bound to: 0 - type: integer
Parameter DEBUG_SUPPORT bound to: 1 - type: integer
Parameter BREAKPOINT_TRIGGERS bound to: 0 - type: integer
Parameter NUM_IRQS bound to: 1 - type: integer
Parameter IRQ_PRIORITY_BITS bound to: 0 - type: integer
Parameter IRQ_INPUT_BYPASS bound to: 1'b0
Parameter MVENDORID_VAL bound to: 0 - type: integer
Parameter MIMPID_VAL bound to: 0 - type: integer
Parameter MHARTID_VAL bound to: 0 - type: integer
Parameter MCONFIGPTR_VAL bound to: 0 - type: integer
Parameter REDUCED_BYPASS bound to: 0 - type: integer
Parameter MULDIV_UNROLL bound to: 1 - type: integer
Parameter MUL_FAST bound to: 0 - type: integer
Parameter MUL_FASTER bound to: 1 - type: integer
Parameter MULH_FAST bound to: 1 - type: integer
Parameter FAST_BRANCHCMP bound to: 1 - type: integer
Parameter RESET_REGFILE bound to: 0 - type: integer
Parameter BRANCH_PREDICTOR bound to: 1 - type: integer
Parameter MTVEC_WMASK bound to: -3 - type: integer
Parameter W_ADDR bound to: 32 - type: integer
Parameter W_DATA bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'hazard3_branchcmp' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_branchcmp.v:16]
INFO: [Synth 8-6157] synthesizing module 'hazard3_frontend' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_frontend.v:8]
Parameter RESET_VECTOR bound to: 0 - type: integer
Parameter MTVEC_INIT bound to: 0 - type: integer
Parameter EXTENSION_A bound to: 1 - type: integer
Parameter EXTENSION_C bound to: 1 - type: integer
Parameter EXTENSION_M bound to: 1 - type: integer
Parameter EXTENSION_ZBA bound to: 1 - type: integer
Parameter EXTENSION_ZBB bound to: 1 - type: integer
Parameter EXTENSION_ZBC bound to: 1 - type: integer
Parameter EXTENSION_ZBS bound to: 1 - type: integer
Parameter EXTENSION_ZBKB bound to: 1 - type: integer
Parameter EXTENSION_ZCB bound to: 0 - type: integer
Parameter EXTENSION_ZCMP bound to: 0 - type: integer
Parameter EXTENSION_ZIFENCEI bound to: 0 - type: integer
Parameter EXTENSION_XH3BEXTM bound to: 0 - type: integer
Parameter EXTENSION_XH3IRQ bound to: 0 - type: integer
Parameter EXTENSION_XH3PMPM bound to: 0 - type: integer
Parameter EXTENSION_XH3POWER bound to: 0 - type: integer
Parameter CSR_M_MANDATORY bound to: 1 - type: integer
Parameter CSR_M_TRAP bound to: 1 - type: integer
Parameter CSR_COUNTER bound to: 0 - type: integer
Parameter U_MODE bound to: 0 - type: integer
Parameter PMP_REGIONS bound to: 0 - type: integer
Parameter PMP_GRAIN bound to: 0 - type: integer
Parameter PMP_HARDWIRED bound to: 0 - type: integer
Parameter PMP_HARDWIRED_ADDR bound to: 0 - type: integer
Parameter PMP_HARDWIRED_CFG bound to: 0 - type: integer
Parameter DEBUG_SUPPORT bound to: 1 - type: integer
Parameter BREAKPOINT_TRIGGERS bound to: 0 - type: integer
Parameter NUM_IRQS bound to: 1 - type: integer
Parameter IRQ_PRIORITY_BITS bound to: 0 - type: integer
Parameter IRQ_INPUT_BYPASS bound to: 1'b0
Parameter MVENDORID_VAL bound to: 0 - type: integer
Parameter MIMPID_VAL bound to: 0 - type: integer
Parameter MHARTID_VAL bound to: 0 - type: integer
Parameter MCONFIGPTR_VAL bound to: 0 - type: integer
Parameter REDUCED_BYPASS bound to: 0 - type: integer
Parameter MULDIV_UNROLL bound to: 1 - type: integer
Parameter MUL_FAST bound to: 0 - type: integer
Parameter MUL_FASTER bound to: 1 - type: integer
Parameter MULH_FAST bound to: 1 - type: integer
Parameter FAST_BRANCHCMP bound to: 1 - type: integer
Parameter RESET_REGFILE bound to: 0 - type: integer
Parameter BRANCH_PREDICTOR bound to: 1 - type: integer
Parameter MTVEC_WMASK bound to: -3 - type: integer
Parameter W_ADDR bound to: 32 - type: integer
Parameter W_DATA bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'hazard3_frontend' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_frontend.v:8]
INFO: [Synth 8-6157] synthesizing module 'hazard3_decode' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_decode.v:8]
Parameter RESET_VECTOR bound to: 0 - type: integer
Parameter MTVEC_INIT bound to: 0 - type: integer
Parameter EXTENSION_A bound to: 1 - type: integer
Parameter EXTENSION_C bound to: 1 - type: integer
Parameter EXTENSION_M bound to: 1 - type: integer
Parameter EXTENSION_ZBA bound to: 1 - type: integer
Parameter EXTENSION_ZBB bound to: 1 - type: integer
Parameter EXTENSION_ZBC bound to: 1 - type: integer
Parameter EXTENSION_ZBS bound to: 1 - type: integer
Parameter EXTENSION_ZBKB bound to: 1 - type: integer
Parameter EXTENSION_ZCB bound to: 0 - type: integer
Parameter EXTENSION_ZCMP bound to: 0 - type: integer
Parameter EXTENSION_ZIFENCEI bound to: 0 - type: integer
Parameter EXTENSION_XH3BEXTM bound to: 0 - type: integer
Parameter EXTENSION_XH3IRQ bound to: 0 - type: integer
Parameter EXTENSION_XH3PMPM bound to: 0 - type: integer
Parameter EXTENSION_XH3POWER bound to: 0 - type: integer
Parameter CSR_M_MANDATORY bound to: 1 - type: integer
Parameter CSR_M_TRAP bound to: 1 - type: integer
Parameter CSR_COUNTER bound to: 0 - type: integer
Parameter U_MODE bound to: 0 - type: integer
Parameter PMP_REGIONS bound to: 0 - type: integer
Parameter PMP_GRAIN bound to: 0 - type: integer
Parameter PMP_HARDWIRED bound to: 0 - type: integer
Parameter PMP_HARDWIRED_ADDR bound to: 0 - type: integer
Parameter PMP_HARDWIRED_CFG bound to: 0 - type: integer
Parameter DEBUG_SUPPORT bound to: 1 - type: integer
Parameter BREAKPOINT_TRIGGERS bound to: 0 - type: integer
Parameter NUM_IRQS bound to: 1 - type: integer
Parameter IRQ_PRIORITY_BITS bound to: 0 - type: integer
Parameter IRQ_INPUT_BYPASS bound to: 1'b0
Parameter MVENDORID_VAL bound to: 0 - type: integer
Parameter MIMPID_VAL bound to: 0 - type: integer
Parameter MHARTID_VAL bound to: 0 - type: integer
Parameter MCONFIGPTR_VAL bound to: 0 - type: integer
Parameter REDUCED_BYPASS bound to: 0 - type: integer
Parameter MULDIV_UNROLL bound to: 1 - type: integer
Parameter MUL_FAST bound to: 0 - type: integer
Parameter MUL_FASTER bound to: 1 - type: integer
Parameter MULH_FAST bound to: 1 - type: integer
Parameter FAST_BRANCHCMP bound to: 1 - type: integer
Parameter RESET_REGFILE bound to: 0 - type: integer
Parameter BRANCH_PREDICTOR bound to: 1 - type: integer
Parameter MTVEC_WMASK bound to: -3 - type: integer
Parameter W_ADDR bound to: 32 - type: integer
Parameter W_DATA bound to: 32 - type: integer
INFO: [Synth 8-6157] synthesizing module 'hazard3_instr_decompress' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_instr_decompress.v:10]
Parameter RESET_VECTOR bound to: 0 - type: integer
Parameter MTVEC_INIT bound to: 0 - type: integer
Parameter EXTENSION_A bound to: 1 - type: integer
Parameter EXTENSION_C bound to: 1 - type: integer
Parameter EXTENSION_M bound to: 1 - type: integer
Parameter EXTENSION_ZBA bound to: 1 - type: integer
Parameter EXTENSION_ZBB bound to: 1 - type: integer
Parameter EXTENSION_ZBC bound to: 1 - type: integer
Parameter EXTENSION_ZBS bound to: 1 - type: integer
Parameter EXTENSION_ZBKB bound to: 1 - type: integer
Parameter EXTENSION_ZCB bound to: 0 - type: integer
Parameter EXTENSION_ZCMP bound to: 0 - type: integer
Parameter EXTENSION_ZIFENCEI bound to: 0 - type: integer
Parameter EXTENSION_XH3BEXTM bound to: 0 - type: integer
Parameter EXTENSION_XH3IRQ bound to: 0 - type: integer
Parameter EXTENSION_XH3PMPM bound to: 0 - type: integer
Parameter EXTENSION_XH3POWER bound to: 0 - type: integer
Parameter CSR_M_MANDATORY bound to: 1 - type: integer
Parameter CSR_M_TRAP bound to: 1 - type: integer
Parameter CSR_COUNTER bound to: 0 - type: integer
Parameter U_MODE bound to: 0 - type: integer
Parameter PMP_REGIONS bound to: 0 - type: integer
Parameter PMP_GRAIN bound to: 0 - type: integer
Parameter PMP_HARDWIRED bound to: 0 - type: integer
Parameter PMP_HARDWIRED_ADDR bound to: 0 - type: integer
Parameter PMP_HARDWIRED_CFG bound to: 0 - type: integer
Parameter DEBUG_SUPPORT bound to: 1 - type: integer
Parameter BREAKPOINT_TRIGGERS bound to: 0 - type: integer
Parameter NUM_IRQS bound to: 1 - type: integer
Parameter IRQ_PRIORITY_BITS bound to: 0 - type: integer
Parameter IRQ_INPUT_BYPASS bound to: 1'b0
Parameter MVENDORID_VAL bound to: 0 - type: integer
Parameter MIMPID_VAL bound to: 0 - type: integer
Parameter MHARTID_VAL bound to: 0 - type: integer
Parameter MCONFIGPTR_VAL bound to: 0 - type: integer
Parameter REDUCED_BYPASS bound to: 0 - type: integer
Parameter MULDIV_UNROLL bound to: 1 - type: integer
Parameter MUL_FAST bound to: 0 - type: integer
Parameter MUL_FASTER bound to: 1 - type: integer
Parameter MULH_FAST bound to: 1 - type: integer
Parameter FAST_BRANCHCMP bound to: 1 - type: integer
Parameter RESET_REGFILE bound to: 0 - type: integer
Parameter BRANCH_PREDICTOR bound to: 1 - type: integer
Parameter MTVEC_WMASK bound to: -3 - type: integer
Parameter W_ADDR bound to: 32 - type: integer
Parameter W_DATA bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'hazard3_instr_decompress' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_instr_decompress.v:10]
INFO: [Synth 8-6155] done synthesizing module 'hazard3_decode' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_decode.v:8]
INFO: [Synth 8-6157] synthesizing module 'hazard3_alu' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_alu.v:8]
Parameter RESET_VECTOR bound to: 0 - type: integer
Parameter MTVEC_INIT bound to: 0 - type: integer
Parameter EXTENSION_A bound to: 1 - type: integer
Parameter EXTENSION_C bound to: 1 - type: integer
Parameter EXTENSION_M bound to: 1 - type: integer
Parameter EXTENSION_ZBA bound to: 1 - type: integer
Parameter EXTENSION_ZBB bound to: 1 - type: integer
Parameter EXTENSION_ZBC bound to: 1 - type: integer
Parameter EXTENSION_ZBS bound to: 1 - type: integer
Parameter EXTENSION_ZBKB bound to: 1 - type: integer
Parameter EXTENSION_ZCB bound to: 0 - type: integer
Parameter EXTENSION_ZCMP bound to: 0 - type: integer
Parameter EXTENSION_ZIFENCEI bound to: 0 - type: integer
Parameter EXTENSION_XH3BEXTM bound to: 0 - type: integer
Parameter EXTENSION_XH3IRQ bound to: 0 - type: integer
Parameter EXTENSION_XH3PMPM bound to: 0 - type: integer
Parameter EXTENSION_XH3POWER bound to: 0 - type: integer
Parameter CSR_M_MANDATORY bound to: 1 - type: integer
Parameter CSR_M_TRAP bound to: 1 - type: integer
Parameter CSR_COUNTER bound to: 0 - type: integer
Parameter U_MODE bound to: 0 - type: integer
Parameter PMP_REGIONS bound to: 0 - type: integer
Parameter PMP_GRAIN bound to: 0 - type: integer
Parameter PMP_HARDWIRED bound to: 0 - type: integer
Parameter PMP_HARDWIRED_ADDR bound to: 0 - type: integer
Parameter PMP_HARDWIRED_CFG bound to: 0 - type: integer
Parameter DEBUG_SUPPORT bound to: 1 - type: integer
Parameter BREAKPOINT_TRIGGERS bound to: 0 - type: integer
Parameter NUM_IRQS bound to: 1 - type: integer
Parameter IRQ_PRIORITY_BITS bound to: 0 - type: integer
Parameter IRQ_INPUT_BYPASS bound to: 1'b0
Parameter MVENDORID_VAL bound to: 0 - type: integer
Parameter MIMPID_VAL bound to: 0 - type: integer
Parameter MHARTID_VAL bound to: 0 - type: integer
Parameter MCONFIGPTR_VAL bound to: 0 - type: integer
Parameter REDUCED_BYPASS bound to: 0 - type: integer
Parameter MULDIV_UNROLL bound to: 1 - type: integer
Parameter MUL_FAST bound to: 0 - type: integer
Parameter MUL_FASTER bound to: 1 - type: integer
Parameter MULH_FAST bound to: 1 - type: integer
Parameter FAST_BRANCHCMP bound to: 1 - type: integer
Parameter RESET_REGFILE bound to: 0 - type: integer
Parameter BRANCH_PREDICTOR bound to: 1 - type: integer
Parameter MTVEC_WMASK bound to: -3 - type: integer
Parameter W_ADDR bound to: 32 - type: integer
Parameter W_DATA bound to: 32 - type: integer
INFO: [Synth 8-6157] synthesizing module 'hazard3_shift_barrel' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_shift_barrel.v:12]
Parameter RESET_VECTOR bound to: 0 - type: integer
Parameter MTVEC_INIT bound to: 0 - type: integer
Parameter EXTENSION_A bound to: 1 - type: integer
Parameter EXTENSION_C bound to: 1 - type: integer
Parameter EXTENSION_M bound to: 1 - type: integer
Parameter EXTENSION_ZBA bound to: 1 - type: integer
Parameter EXTENSION_ZBB bound to: 1 - type: integer
Parameter EXTENSION_ZBC bound to: 1 - type: integer
Parameter EXTENSION_ZBS bound to: 1 - type: integer
Parameter EXTENSION_ZBKB bound to: 1 - type: integer
Parameter EXTENSION_ZCB bound to: 0 - type: integer
Parameter EXTENSION_ZCMP bound to: 0 - type: integer
Parameter EXTENSION_ZIFENCEI bound to: 0 - type: integer
Parameter EXTENSION_XH3BEXTM bound to: 0 - type: integer
Parameter EXTENSION_XH3IRQ bound to: 0 - type: integer
Parameter EXTENSION_XH3PMPM bound to: 0 - type: integer
Parameter EXTENSION_XH3POWER bound to: 0 - type: integer
Parameter CSR_M_MANDATORY bound to: 1 - type: integer
Parameter CSR_M_TRAP bound to: 1 - type: integer
Parameter CSR_COUNTER bound to: 0 - type: integer
Parameter U_MODE bound to: 0 - type: integer
Parameter PMP_REGIONS bound to: 0 - type: integer
Parameter PMP_GRAIN bound to: 0 - type: integer
Parameter PMP_HARDWIRED bound to: 0 - type: integer
Parameter PMP_HARDWIRED_ADDR bound to: 0 - type: integer
Parameter PMP_HARDWIRED_CFG bound to: 0 - type: integer
Parameter DEBUG_SUPPORT bound to: 1 - type: integer
Parameter BREAKPOINT_TRIGGERS bound to: 0 - type: integer
Parameter NUM_IRQS bound to: 1 - type: integer
Parameter IRQ_PRIORITY_BITS bound to: 0 - type: integer
Parameter IRQ_INPUT_BYPASS bound to: 1'b0
Parameter MVENDORID_VAL bound to: 0 - type: integer
Parameter MIMPID_VAL bound to: 0 - type: integer
Parameter MHARTID_VAL bound to: 0 - type: integer
Parameter MCONFIGPTR_VAL bound to: 0 - type: integer
Parameter REDUCED_BYPASS bound to: 0 - type: integer
Parameter MULDIV_UNROLL bound to: 1 - type: integer
Parameter MUL_FAST bound to: 0 - type: integer
Parameter MUL_FASTER bound to: 1 - type: integer
Parameter MULH_FAST bound to: 1 - type: integer
Parameter FAST_BRANCHCMP bound to: 1 - type: integer
Parameter RESET_REGFILE bound to: 0 - type: integer
Parameter BRANCH_PREDICTOR bound to: 1 - type: integer
Parameter MTVEC_WMASK bound to: -3 - type: integer
Parameter W_ADDR bound to: 32 - type: integer
Parameter W_DATA bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'hazard3_shift_barrel' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_shift_barrel.v:12]
INFO: [Synth 8-6157] synthesizing module 'hazard3_priority_encode' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_priority_encode.v:11]
Parameter W_REQ bound to: 32 - type: integer
Parameter HIGHEST_WINS bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'hazard3_onehot_priority' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_onehot_priority.v:12]
Parameter W_REQ bound to: 32 - type: integer
Parameter HIGHEST_WINS bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'hazard3_onehot_priority' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_onehot_priority.v:12]
INFO: [Synth 8-6157] synthesizing module 'hazard3_onehot_encode' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_onehot_encode.v:11]
Parameter W_REQ bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'hazard3_onehot_encode' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_onehot_encode.v:11]
INFO: [Synth 8-6155] done synthesizing module 'hazard3_priority_encode' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_priority_encode.v:11]
INFO: [Synth 8-6155] done synthesizing module 'hazard3_alu' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/arith/hazard3_alu.v:8]
INFO: [Synth 8-6157] synthesizing module 'hazard3_csr' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_csr.v:12]
Parameter XLEN bound to: 32 - type: integer
Parameter RESET_VECTOR bound to: 0 - type: integer
Parameter MTVEC_INIT bound to: 0 - type: integer
Parameter EXTENSION_A bound to: 1 - type: integer
Parameter EXTENSION_C bound to: 1 - type: integer
Parameter EXTENSION_M bound to: 1 - type: integer
Parameter EXTENSION_ZBA bound to: 1 - type: integer
Parameter EXTENSION_ZBB bound to: 1 - type: integer
Parameter EXTENSION_ZBC bound to: 1 - type: integer
Parameter EXTENSION_ZBS bound to: 1 - type: integer
Parameter EXTENSION_ZBKB bound to: 1 - type: integer
Parameter EXTENSION_ZCB bound to: 0 - type: integer
Parameter EXTENSION_ZCMP bound to: 0 - type: integer
Parameter EXTENSION_ZIFENCEI bound to: 0 - type: integer
Parameter EXTENSION_XH3BEXTM bound to: 0 - type: integer
Parameter EXTENSION_XH3IRQ bound to: 0 - type: integer
Parameter EXTENSION_XH3PMPM bound to: 0 - type: integer
Parameter EXTENSION_XH3POWER bound to: 0 - type: integer
Parameter CSR_M_MANDATORY bound to: 1 - type: integer
Parameter CSR_M_TRAP bound to: 1 - type: integer
Parameter CSR_COUNTER bound to: 0 - type: integer
Parameter U_MODE bound to: 0 - type: integer
Parameter PMP_REGIONS bound to: 0 - type: integer
Parameter PMP_GRAIN bound to: 0 - type: integer
Parameter PMP_HARDWIRED bound to: 0 - type: integer
Parameter PMP_HARDWIRED_ADDR bound to: 0 - type: integer
Parameter PMP_HARDWIRED_CFG bound to: 0 - type: integer
Parameter DEBUG_SUPPORT bound to: 1 - type: integer
Parameter BREAKPOINT_TRIGGERS bound to: 0 - type: integer
Parameter NUM_IRQS bound to: 1 - type: integer
Parameter IRQ_PRIORITY_BITS bound to: 0 - type: integer
Parameter IRQ_INPUT_BYPASS bound to: 1'b0
Parameter MVENDORID_VAL bound to: 0 - type: integer
Parameter MIMPID_VAL bound to: 0 - type: integer
Parameter MHARTID_VAL bound to: 0 - type: integer
Parameter MCONFIGPTR_VAL bound to: 0 - type: integer
Parameter REDUCED_BYPASS bound to: 0 - type: integer
Parameter MULDIV_UNROLL bound to: 1 - type: integer
Parameter MUL_FAST bound to: 0 - type: integer
Parameter MUL_FASTER bound to: 1 - type: integer
Parameter MULH_FAST bound to: 1 - type: integer
Parameter FAST_BRANCHCMP bound to: 1 - type: integer
Parameter RESET_REGFILE bound to: 0 - type: integer
Parameter BRANCH_PREDICTOR bound to: 1 - type: integer
Parameter MTVEC_WMASK bound to: -3 - type: integer
Parameter W_ADDR bound to: 32 - type: integer
Parameter W_DATA bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'hazard3_csr' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_csr.v:12]
INFO: [Synth 8-6157] synthesizing module 'hazard3_power_ctrl' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_power_ctrl.v:10]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_power_ctrl.v:74]
INFO: [Synth 8-6155] done synthesizing module 'hazard3_power_ctrl' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_power_ctrl.v:10]
INFO: [Synth 8-6157] synthesizing module 'hazard3_regfile_1w2r' [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_regfile_1w2r.v:11]
Parameter RESET_REGS bound to: 0 - type: integer
Parameter N_REGS bound to: 32 - type: integer
Parameter W_DATA bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'hazard3_regfile_1w2r' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_regfile_1w2r.v:11]
INFO: [Synth 8-6155] done synthesizing module 'hazard3_core' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_core.v:8]
INFO: [Synth 8-6155] done synthesizing module 'hazard3_cpu_1port' (0#1) [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_cpu_1port.v:12]
WARNING: [Synth 8-7071] port 'hmaster' of module 'hazard3_cpu_1port' is unconnected for instance 'cpu' [/eda/processor_ci/rtl/Hazard3.sv:229]
WARNING: [Synth 8-7023] instance 'cpu' of module 'hazard3_cpu_1port' has 46 connections declared, but only 45 given [/eda/processor_ci/rtl/Hazard3.sv:229]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/Hazard3.sv:7]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/rtl/reset.sv:1]
Parameter CYCLES bound to: 32'sb00000000000000000000000000010100
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/rtl/reset.sv:32]
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/rtl/reset.sv:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/internal/fpga_top.sv:98]
WARNING: [Synth 8-7071] port 'rst_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/internal/fpga_top.sv:98]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/internal/fpga_top.sv:98]
INFO: [Synth 8-6155] done synthesizing module 'fpga_top' (0#1) [/eda/processor_ci/internal/fpga_top.sv:8]
WARNING: [Synth 8-3848] Net intr_o in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:25]
WARNING: [Synth 8-3848] Net data_memory_ack in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:119]
WARNING: [Synth 8-3848] Net data_memory_read_data in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:120]
WARNING: [Synth 8-6014] Unused sequential element base_addr_reg was removed. [/eda/processor_ci/internal/ahblite_to_wishbone.sv:65]
WARNING: [Synth 8-7137] Register wb_wstrb_reg in module ahb_to_wishbone has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/eda/processor_ci/internal/ahblite_to_wishbone.sv:79]
WARNING: [Synth 8-7137] Register HRDATA_reg in module ahb_to_wishbone has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/eda/processor_ci/internal/ahblite_to_wishbone.sv:103]
WARNING: [Synth 8-3848] Net fifo_valid[2] in module/entity hazard3_frontend does not have driver. [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_frontend.v:121]
WARNING: [Synth 8-6014] Unused sequential element mcycleh_reg was removed. [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_csr.v:422]
WARNING: [Synth 8-6014] Unused sequential element mcycle_reg was removed. [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_csr.v:423]
WARNING: [Synth 8-6014] Unused sequential element minstreth_reg was removed. [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_csr.v:424]
WARNING: [Synth 8-6014] Unused sequential element minstret_reg was removed. [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_csr.v:425]
WARNING: [Synth 8-6014] Unused sequential element mcountinhibit_cy_reg was removed. [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_csr.v:427]
WARNING: [Synth 8-6014] Unused sequential element mcountinhibit_ir_reg was removed. [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_csr.v:428]
WARNING: [Synth 8-6014] Unused sequential element mcounteren_cy_reg was removed. [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_csr.v:460]
WARNING: [Synth 8-6014] Unused sequential element mcounteren_tm_reg was removed. [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_csr.v:461]
WARNING: [Synth 8-6014] Unused sequential element mcounteren_ir_reg was removed. [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_csr.v:462]
WARNING: [Synth 8-6014] Unused sequential element xm_rs1_reg was removed. [/var/jenkins_home/workspace/Hazard3/Hazard3/hdl/hazard3_core.v:1088]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/Hazard3.sv:20]
WARNING: [Synth 8-7129] Port rst_n in module hazard3_regfile_1w2r is either unconnected or has no load
WARNING: [Synth 8-7129] Port ren in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[31] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[30] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[29] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[28] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[27] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[26] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[25] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[24] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[23] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[22] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[21] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[20] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[19] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[18] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[17] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[16] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[15] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[14] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[13] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[12] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[11] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[10] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[9] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[8] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[7] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[6] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[5] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[4] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[3] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[2] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[1] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port pmp_cfg_rdata[0] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[31] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[30] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[29] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[28] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[27] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[26] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[25] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[24] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[23] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[22] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[21] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[20] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[19] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[18] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[17] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[16] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[15] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[14] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[13] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[12] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[11] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[10] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[9] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[8] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[7] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[6] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[5] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[4] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[3] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[2] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[1] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port trig_cfg_rdata[0] in module hazard3_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port req[0] in module hazard3_onehot_encode is either unconnected or has no load
WARNING: [Synth 8-7129] Port funct7_32b[6] in module hazard3_alu is either unconnected or has no load
WARNING: [Synth 8-7129] Port funct7_32b[5] in module hazard3_alu is either unconnected or has no load
WARNING: [Synth 8-7129] Port funct7_32b[4] in module hazard3_alu is either unconnected or has no load
WARNING: [Synth 8-7129] Port funct7_32b[0] in module hazard3_alu is either unconnected or has no load
WARNING: [Synth 8-7129] Port clk in module hazard3_instr_decompress is either unconnected or has no load
WARNING: [Synth 8-7129] Port rst_n in module hazard3_instr_decompress is either unconnected or has no load
WARNING: [Synth 8-7129] Port instr_out_uop_stall in module hazard3_instr_decompress is either unconnected or has no load
WARNING: [Synth 8-7129] Port instr_out_uop_clear in module hazard3_instr_decompress is either unconnected or has no load
WARNING: [Synth 8-7129] Port jump_target[0] in module hazard3_frontend is either unconnected or has no load
WARNING: [Synth 8-7129] Port jump_priv in module hazard3_frontend is either unconnected or has no load
WARNING: [Synth 8-7129] Port df_uop_step_next[3] in module hazard3_frontend is either unconnected or has no load
WARNING: [Synth 8-7129] Port df_uop_step_next[2] in module hazard3_frontend is either unconnected or has no load
WARNING: [Synth 8-7129] Port df_uop_step_next[1] in module hazard3_frontend is either unconnected or has no load
WARNING: [Synth 8-7129] Port df_uop_step_next[0] in module hazard3_frontend is either unconnected or has no load
WARNING: [Synth 8-7129] Port delay_first_fetch in module hazard3_frontend is either unconnected or has no load
WARNING: [Synth 8-7129] Port aluop[5] in module hazard3_branchcmp is either unconnected or has no load
WARNING: [Synth 8-7129] Port aluop[4] in module hazard3_branchcmp is either unconnected or has no load
WARNING: [Synth 8-7129] Port aluop[3] in module hazard3_branchcmp is either unconnected or has no load
WARNING: [Synth 8-7129] Port aluop[1] in module hazard3_branchcmp is either unconnected or has no load
WARNING: [Synth 8-7129] Port HTRANS[0] in module ahb_to_wishbone is either unconnected or has no load
WARNING: [Synth 8-7129] Port HPROT[3] in module ahb_to_wishbone is either unconnected or has no load
WARNING: [Synth 8-7129] Port HPROT[2] in module ahb_to_wishbone is either unconnected or has no load
WARNING: [Synth 8-7129] Port HPROT[1] in module ahb_to_wishbone is either unconnected or has no load
WARNING: [Synth 8-7129] Port HPROT[0] in module ahb_to_wishbone is either unconnected or has no load
WARNING: [Synth 8-7129] Port HLOCK in module ahb_to_wishbone is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[31] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[30] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[29] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[28] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[27] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[26] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[25] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[24] in module Memory is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2158.688 ; gain = 529.652 ; free physical = 1214 ; free virtual = 28376
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2173.531 ; gain = 544.496 ; free physical = 1219 ; free virtual = 28381
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2173.531 ; gain = 544.496 ; free physical = 1219 ; free virtual = 28381
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2173.531 ; gain = 0.000 ; free physical = 1219 ; free virtual = 28381
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2326.281 ; gain = 0.000 ; free physical = 1196 ; free virtual = 28358
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2326.316 ; gain = 0.000 ; free physical = 1196 ; free virtual = 28358
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2326.316 ; gain = 697.281 ; free physical = 1193 ; free virtual = 28355
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2326.316 ; gain = 697.281 ; free physical = 1193 ; free virtual = 28355
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2326.316 ; gain = 697.281 ; free physical = 1193 ; free virtual = 28355
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_read_fifo_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'hazard3_power_ctrl'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
READ | 001 | 0001
COPY_READ_BUFFER | 010 | 0100
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
COPY_WRITE_BUFFER | 001 | 0100
WRITE | 010 | 0101
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
TX_FIFO_IDLE | 0001 | 00
TX_FIFO_READ_FIFO | 0010 | 01
TX_FIFO_WRITE_TX | 0100 | 10
TX_FIFO_WAIT | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_read_fifo_state_reg' using encoding 'one-hot' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
S_AWAKE | 00 | 00
S_ENTER_ASLEEP | 01 | 01
S_ASLEEP | 10 | 10
S_ENTER_AWAKE | 11 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'hazard3_power_ctrl'
INFO: [Synth 8-3971] The signal "hazard3_regfile_1w2r:/real_dualport_noreset.mem_reg" was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
INIT | 001 | 00
RESET_COUNTER | 010 | 01
IDLE | 100 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 2326.316 ; gain = 697.281 ; free physical = 1186 ; free virtual = 28350
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 3
2 Input 33 Bit Adders := 1
2 Input 32 Bit Adders := 8
3 Input 32 Bit Adders := 3
2 Input 24 Bit Adders := 2
2 Input 10 Bit Adders := 2
2 Input 8 Bit Adders := 1
2 Input 6 Bit Adders := 1
32 Input 6 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 4
2 Input 3 Bit Adders := 8
4 Input 2 Bit Adders := 2
2 Input 2 Bit Adders := 1
3 Input 2 Bit Adders := 2
+---XORs :
32 Input 64 Bit XORs := 1
2 Input 32 Bit XORs := 5
2 Input 1 Bit XORs := 3
+---XORs :
2 Bit Wide XORs := 1
+---Registers :
64 Bit Registers := 3
32 Bit Registers := 28
24 Bit Registers := 4
16 Bit Registers := 1
10 Bit Registers := 2
8 Bit Registers := 11
6 Bit Registers := 2
5 Bit Registers := 6
4 Bit Registers := 5
3 Bit Registers := 12
2 Bit Registers := 13
1 Bit Registers := 84
+---RAMs :
64K Bit (2048 X 32 bit) RAMs := 1
1024 Bit (32 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 1
2 Input 64 Bit Muxes := 15
48 Input 64 Bit Muxes := 2
2 Input 63 Bit Muxes := 1
2 Input 48 Bit Muxes := 5
5 Input 32 Bit Muxes := 3
2 Input 32 Bit Muxes := 69
40 Input 32 Bit Muxes := 1
108 Input 32 Bit Muxes := 1
8 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 1
37 Input 32 Bit Muxes := 1
14 Input 32 Bit Muxes := 1
15 Input 32 Bit Muxes := 1
48 Input 24 Bit Muxes := 1
2 Input 16 Bit Muxes := 1
48 Input 8 Bit Muxes := 2
2 Input 8 Bit Muxes := 5
24 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 2
3 Input 6 Bit Muxes := 2
109 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 30
4 Input 5 Bit Muxes := 2
10 Input 5 Bit Muxes := 1
3 Input 5 Bit Muxes := 2
108 Input 5 Bit Muxes := 3
109 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 20
9 Input 4 Bit Muxes := 1
108 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
151 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 4
2 Input 3 Bit Muxes := 34
108 Input 3 Bit Muxes := 1
4 Input 3 Bit Muxes := 4
3 Input 3 Bit Muxes := 2
6 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 30
48 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 6
3 Input 2 Bit Muxes := 3
108 Input 2 Bit Muxes := 1
111 Input 2 Bit Muxes := 1
9 Input 2 Bit Muxes := 1
8 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 183
48 Input 1 Bit Muxes := 22
3 Input 1 Bit Muxes := 5
4 Input 1 Bit Muxes := 8
5 Input 1 Bit Muxes := 14
40 Input 1 Bit Muxes := 1
108 Input 1 Bit Muxes := 7
109 Input 1 Bit Muxes := 1
151 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-3971] The signal "\ptop/cpu/core/regs/real_dualport_noreset.mem_reg " was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:28 ; elapsed = 00:01:28 . Memory (MB): peak = 2352.172 ; gain = 723.137 ; free physical = 1047 ; free virtual = 28224
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1 | LUT |
|Interpreter | memory_mux_selector | 256x1 | LUT |
+------------+---------------------+---------------+----------------+
Block RAM: Preliminary Mapping Report (see note below)
-------NONE-------
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-------------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-------------------------------------------+-----------+----------------------+------------------+
|fpga_top | ptop/u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|fpga_top | ptop/u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|fpga_top | ptop/u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 |
+------------+-------------------------------------------+-----------+----------------------+------------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:33 ; elapsed = 00:01:33 . Memory (MB): peak = 2352.172 ; gain = 723.137 ; free physical = 1043 ; free virtual = 28219
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:39 ; elapsed = 00:01:39 . Memory (MB): peak = 2368.180 ; gain = 739.145 ; free physical = 1030 ; free virtual = 28206
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
-------NONE-------
Distributed RAM: Final Mapping Report
+------------+-------------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-------------------------------------------+-----------+----------------------+------------------+
|fpga_top | ptop/u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|fpga_top | ptop/u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|fpga_top | ptop/u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 |
+------------+-------------------------------------------+-----------+----------------------+------------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
WARNING: [Synth 8-3332] Sequential element (ptop/cpu/core/power_ctrl/FSM_sequential_state_reg[1]) is unused and will be removed from module fpga_top.
WARNING: [Synth 8-3332] Sequential element (ptop/cpu/core/power_ctrl/FSM_sequential_state_reg[0]) is unused and will be removed from module fpga_top.
INFO: [Synth 8-7052] The timing for the instance ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance ptop/cpu/core/regs/real_dualport_noreset.mem_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:44 ; elapsed = 00:01:44 . Memory (MB): peak = 2531.180 ; gain = 902.145 ; free physical = 859 ; free virtual = 28035
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:48 ; elapsed = 00:01:48 . Memory (MB): peak = 2531.180 ; gain = 902.145 ; free physical = 865 ; free virtual = 28041
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:48 ; elapsed = 00:01:48 . Memory (MB): peak = 2531.180 ; gain = 902.145 ; free physical = 865 ; free virtual = 28041
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:48 ; elapsed = 00:01:49 . Memory (MB): peak = 2531.180 ; gain = 902.145 ; free physical = 865 ; free virtual = 28041
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:48 ; elapsed = 00:01:49 . Memory (MB): peak = 2531.180 ; gain = 902.145 ; free physical = 865 ; free virtual = 28041
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:48 ; elapsed = 00:01:49 . Memory (MB): peak = 2531.180 ; gain = 902.145 ; free physical = 852 ; free virtual = 28028
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:48 ; elapsed = 00:01:49 . Memory (MB): peak = 2531.180 ; gain = 902.145 ; free physical = 851 ; free virtual = 28027
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 3|
|2 |CARRY4 | 183|
|3 |LUT1 | 68|
|4 |LUT2 | 540|
|5 |LUT3 | 701|
|6 |LUT4 | 682|
|7 |LUT5 | 1127|
|8 |LUT6 | 1904|
|9 |MUXF7 | 65|
|10 |RAM256X1S | 256|
|11 |RAM32M | 2|
|12 |RAM32X1D | 4|
|13 |RAMB18E1 | 2|
|14 |FDCE | 632|
|15 |FDPE | 12|
|16 |FDRE | 724|
|17 |FDSE | 4|
|18 |IBUF | 2|
|19 |OBUF | 1|
|20 |OBUFT | 2|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:48 ; elapsed = 00:01:49 . Memory (MB): peak = 2531.180 ; gain = 902.145 ; free physical = 848 ; free virtual = 28024
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 112 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:45 ; elapsed = 00:01:46 . Memory (MB): peak = 2531.180 ; gain = 749.359 ; free physical = 858 ; free virtual = 28034
Synthesis Optimization Complete : Time (s): cpu = 00:01:49 ; elapsed = 00:01:49 . Memory (MB): peak = 2531.188 ; gain = 902.145 ; free physical = 858 ; free virtual = 28034
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2531.188 ; gain = 0.000 ; free physical = 1140 ; free virtual = 28316
INFO: [Netlist 29-17] Analyzing 512 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2627.227 ; gain = 0.000 ; free physical = 1140 ; free virtual = 28316
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 262 instances were transformed.
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: c0bcad7f
INFO: [Common 17-83] Releasing license: Synthesis
96 Infos, 137 Warnings, 2 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:58 ; elapsed = 00:01:56 . Memory (MB): peak = 2627.262 ; gain = 1307.266 ; free physical = 1140 ; free virtual = 28316
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2195.700; main = 2072.637; forked = 429.173
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3350.535; main = 2627.230; forked = 982.352
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2691.258 ; gain = 63.996 ; free physical = 1141 ; free virtual = 28317
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 25d22a2bc
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2723.273 ; gain = 32.016 ; free physical = 1328 ; free virtual = 28504
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 25d22a2bc
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2809.086 ; gain = 0.000 ; free physical = 1132 ; free virtual = 28309
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 25d22a2bc
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2809.086 ; gain = 0.000 ; free physical = 1132 ; free virtual = 28309
Phase 1 Initialization | Checksum: 25d22a2bc
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2809.086 ; gain = 0.000 ; free physical = 1132 ; free virtual = 28309
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 25d22a2bc
Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2809.086 ; gain = 0.000 ; free physical = 1132 ; free virtual = 28309
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 25d22a2bc
Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2809.086 ; gain = 0.000 ; free physical = 1131 ; free virtual = 28308
Phase 2 Timer Update And Timing Data Collection | Checksum: 25d22a2bc
Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2809.086 ; gain = 0.000 ; free physical = 1131 ; free virtual = 28308
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 24 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 16ff97eb4
Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2809.086 ; gain = 0.000 ; free physical = 1131 ; free virtual = 28308
Retarget | Checksum: 16ff97eb4
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 2 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 21a16048d
Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2809.086 ; gain = 0.000 ; free physical = 1131 ; free virtual = 28307
Constant propagation | Checksum: 21a16048d
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 194591922
Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2809.086 ; gain = 0.000 ; free physical = 1131 ; free virtual = 28307
Sweep | Checksum: 194591922
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 194591922
Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2841.102 ; gain = 32.016 ; free physical = 1131 ; free virtual = 28307
BUFG optimization | Checksum: 194591922
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 194591922
Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2841.102 ; gain = 32.016 ; free physical = 1131 ; free virtual = 28307
Shift Register Optimization | Checksum: 194591922
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 194591922
Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2841.102 ; gain = 32.016 ; free physical = 1131 ; free virtual = 28307
Post Processing Netlist | Checksum: 194591922
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 21da24ae1
Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2841.102 ; gain = 32.016 ; free physical = 1122 ; free virtual = 28298
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2841.102 ; gain = 0.000 ; free physical = 1120 ; free virtual = 28296
Phase 9.2 Verifying Netlist Connectivity | Checksum: 21da24ae1
Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2841.102 ; gain = 32.016 ; free physical = 1120 ; free virtual = 28296
Phase 9 Finalization | Checksum: 21da24ae1
Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2841.102 ; gain = 32.016 ; free physical = 1120 ; free virtual = 28296
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 2 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 21da24ae1
Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.54 . Memory (MB): peak = 2841.102 ; gain = 32.016 ; free physical = 1120 ; free virtual = 28296
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2841.102 ; gain = 0.000 ; free physical = 1119 ; free virtual = 28295
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 2 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 4
Ending PowerOpt Patch Enables Task | Checksum: 21da24ae1
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1022 ; free virtual = 28198
Ending Power Optimization Task | Checksum: 21da24ae1
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3049.180 ; gain = 208.078 ; free physical = 1022 ; free virtual = 28198
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 21da24ae1
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1022 ; free virtual = 28198
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1022 ; free virtual = 28198
Ending Netlist Obfuscation Task | Checksum: 21da24ae1
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1022 ; free virtual = 28198
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 3049.180 ; gain = 421.918 ; free physical = 1022 ; free virtual = 28198
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 21 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1021 ; free virtual = 28197
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12c89b65b
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1021 ; free virtual = 28197
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1021 ; free virtual = 28197
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 195a66640
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1016 ; free virtual = 28192
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1bf05b279
Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1017 ; free virtual = 28193
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1bf05b279
Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1017 ; free virtual = 28193
Phase 1 Placer Initialization | Checksum: 1bf05b279
Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1017 ; free virtual = 28193
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 247e80818
Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1011 ; free virtual = 28187
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 224784228
Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1011 ; free virtual = 28187
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 224784228
Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1011 ; free virtual = 28187
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 16b4c0722
Time (s): cpu = 00:00:16 ; elapsed = 00:00:05 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1003 ; free virtual = 28179
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 288 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 101 nets or LUTs. Breaked 0 LUT, combined 101 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1004 ; free virtual = 28180
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 101 | 101 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 101 | 101 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 17e90b522
Time (s): cpu = 00:00:17 ; elapsed = 00:00:06 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1004 ; free virtual = 28180
Phase 2.4 Global Placement Core | Checksum: 105d965c4
Time (s): cpu = 00:00:18 ; elapsed = 00:00:07 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1002 ; free virtual = 28178
Phase 2 Global Placement | Checksum: 105d965c4
Time (s): cpu = 00:00:18 ; elapsed = 00:00:07 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1002 ; free virtual = 28178
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 12254213a
Time (s): cpu = 00:00:18 ; elapsed = 00:00:07 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 997 ; free virtual = 28173
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 219c6c1b0
Time (s): cpu = 00:00:19 ; elapsed = 00:00:07 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1004 ; free virtual = 28180
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1bf713eee
Time (s): cpu = 00:00:19 ; elapsed = 00:00:07 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 996 ; free virtual = 28172
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 23f56e22d
Time (s): cpu = 00:00:19 ; elapsed = 00:00:07 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1003 ; free virtual = 28179
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 2018e1623
Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28181
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1fd73702d
Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28181
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 27dcda2ee
Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28181
Phase 3 Detail Placement | Checksum: 27dcda2ee
Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28181
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 260953a21
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.875 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 2955e0267
Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 2955e0267
Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
Phase 4.1.1.1 BUFG Insertion | Checksum: 260953a21
Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.875. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1a9b652ac
Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
Phase 4.1 Post Commit Optimization | Checksum: 1a9b652ac
Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1a9b652ac
Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 1x1|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 2x2|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1a9b652ac
Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
Phase 4.3 Placer Reporting | Checksum: 1a9b652ac
Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1a903f0a5
Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
Ending Placer Task | Checksum: 1a3930bda
Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:12 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
# report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
# report_utilization -file digilent_arty_a7_utilization_place.rpt
# report_io -file digilent_arty_a7_io.rpt
report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28182
# report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 1005 ; free virtual = 28181
# report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: e89dca52 ConstDB: 0 ShapeSum: baf54188 RouteDB: 0
Post Restoration Checksum: NetGraph: aa5ad007 | NumContArr: 98fd7e67 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2c8aa43a8
Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 993 ; free virtual = 28169
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2c8aa43a8
Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 993 ; free virtual = 28169
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2c8aa43a8
Time (s): cpu = 00:00:35 ; elapsed = 00:00:26 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 993 ; free virtual = 28169
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 1b2ca1d58
Time (s): cpu = 00:00:41 ; elapsed = 00:00:28 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 992 ; free virtual = 28168
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 |
Router Utilization Summary
Global Vertical Routing Utilization = 0.00657179 %
Global Horizontal Routing Utilization = 0.0121483 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 5924
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 5887
Number of Partially Routed Nets = 37
Number of Node Overlaps = 14
Phase 2 Router Initialization | Checksum: 23164b8a7
Time (s): cpu = 00:00:44 ; elapsed = 00:00:28 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 992 ; free virtual = 28168
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 23164b8a7
Time (s): cpu = 00:00:44 ; elapsed = 00:00:28 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 992 ; free virtual = 28168
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 2647d6e8a
Time (s): cpu = 00:00:47 ; elapsed = 00:00:29 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 992 ; free virtual = 28168
Phase 3 Initial Routing | Checksum: 2647d6e8a
Time (s): cpu = 00:00:47 ; elapsed = 00:00:29 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 992 ; free virtual = 28168
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 585
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.245 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 2efdb68a5
Time (s): cpu = 00:00:52 ; elapsed = 00:00:31 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28167
Phase 4 Rip-up And Reroute | Checksum: 2efdb68a5
Time (s): cpu = 00:00:52 ; elapsed = 00:00:31 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28167
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 2efdb68a5
Time (s): cpu = 00:00:52 ; elapsed = 00:00:31 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28167
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 2efdb68a5
Time (s): cpu = 00:00:52 ; elapsed = 00:00:31 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28167
Phase 5 Delay and Skew Optimization | Checksum: 2efdb68a5
Time (s): cpu = 00:00:52 ; elapsed = 00:00:31 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28167
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 3023aabfe
Time (s): cpu = 00:00:52 ; elapsed = 00:00:31 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28167
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.341 | TNS=0.000 | WHS=0.445 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 3023aabfe
Time (s): cpu = 00:00:52 ; elapsed = 00:00:31 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28167
Phase 6 Post Hold Fix | Checksum: 3023aabfe
Time (s): cpu = 00:00:52 ; elapsed = 00:00:31 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28167
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 1.27279 %
Global Horizontal Routing Utilization = 1.63697 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 3023aabfe
Time (s): cpu = 00:00:52 ; elapsed = 00:00:31 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28167
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 3023aabfe
Time (s): cpu = 00:00:53 ; elapsed = 00:00:31 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28166
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 23dda330f
Time (s): cpu = 00:00:54 ; elapsed = 00:00:31 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28166
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.341 | TNS=0.000 | WHS=0.445 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 23dda330f
Time (s): cpu = 00:00:54 ; elapsed = 00:00:32 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28166
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 1ec6d9da5
Time (s): cpu = 00:00:54 ; elapsed = 00:00:32 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28166
Ending Routing Task | Checksum: 1ec6d9da5
Time (s): cpu = 00:00:54 ; elapsed = 00:00:32 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 990 ; free virtual = 28166
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:33 . Memory (MB): peak = 3049.180 ; gain = 0.000 ; free physical = 985 ; free virtual = 28161
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (23159)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (14124)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (23159)
----------------------------
There are 2423 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[0]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[10]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[11]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[12]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[13]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[14]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[15]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[16]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[17]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[18]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[19]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[1]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[20]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[21]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[22]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[23]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[24]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[25]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[26]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[27]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[28]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[29]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[2]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[30]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[31]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[3]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[4]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[5]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[6]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[7]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[8]/Q (HIGH)
There are 648 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[9]/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (14124)
----------------------------------------------------
There are 14124 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (1)
-------------------------------
There is 1 port with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.365 0.000 0 1 0.461 0.000 0 1 4.500 0.000 0 2
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sck {0.000 50.000} 100.000 10.000
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.365 0.000 0 1 0.461 0.000 0 1 4.500 0.000 0 2
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_arty_a7_route_status.rpt
# report_drc -file digilent_arty_a7_drc.rpt
Command: report_drc -file digilent_arty_a7_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/Hazard3/Hazard3/digilent_arty_a7_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_arty_a7_power.rpt
Command: report_power -file digilent_arty_a7_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "digilent_arty_a7_100t.bit"
Command: write_bitstream -force digilent_arty_a7_100t.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/frontend/cir_reg[31]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/frontend/fifo_mem_reg[0][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/frontend/fifo_mem_reg[0][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/mw_result_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/mw_result_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/mw_result_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[18]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[21]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[22]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[24]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[25]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[27]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[28]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[29]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1 has an input control pin ptop/cpu/core/regs/real_dualport_noreset.mem_reg_1/ADDRARDADDR[9] (net: ptop/cpu/core/regs/raddr2[4]) which is driven by a register (ptop/cpu/core/xm_result_reg[30]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 22 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_arty_a7_100t.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 22 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 3189.402 ; gain = 140.223 ; free physical = 696 ; free virtual = 27876
# exit
INFO: [Common 17-206] Exiting Vivado at Sun Nov 16 00:46:51 2025...
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Hazard3/Hazard3
[Pipeline] {
[Pipeline] echo
Flashing FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Hazard3 -b digilent_arty_a7_100t -l
Makefile executed successfully.
Makefile output:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit
empty
Jtag frequency : requested 10.00MHz -> real 10.00MHz
Open file DONE
Parse file DONE
load program
Load SRAM: [================ ] 31.00%
Load SRAM: [================================ ] 63.00%
Load SRAM: [================================================ ] 95.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
[Pipeline] echo
Testing FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyUSB1
Test for FPGA in /dev/ttyUSB1
[Pipeline] sh
+ python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459
32
Connected to FPGA with ID: b'ARTY'
Checking for sync keyword...
Sync keyword matched.
Testsuite configurated.
Running tests: RV32I in /eda/processor_ci_tests/tests/RV32I
Running basic tests in /eda/processor_ci_tests/tests/RV32I/basic, with breakpoint 60
Running test: 000-addi.hex
Running test: 001-sw.hex
Running test: 002-slti.hex
Running test: 003-sltiu.hex
Running test: 004-xori.hex
Running test: 005-ori.hex
Running test: 006-andi.hex
Running test: 007-slli.hex
Running test: 008-srli.hex
Running test: 009-srai.hex
Running test: 010-lui.hex
Running test: 011-auipc.hex
Running test: 012-jal.hex
Running test: 013-jalr.hex
Running test: 014-beq.hex
Running test: 015-bne.hex
Running test: 016-blt.hex
Running test: 017-bge.hex
Running test: 018-bltu.hex
Running test: 019-bgeu.hex
Running test: 020-lb.hex
Running test: 021-lh.hex
Running test: 022-lw.hex
Running test: 023-lbu.hex
Running test: 024-lhu.hex
Running test: 025-sb.hex
Running test: 026-sh.hex
Running test: 027-add.hex
Running test: 028-sub.hex
Running test: 029-sll.hex
Running test: 030-slt.hex
Running test: 031-sltu.hex
Running test: 032-xor.hex
Running test: 033-srl.hex
Running test: 034-sra.hex
Running test: 035-or.hex
Running test: 036-and.hex
Running test: 037-fence.hex
Running test: 038-ecall.hex
Running test: 039-ebreak.hex
Running test: 040-timeout.hex
Running test: 041-forwarding.hex
Running test: 042-forwarding-lw.hex
JUnit XML report generated: test_results_1763272026.1366696.xml
All tests finished.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: UNSTABLE
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