Skip to content
[Jenkins]Jenkins
log in
StepArgumentsStatus
Start of Pipeline - (21 min in block)
node - (21 min in block)
node block - (1 min 4 sec in block)
stage - (12 sec in block)Git Clone
stage block (Git Clone) - (11 sec in block)
sh - (0.81 sec in self)rm -rf I2SRV32-V-v1
sh - (10 sec in self)git clone --recursive --depth=1 https://github.com/RClabiisc/I2SRV32-V-v1 I2SRV32-V-v1
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.94 sec in block)
dir - (0.59 sec in block)I2SRV32-V-v1
dir block - (0.32 sec in block)
echo - (0.11 sec in self)simulation not supported for mixed VHDL and Verilog files
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.88 sec in block)I2SRV32-V-v1
dir block - (0.61 sec in block)
sh - (0.41 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (48 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (47 sec in block)
parallel - (47 sec in block)
parallel block (Branch: colorlight_i9) - (50 ms in block)
stage - (7.3 sec in block)colorlight_i9
stage block (colorlight_i9) - (7 sec in block)
lock - (6.2 sec in block)colorlight_i9
lock block - (5.6 sec in block)
stage - (2.9 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.3 sec in block)
dir - (1.6 sec in block)I2SRV32-V-v1
dir block - (1.3 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.65 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p I2SRV32-V-v1 -b colorlight_i9
stage - (0.97 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.38 sec in block)
getContext - (0.16 sec in self)
stage - (0.76 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.44 sec in block)
getContext - (0.22 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (46 sec in block)
stage - (45 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (45 sec in block)
lock - (44 sec in block)digilent_nexys4_ddr
lock block - (43 sec in block)
stage - (41 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (41 sec in block)
dir - (40 sec in block)I2SRV32-V-v1
dir block - (40 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (39 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p I2SRV32-V-v1 -b digilent_nexys4_ddr
stage - (0.95 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.38 sec in block)
getContext - (0.16 sec in self)
stage - (0.68 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.73 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.48 sec in block)
junit - (0.24 sec in self)**/test-reports/*.xml