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Start of Pipeline - (20 min in block)
node - (20 min in block)
node block - (1 min 5 sec in block)
stage - (12 sec in block)Git Clone
stage block (Git Clone) - (11 sec in block)
sh - (1.1 sec in self)rm -rf I2SRV32-V-v1
sh - (10 sec in self)git clone --recursive --depth=1 https://github.com/RClabiisc/I2SRV32-V-v1 I2SRV32-V-v1
stage - (1.3 sec in block)Simulation
stage block (Simulation) - (0.91 sec in block)
dir - (0.56 sec in block)I2SRV32-V-v1
dir block - (0.32 sec in block)
echo - (0.11 sec in self)simulation not supported for mixed VHDL and Verilog files
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.3 sec in block)
dir - (0.96 sec in block)I2SRV32-V-v1
dir block - (0.66 sec in block)
sh - (0.43 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (48 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (47 sec in block)
parallel - (47 sec in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (7.2 sec in block)colorlight_i9
stage block (colorlight_i9) - (6.9 sec in block)
lock - (6.1 sec in block)colorlight_i9
lock block - (5.5 sec in block)
stage - (3.1 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.5 sec in block)
dir - (1.7 sec in block)I2SRV32-V-v1
dir block - (1.4 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.85 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p I2SRV32-V-v1 -b colorlight_i9
stage - (0.96 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (0.64 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.35 sec in block)
getContext - (0.15 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (46 sec in block)
stage - (46 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (45 sec in block)
lock - (44 sec in block)digilent_nexys4_ddr
lock block - (44 sec in block)
stage - (41 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (40 sec in block)
dir - (40 sec in block)I2SRV32-V-v1
dir block - (39 sec in block)
echo - (0.35 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (39 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p I2SRV32-V-v1 -b digilent_nexys4_ddr
stage - (1.1 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.34 sec in block)
getContext - (0.15 sec in self)
stage - (1 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.52 sec in block)
getContext - (0.17 sec in self)
stage - (0.72 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.49 sec in block)
junit - (0.25 sec in self)**/test-reports/*.xml