Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s fpga/board/PXIe/rtl/addr_mapper.v fpga/board/PXIe/rtl/system_top.v fpga/board/axu3cg/rtl/addr_mapper.v fpga/board/axu3cg/rtl/system_top.v fpga/board/axu3cg/rtl/hdmi/i2c_config.v fpga/board/axu3cg/rtl/hdmi/i2c_master_bit_ctrl.v fpga/board/axu3cg/rtl/hdmi/i2c_master_byte_ctrl.v fpga/board/axu3cg/rtl/hdmi/i2c_master_defines.v fpga/board/axu3cg/rtl/hdmi/i2c_master_top.v fpga/board/axu3cg/rtl/hdmi/timescale.v difftest/src/test/vsrc/common/SimJTAG.v difftest/src/test/vsrc/common/assert.v difftest/src/test/vsrc/common/ref.v difftest/src/test/vsrc/vcs/DeferredControl.v difftest/src/test/vsrc/vcs/DifftestEndpoint.v difftest/src/test/vsrc/vcs/top.v
fpga/board/PXIe/rtl/system_top.v:2: Include file axi.vh not found
Preprocessor failed with 1 errors.