Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/NutShell
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf *.xml
[Pipeline] sh
+ rm -rf NutShell
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/OSCPU/NutShell NutShell
Cloning into 'NutShell'...
Submodule 'difftest' (https://github.com/OpenXiangShan/difftest.git) registered for path 'difftest'
Cloning into '/var/jenkins_home/workspace/NutShell/NutShell/difftest'...
Submodule path 'difftest': checked out '9b058bd01a349c715ed83aadd9a4dadbd7b0f4e9'
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/NutShell/NutShell
[Pipeline] {
[Pipeline] echo
FPGA > Simulation
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/NutShell/NutShell
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/NutShell/NutShell -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/NutShell/NutShell/fpga/board/PXIe/rtl/addr_mapper.v
Trying to read file: /var/jenkins_home/workspace/NutShell/NutShell/fpga/board/PXIe/rtl/addr_mapper.v
Trying to read file: /var/jenkins_home/workspace/NutShell/NutShell/fpga/board/PXIe/rtl/system_top.v
Trying to read file: /var/jenkins_home/workspace/NutShell/NutShell/fpga/board/axu3cg/rtl/addr_mapper.v
Trying to read file: /var/jenkins_home/workspace/NutShell/NutShell/fpga/board/axu3cg/rtl/system_top.v
Trying to read file: /var/jenkins_home/workspace/NutShell/NutShell/fpga/board/axu3cg/rtl/hdmi/i2c_config.v
Trying to read file: /var/jenkins_home/workspace/NutShell/NutShell/fpga/board/axu3cg/rtl/hdmi/i2c_master_bit_ctrl.v
Trying to read file: /var/jenkins_home/workspace/NutShell/NutShell/fpga/board/axu3cg/rtl/hdmi/i2c_master_byte_ctrl.v
Trying to read file: /var/jenkins_home/workspace/NutShell/NutShell/fpga/board/axu3cg/rtl/hdmi/i2c_master_defines.v
Trying to read file: /var/jenkins_home/workspace/NutShell/NutShell/fpga/board/axu3cg/rtl/hdmi/i2c_master_top.v
Trying to read file: /var/jenkins_home/workspace/NutShell/NutShell/fpga/board/axu3cg/rtl/hdmi/timescale.v
Results saved to /jenkins/processor_ci_utils/labels/NutShell.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
The resource [digilent_arty_a7_100t] is locked by build cv32e40p #539 #539 since Apr 12, 2026, 4:01 AM.
[Resource: digilent_arty_a7_100t] is not free, waiting for execution ...
[Required resources: [digilent_arty_a7_100t]] added into queue at position 0
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/NutShell/NutShell
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p NutShell -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/NutShell/NutShell/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'axi.vh' [/var/jenkins_home/workspace/NutShell/NutShell/fpga/board/PXIe/rtl/system_top.v:1]
ERROR: [Synth 8-9263] cannot open include file 'axi.vh' [/var/jenkins_home/workspace/NutShell/NutShell/fpga/board/axu3cg/rtl/system_top.v:1]
ERROR: [Synth 8-10157] use of undefined macro 'axi_slave_if' [/var/jenkins_home/workspace/NutShell/NutShell/fpga/board/PXIe/rtl/addr_mapper.v:2]
ERROR: [Synth 8-2716] syntax error near '(' [/var/jenkins_home/workspace/NutShell/NutShell/fpga/board/PXIe/rtl/addr_mapper.v:2]
ERROR: [Synth 8-439] module 'uart_rx' not found [/eda/processor-ci-controller/modules/uart.sv:260]
ERROR: [Synth 8-6156] failed synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/NutShell.sv:7]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_top' [/eda/processor_ci/internal/fpga_top.sv:8]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 299, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE