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Start of Pipeline - (17 min in block)
node - (17 min in block)
node block - (5 min 13 sec in block)
stage - (2.4 sec in block)Git Clone
stage block (Git Clone) - (1.8 sec in block)
sh - (0.57 sec in self)rm -rf Pequeno-Risco-5
sh - (0.92 sec in self)git clone --recursive --depth=1 https://github.com/JN513/Pequeno-Risco-5 Pequeno-Risco-5
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.89 sec in block)Pequeno-Risco-5
dir block - (0.63 sec in block)
sh - (0.42 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s Core src/alu.v src/alu_control.v src/control_unit.v src/core.v src/immediate_generator.v src/mux.v src/pc.v src/registers.v src/instruction_memory.v src/data_memory.v
stage - (1.6 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.86 sec in block)Pequeno-Risco-5
dir block - (0.61 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (5 min 6 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 min 6 sec in block)
parallel - (5 min 5 sec in block)
parallel block (Branch: colorlight_i9) - (51 ms in block)
stage - (4 min 14 sec in block)colorlight_i9
stage block (colorlight_i9) - (4 min 13 sec in block)
lock - (4 min 13 sec in block)colorlight_i9
lock block - (4 min 12 sec in block)
stage - (3 min 53 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (3 min 53 sec in block)
dir - (3 min 52 sec in block)Pequeno-Risco-5
dir block - (3 min 52 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (3 min 51 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Pequeno-Risco-5 -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)Pequeno-Risco-5
dir block - (15 sec in block)
echo - (0.17 sec in self)Flashing FPGA colorlight_i9.
sh - (15 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Pequeno-Risco-5 -b colorlight_i9 -l
stage - (1.6 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.4 sec in block)
echo - (0.2 sec in self)Testing FPGA colorlight_i9.
dir - (0.87 sec in block)Pequeno-Risco-5
dir block - (0.63 sec in block)
sh - (0.42 sec in self)echo "Test for FPGA in /dev/ttyACM0"
parallel block (Branch: digilent_nexys4_ddr) - (5 min 5 sec in block)
stage - (5 min 4 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (5 min 4 sec in block)
lock - (5 min 3 sec in block)digilent_nexys4_ddr
lock block - (5 min 3 sec in block)
stage - (4 min 53 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (4 min 53 sec in block)
dir - (4 min 52 sec in block)Pequeno-Risco-5
dir block - (4 min 52 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (4 min 51 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Pequeno-Risco-5 -b digilent_nexys4_ddr
stage - (7 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (6.6 sec in block)
dir - (6.2 sec in block)Pequeno-Risco-5
dir block - (5.9 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_nexys4_ddr.
sh - (5.5 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Pequeno-Risco-5 -b digilent_nexys4_ddr -l
stage - (1.6 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (1.3 sec in block)
echo - (0.23 sec in self)Testing FPGA digilent_nexys4_ddr.
dir - (0.86 sec in block)Pequeno-Risco-5
dir block - (0.6 sec in block)
sh - (0.41 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
stage - (0.77 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.53 sec in block)
junit - (0.28 sec in self)**/test-reports/*.xml