Console Output

+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Piccolo -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/Piccolo/Piccolo/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-36] 'TASK_testplusargs___d11' is not declared [/var/jenkins_home/workspace/Piccolo/Piccolo/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v:162]
ERROR: [Synth 8-36] 'TASK_testplusargs___d12' is not declared [/var/jenkins_home/workspace/Piccolo/Piccolo/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v:164]
ERROR: [Synth 8-439] module 'uart_rx' not found [/eda/processor-ci-controller/modules/uart.sv:260]
ERROR: [Synth 8-6156] failed synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/Piccolo.sv:7]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_top' [/eda/processor_ci/internal/fpga_top.sv:8]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 299, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.