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Start of Pipeline - (42 sec in block)
node - (41 sec in block)
node block - (41 sec in block)
stage - (2.5 sec in block)Git Clone
stage block (Git Clone) - (2.1 sec in block)
sh - (0.47 sec in self)rm -rf *.xml
sh - (0.47 sec in self)rm -rf RISC-V
sh - (0.92 sec in self)git clone --recursive --depth=1 https://github.com/yavuz650/RISC-V RISC-V
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.87 sec in block)RISC-V
dir block - (0.64 sec in block)
sh - (0.42 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s core core/ALU.v core/control_unit.v core/core.v core/core_wb.v core/csr_unit.v core/forwarding_unit.v core/hazard_detection_unit.v core/imm_decoder.v core/load_store_unit.v core/muldiv/MULDIV_ctrl.v core/muldiv/MULDIV_in.v core/muldiv/MULDIV_top.v core/muldiv/MUL_DIV_out.v core/muldiv/divider_32.v core/muldiv/multiplier_32.v
stage - (1.6 sec in block)Utilities
stage block (Utilities) - (1.1 sec in block)
dir - (0.83 sec in block)RISC-V
dir block - (0.59 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (34 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (33 sec in block)
parallel - (33 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (32 sec in block)
stage - (32 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (31 sec in block)
lock - (31 sec in block)digilent_arty_a7_100t
lock block - (30 sec in block)
stage - (28 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (28 sec in block)
dir - (27 sec in block)RISC-V
dir block - (27 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (26 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p RISC-V -b digilent_arty_a7_100t
stage - (0.95 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.17 sec in self)
stage - (0.7 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.15 sec in self)
stage - (0.78 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.54 sec in block)
junit - (0.3 sec in self)**/*.xml