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Start of Pipeline - (5 days 21 hr in block)
node - (5 days 21 hr in block)
node block - (5 days 21 hr in block)
stage - (2.5 sec in block)Git Clone
stage block (Git Clone) - (2 sec in block)
sh - (0.44 sec in self)rm -rf *.xml
sh - (0.44 sec in self)rm -rf RISC-V
sh - (0.9 sec in self)git clone --recursive --depth=1 https://github.com/yavuz650/RISC-V RISC-V
stage - (1.3 sec in block)Simulation
stage block (Simulation) - (0.91 sec in block)
dir - (0.53 sec in block)RISC-V
dir block - (0.31 sec in block)
echo - (0.11 sec in self)FPGA > Simulation
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.89 sec in block)RISC-V
dir block - (0.61 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (5 days 21 hr in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 days 21 hr in block)
parallel - (5 days 21 hr in block)
parallel block (Branch: digilent_arty_a7_100t) - (5 days 21 hr in block)
stage - (5 days 21 hr in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (5 days 21 hr in block)
lock - (5 days 21 hr in block)digilent_arty_a7_100t
lock block - (5 days 21 hr in block)
stage - (3 min 8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (3 min 7 sec in block)
dir - (3 min 7 sec in block)RISC-V
dir block - (3 min 7 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (3 min 6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p RISC-V -b digilent_arty_a7_100t
stage - (5 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.6 sec in block)
dir - (4.2 sec in block)RISC-V
dir block - (4 sec in block)
echo - (0.15 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p RISC-V -b digilent_arty_a7_100t -l
stage - (5 days 21 hr in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (5 days 21 hr in block)
echo - (0.15 sec in self)Testing FPGA digilent_arty_a7_100t.
sh - (0.46 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (5 days 21 hr in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459 -ctm
stage - (1.3 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1 sec in block)
junit - (0.51 sec in self)**/*.xml