Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s RS5 -I rtl/ rtl/CSRBank.sv rtl/RS5.sv rtl/aes_unit.sv rtl/align.sv rtl/decode.sv rtl/decompresser.sv rtl/div.sv rtl/execute.sv rtl/fetch.sv rtl/mmu.sv rtl/mul.sv rtl/mulNbits.sv rtl/regbank.sv rtl/retire.sv rtl/vectorALU.sv rtl/vectorCSRs.sv rtl/vectorLSU.sv rtl/vectorRegbank.sv rtl/vectorUnit.sv rtl/aes/riscv_crypto_aes_fwd_sbox.sv rtl/aes/riscv_crypto_aes_sbox.sv rtl/aes/riscv_crypto_sbox_aes_out.sv rtl/aes/riscv_crypto_sbox_aes_top.sv rtl/aes/riscv_crypto_sbox_inv_mid.sv
rtl/align.sv: No such file or directory
rtl/CSRBank.sv:689: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:690: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:691: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:692: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:693: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:694: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:695: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:696: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:697: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:698: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:699: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:700: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:703: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:707: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:709: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:714: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:715: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:716: sorry: "inside" expressions not supported yet.
rtl/CSRBank.sv:718: sorry: "inside" expressions not supported yet.