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Start of Pipeline - (46 sec in block)
node - (44 sec in block)
node block - (44 sec in block)
stage - (9.9 sec in block)Git Clone
stage block (Git Clone) - (9.4 sec in block)
sh - (0.63 sec in self)rm -rf *.xml
sh - (4.8 sec in self)rm -rf RS5
sh - (3.5 sec in self)git clone --recursive --depth=1 https://github.com/gaph-pucrs/RS5 RS5
stage - (2.4 sec in block)Simulation
stage block (Simulation) - (1.6 sec in block)
dir - (1 sec in block)RS5
dir block - (0.59 sec in block)
echo - (0.2 sec in self)FPGA > Simulation
stage - (30 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (29 sec in block)
parallel - (29 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (27 sec in block)
stage - (26 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (26 sec in block)
lock - (25 sec in block)digilent_arty_a7_100t
lock block - (23 sec in block)
stage - (21 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (20 sec in block)
dir - (20 sec in block)RS5
dir block - (19 sec in block)
echo - (0.32 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (19 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p RS5 -b digilent_arty_a7_100t
stage - (0.99 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.4 sec in block)
getContext - (0.21 sec in self)
stage - (0.65 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.81 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.54 sec in block)
junit - (0.26 sec in self)**/*.xml