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Start of Pipeline - (1 min 10 sec in block)
node - (1 min 10 sec in block)
node block - (1 min 9 sec in block)
stage - (6.6 sec in block)Git Clone
stage block (Git Clone) - (5.7 sec in block)
sh - (0.75 sec in self)rm -rf *.xml
sh - (1.2 sec in self)rm -rf RS5
sh - (3.4 sec in self)git clone --recursive --depth=1 https://github.com/gaph-pucrs/RS5 RS5
stage - (2.5 sec in block)Simulation
stage block (Simulation) - (1.6 sec in block)
dir - (1 sec in block)RS5
dir block - (0.55 sec in block)
echo - (0.17 sec in self)FPGA > Simulation
stage - (58 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (58 sec in block)
parallel - (57 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (57 sec in block)
stage - (56 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (56 sec in block)
lock - (55 sec in block)digilent_arty_a7_100t
lock block - (23 sec in block)
stage - (20 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (20 sec in block)
dir - (19 sec in block)RS5
dir block - (19 sec in block)
echo - (0.3 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (18 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p RS5 -b digilent_arty_a7_100t
stage - (0.9 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.34 sec in block)
getContext - (0.15 sec in self)
stage - (0.64 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.34 sec in block)
getContext - (0.15 sec in self)
stage - (0.72 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.51 sec in block)
junit - (0.27 sec in self)**/*.xml