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5. #272
7. Pipeline Steps

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Step	Arguments			Status
Start of Pipeline - (15 min in block)
node - (15 min in block)
node block - (3 min 24 sec in block)
stage - (4.9 sec in block)	Git Clone
stage block (Git Clone) - (4.2 sec in block)
sh - (0.5 sec in self)	rm -rf *.xml
sh - (0.55 sec in self)	rm -rf RV12
sh - (2.8 sec in self)	git clone --recursive --depth=1 https://github.com/roalogic/RV12 RV12
stage - (1.5 sec in block)	Simulation
stage block (Simulation) - (1 sec in block)
dir - (0.59 sec in block)	RV12
dir block - (0.31 sec in block)
echo - (0.1 sec in self)	FPGA > Simulation
stage - (1.8 sec in block)	Utilities
stage block (Utilities) - (1.3 sec in block)
dir - (0.94 sec in block)	RV12
dir block - (0.67 sec in block)
sh - (0.46 sec in self)	python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (3 min 14 sec in block)	FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (3 min 13 sec in block)
parallel - (3 min 13 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (3 min 13 sec in block)
stage - (3 min 12 sec in block)	digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3 min 12 sec in block)
lock - (3 min 11 sec in block)	digilent_arty_a7_100t
stage - (0.9 sec in block)	Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.66 sec in block)
junit - (0.38 sec in self)	**/*.xml