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Start of Pipeline - (33 sec in block)
node - (32 sec in block)
node block - (32 sec in block)
stage - (3 sec in block)Git Clone
stage block (Git Clone) - (2.6 sec in block)
sh - (0.48 sec in self)rm -rf *.xml
sh - (0.66 sec in self)rm -rf RV32IC-CPU
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/djzenma/RV32IC-CPU RV32IC-CPU
stage - (1.3 sec in block)Simulation
stage block (Simulation) - (0.93 sec in block)
dir - (0.59 sec in block)RV32IC-CPU
dir block - (0.34 sec in block)
echo - (0.1 sec in self)FPGA > Simulation
stage - (1.6 sec in block)Utilities
stage block (Utilities) - (1.1 sec in block)
dir - (0.82 sec in block)RV32IC-CPU
dir block - (0.58 sec in block)
sh - (0.38 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (25 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (24 sec in block)
parallel - (24 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (23 sec in block)
stage - (23 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (23 sec in block)
lock - (22 sec in block)digilent_arty_a7_100t
lock block - (21 sec in block)
stage - (20 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (19 sec in block)
dir - (19 sec in block)RV32IC-CPU
dir block - (18 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (18 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p RV32IC-CPU -b digilent_arty_a7_100t
stage - (0.9 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.16 sec in self)
stage - (0.65 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.71 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.5 sec in block)
junit - (0.25 sec in self)**/*.xml