Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/ReonV
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf *.xml
[Pipeline] sh
+ rm -rf ReonV
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/lcbcFoo/ReonV ReonV
Cloning into 'ReonV'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/ReonV/ReonV
[Pipeline] {
[Pipeline] echo
FPGA > Simulation
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/ReonV/ReonV
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/ReonV/ReonV -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
WARNING: Error reading file /var/jenkins_home/workspace/ReonV/ReonV/lib/micron/sdram/mobile_sdr.v with encoding utf-8: 'utf-8' codec can't decode byte 0xa9 in position 2048: invalid start byte
Trying to read file: /var/jenkins_home/workspace/ReonV/ReonV/bin/altera/altera_mf.vhd
Trying to read file: /var/jenkins_home/workspace/ReonV/ReonV/bin/altera/altera_mf.vhd
Trying to read file: /var/jenkins_home/workspace/ReonV/ReonV/boards/altera-c5ekit/ddr3ctrl1.vhd
Cache-related signals in i2c_slave_model.v
Results saved to /jenkins/processor_ci_utils/labels/ReonV.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
Resource [digilent_arty_a7_100t] did not exist. Created.
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/ReonV/ReonV
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p ReonV -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/ReonV/ReonV/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGCANIO# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/can/can_mc.in.vhd:4]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGCANIO# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/can/can_oc.in.vhd:3]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGMIGHMASK# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/ddr/mig.in.vhd:7]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGI2C2AHBADDRH# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/i2c/i2c2ahb.in.vhd:4]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGI2C2AHBADDRL# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/i2c/i2c2ahb.in.vhd:5]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGI2C2AHBMASKH# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/i2c/i2c2ahb.in.vhd:6]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGI2C2AHBMASKL# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/i2c/i2c2ahb.in.vhd:7]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGI2C2AHBSADDR# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/i2c/i2c2ahb.in.vhd:9]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGI2C2AHBCADDR# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/i2c/i2c2ahb.in.vhd:10]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGL2MAP# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/l2cache/l2c.in.vhd:11]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGIURSTADDR# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/leon3/leon3.in.vhd:9]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGICACHELRSTART# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/leon3/leon3.in.vhd:23]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGCACHEFIXED# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/leon3/leon3.in.vhd:32]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGDCACHELRSTART# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/leon3/leon3.in.vhd:34]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGIURSTADDR# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/leon4/leon4.in.vhd:8]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGICACHELRSTART# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/leon4/leon4.in.vhd:21]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGCACHEFIXED# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/leon4/leon4.in.vhd:30]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGBWMASK# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/leon4/leon4.in.vhd:31]
ERROR: [Synth 8-10655] digit 'O' is larger than the base of 16#CONFIGDCACHELRSTART# [/var/jenkins_home/workspace/ReonV/ReonV/lib/gaisler/leon4/leon4.in.vhd:34]
ERROR: [Synth 8-4169] error in use clause: package 'config' not found in library 'grlib' [/var/jenkins_home/workspace/ReonV/ReonV/lib/techmap/gencomp/gencomp.vhd:30]
ERROR: [Synth 8-4169] error in use clause: package 'config_types' not found in library 'grlib' [/var/jenkins_home/workspace/ReonV/ReonV/lib/techmap/gencomp/gencomp.vhd:31]
ERROR: [Synth 8-36] 'grlib_config_array' is not declared [/var/jenkins_home/workspace/ReonV/ReonV/lib/techmap/gencomp/gencomp.vhd:536]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 299, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE