Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 8611/43848 19%
Info: logic LUTs: 5275/43848 12%
Info: carry LUTs: 264/43848 0%
Info: RAM LUTs: 2048/ 5481 37%
Info: RAMW LUTs: 1024/10962 9%
Info: Total DFFs: 1291/43848 2%
Info: Packing IOs..
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 281 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk_o to global network
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xfaf76d07
Info: Device utilisation:
Info: TRELLIS_IO: 12/ 245 4%
Info: DCCA: 2/ 56 3%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1291/43848 2%
Info: TRELLIS_COMB: 8661/43848 19%
Info: TRELLIS_RAMW: 512/ 5481 9%
Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 5305 cells, random placement wirelen = 444515.
Info: at initial placer iter 0, wirelen = 1320
Info: at initial placer iter 1, wirelen = 1038
Info: at initial placer iter 2, wirelen = 1082
Info: at initial placer iter 3, wirelen = 936
Info: Running main analytical placer, max placement attempts per cell = 13723560.
Info: at iteration #1, type ALL: wirelen solved = 961, spread = 68048, legal = 68745; time = 0.29s
Info: at iteration #2, type ALL: wirelen solved = 4905, spread = 44545, legal = 45793; time = 0.29s
Info: at iteration #3, type ALL: wirelen solved = 8713, spread = 41070, legal = 42221; time = 0.28s
Info: at iteration #4, type ALL: wirelen solved = 12815, spread = 38092, legal = 39133; time = 0.27s
Info: at iteration #5, type ALL: wirelen solved = 14635, spread = 37450, legal = 38437; time = 0.25s
Info: at iteration #6, type ALL: wirelen solved = 16157, spread = 38228, legal = 39006; time = 0.27s
Info: at iteration #7, type ALL: wirelen solved = 18029, spread = 38428, legal = 39177; time = 0.26s
Info: at iteration #8, type ALL: wirelen solved = 18862, spread = 38400, legal = 38997; time = 0.26s
Info: at iteration #9, type ALL: wirelen solved = 20033, spread = 38220, legal = 38792; time = 0.27s
Info: at iteration #10, type ALL: wirelen solved = 21137, spread = 40093, legal = 40547; time = 0.25s
Info: HeAP Placer Time: 4.69s
Info: of which solving equations: 2.99s
Info: of which spreading cells: 0.34s
Info: of which strict legalisation: 0.10s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 19969, wirelen = 38437
Info: at iteration #5: temp = 0.000000, timing cost = 12504, wirelen = 30712
Info: at iteration #10: temp = 0.000000, timing cost = 10721, wirelen = 29012
Info: at iteration #15: temp = 0.000000, timing cost = 12887, wirelen = 28280
Info: at iteration #20: temp = 0.000000, timing cost = 11755, wirelen = 27455
Info: at iteration #25: temp = 0.000000, timing cost = 11218, wirelen = 27199
Info: at iteration #30: temp = 0.000000, timing cost = 11544, wirelen = 27075
Info: at iteration #33: temp = 0.000000, timing cost = 10626, wirelen = 27040
Info: SA placement time 32.16s
Info: Max frequency for clock '$glbnet$clk_o': 28.59 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 161.55 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 10.02 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 9.64 ns
Info: Max delay posedge $glbnet$clk_o -> <async> : 11.80 ns
Info: Slack histogram:
Info: legend: * represents 88 endpoint(s)
Info: + represents [1,88) endpoint(s)
Info: [ 33810, 36249) |+
Info: [ 36249, 38688) |+
Info: [ 38688, 41127) |+
Info: [ 41127, 43566) |
Info: [ 43566, 46005) |
Info: [ 46005, 48444) |+
Info: [ 48444, 50883) |+
Info: [ 50883, 53322) |+
Info: [ 53322, 55761) |+
Info: [ 55761, 58200) |********+
Info: [ 58200, 60639) |***************
Info: [ 60639, 63078) |************************************************************
Info: [ 63078, 65517) |******************************************************+
Info: [ 65517, 67956) |******+
Info: [ 67956, 70395) |******+
Info: [ 70395, 72834) |*+
Info: [ 72834, 75273) |***+
Info: [ 75273, 77712) |********+
Info: [ 77712, 80151) |**+
Info: [ 80151, 82590) |+
Info: Checksum: 0x4f49a00b
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: routing clock net $glbnet$clk_o using global 1
Info: Routing..
Info: Setting up routing queue.
Info: Routing 42443 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 100 899 | 100 899 | 41633| 0.62 0.62|
Info: 2000 | 265 1734 | 165 835 | 40991| 0.15 0.77|
Info: 3000 | 372 2627 | 107 893 | 40672| 0.14 0.91|
Info: 4000 | 517 3482 | 145 855 | 40221| 0.15 1.06|
Info: 5000 | 672 4327 | 155 845 | 39630| 0.16 1.22|
Info: 6000 | 828 5171 | 156 844 | 39200| 0.16 1.38|
Info: 7000 | 918 6081 | 90 910 | 39004| 0.14 1.52|
Info: 8000 | 1044 6955 | 126 874 | 38559| 0.15 1.67|
Info: 9000 | 1282 7717 | 238 762 | 38229| 0.16 1.83|
Info: 10000 | 1469 8530 | 187 813 | 37842| 0.17 2.00|
Info: 11000 | 1633 9366 | 164 836 | 37627| 0.18 2.17|
Info: 12000 | 1750 10249 | 117 883 | 37635| 0.16 2.33|
Info: 13000 | 1922 11077 | 172 828 | 36991| 0.17 2.50|
Info: 14000 | 2064 11935 | 142 858 | 36751| 0.17 2.67|
Info: 15000 | 2267 12732 | 203 797 | 36398| 0.19 2.87|
Info: 16000 | 2420 13579 | 153 847 | 36108| 0.19 3.05|
Info: 17000 | 2601 14398 | 181 819 | 35949| 0.17 3.22|
Info: 18000 | 2788 15211 | 187 813 | 35346| 0.18 3.41|
Info: 19000 | 2930 16069 | 142 858 | 35657| 0.19 3.59|
Info: 20000 | 3084 16915 | 154 846 | 35388| 0.19 3.79|
Info: 21000 | 3299 17700 | 215 785 | 34958| 0.19 3.97|
Info: 22000 | 3526 18473 | 227 773 | 34805| 0.19 4.17|
Info: 23000 | 3692 19307 | 166 834 | 34489| 0.19 4.35|
Info: 24000 | 3812 20187 | 120 880 | 34227| 0.17 4.53|
Info: 25000 | 4015 20984 | 203 797 | 33672| 0.19 4.71|
Info: 26000 | 4172 21827 | 157 843 | 33507| 0.19 4.90|
Info: 27000 | 4282 22717 | 110 890 | 33379| 0.17 5.07|
Info: 28000 | 4300 23699 | 18 982 | 33579| 0.15 5.22|
Info: 29000 | 4341 24658 | 41 959 | 33542| 0.17 5.39|
Info: 30000 | 4500 25499 | 159 841 | 33009| 0.18 5.57|
Info: 31000 | 4749 26250 | 249 751 | 32616| 0.20 5.77|
Info: 32000 | 5039 26960 | 290 710 | 32628| 0.24 6.00|
Info: 33000 | 5150 27849 | 111 889 | 32870| 0.18 6.18|
Info: 34000 | 5258 28741 | 108 892 | 32816| 0.19 6.38|
Info: 35000 | 5452 29547 | 194 806 | 32217| 0.19 6.57|
Info: 36000 | 5707 30292 | 255 745 | 31781| 0.20 6.77|
Info: 37000 | 5984 31015 | 277 723 | 31415| 0.21 6.98|
Info: 38000 | 6205 31794 | 221 779 | 30867| 0.19 7.17|
Info: 39000 | 6501 32498 | 296 704 | 30599| 0.22 7.39|
Info: 40000 | 6743 33256 | 242 758 | 30188| 0.20 7.59|
Info: 41000 | 7061 33938 | 318 682 | 30012| 0.24 7.83|
Info: 42000 | 7267 34732 | 206 794 | 29669| 0.21 8.04|
Info: 43000 | 7462 35537 | 195 805 | 29272| 0.20 8.24|
Info: 44000 | 7550 36449 | 88 912 | 29280| 0.21 8.45|
Info: 45000 | 7848 37151 | 298 702 | 28903| 0.22 8.67|
Info: 46000 | 8140 37859 | 292 708 | 28743| 0.25 8.92|
Info: 47000 | 8364 38635 | 224 776 | 28744| 0.21 9.14|
Info: 48000 | 8490 39509 | 126 874 | 28591| 0.20 9.34|
Info: 49000 | 8751 40248 | 261 739 | 28276| 0.25 9.59|
Info: 50000 | 9073 40926 | 322 678 | 28150| 0.23 9.82|
Info: 51000 | 9270 41729 | 197 803 | 28232| 0.23 10.05|
Info: 52000 | 9393 42606 | 123 877 | 28075| 0.18 10.23|
Info: 53000 | 9583 43416 | 190 810 | 27880| 0.19 10.42|
Info: 54000 | 9833 44166 | 250 750 | 27629| 0.21 10.63|
Info: 55000 | 10159 44840 | 326 674 | 27325| 0.24 10.86|
Info: 56000 | 10441 45558 | 282 718 | 27186| 0.24 11.11|
Info: 57000 | 10805 46194 | 364 636 | 27146| 0.28 11.39|
Info: 58000 | 11065 46934 | 260 740 | 26814| 0.26 11.65|
Info: 59000 | 11396 47603 | 331 669 | 26556| 0.31 11.96|
Info: 60000 | 11743 48256 | 347 653 | 26373| 0.28 12.23|
Info: 61000 | 12018 48981 | 275 725 | 26263| 0.23 12.46|
Info: 62000 | 12239 49760 | 221 779 | 25921| 0.21 12.67|
Info: 63000 | 12523 50476 | 284 716 | 25687| 0.23 12.91|
Info: 64000 | 12828 51171 | 305 695 | 25333| 0.24 13.15|
Info: 65000 | 13137 51862 | 309 691 | 25024| 0.26 13.41|
Info: 66000 | 13385 52614 | 248 752 | 24759| 0.22 13.63|
Info: 67000 | 13695 53304 | 310 690 | 24624| 0.27 13.90|
Info: 68000 | 13995 54004 | 300 700 | 24339| 0.27 14.17|
Info: 69000 | 14381 54618 | 386 614 | 24098| 0.28 14.45|
Info: 70000 | 14611 55388 | 230 770 | 23919| 0.26 14.70|
Info: 71000 | 14836 56163 | 225 775 | 23661| 0.24 14.94|
Info: 72000 | 15246 56753 | 410 590 | 23457| 0.37 15.31|
Info: 73000 | 15533 57466 | 287 713 | 23323| 0.27 15.59|
Info: 74000 | 15824 58175 | 291 709 | 22965| 0.25 15.84|
Info: 75000 | 16235 58764 | 411 589 | 22701| 0.26 16.09|
Info: 76000 | 16594 59405 | 359 641 | 22343| 0.28 16.38|
Info: 77000 | 16889 60110 | 295 705 | 22276| 0.26 16.63|
Info: 78000 | 17023 60976 | 134 866 | 22751| 0.23 16.86|
Info: 79000 | 17172 61827 | 149 851 | 22193| 0.24 17.11|
Info: 80000 | 17509 62490 | 337 663 | 21979| 0.27 17.38|
Info: 81000 | 17825 63174 | 316 684 | 21868| 0.28 17.66|
Info: 82000 | 18196 63803 | 371 629 | 21744| 0.33 17.98|
Info: 83000 | 18603 64396 | 407 593 | 21430| 0.27 18.25|
Info: 84000 | 19012 64987 | 409 591 | 21149| 0.29 18.54|
Info: 85000 | 19406 65593 | 394 606 | 20750| 0.27 18.81|
Info: 86000 | 19716 66283 | 310 690 | 20702| 0.27 19.08|
Info: 87000 | 19963 67036 | 247 753 | 20679| 0.24 19.32|
Info: 88000 | 20150 67849 | 187 813 | 20992| 0.25 19.57|
Info: 89000 | 20447 68552 | 297 703 | 20553| 0.24 19.81|
Info: 90000 | 20789 69210 | 342 658 | 20345| 0.26 20.07|
Info: 91000 | 21160 69839 | 371 629 | 20770| 0.26 20.32|
Info: 92000 | 21258 70741 | 98 902 | 20878| 0.23 20.56|
Info: 93000 | 21408 71591 | 150 850 | 20360| 0.24 20.79|
Info: 94000 | 21807 72192 | 399 601 | 20074| 0.26 21.05|
Info: 95000 | 22224 72775 | 417 583 | 19985| 0.26 21.31|
Info: 96000 | 22511 73488 | 287 713 | 19775| 0.25 21.56|
Info: 97000 | 22935 74064 | 424 576 | 19629| 0.26 21.82|
Info: 98000 | 23427 74572 | 492 508 | 19444| 0.29 22.11|
Info: 99000 | 23886 75113 | 459 541 | 19269| 0.25 22.37|
Info: 100000 | 24313 75686 | 427 573 | 19046| 0.28 22.65|
Info: 101000 | 24728 76271 | 415 585 | 18796| 0.27 22.91|
Info: 102000 | 24958 77041 | 230 770 | 18905| 0.25 23.17|
Info: 103000 | 25306 77693 | 348 652 | 18678| 0.29 23.46|
Info: 104000 | 25795 78204 | 489 511 | 18361| 0.27 23.73|
Info: 105000 | 26295 78704 | 500 500 | 18094| 0.27 24.00|
Info: 106000 | 26758 79241 | 463 537 | 17911| 0.29 24.29|
Info: 107000 | 27187 79812 | 429 571 | 17838| 0.28 24.57|
Info: 108000 | 27728 80271 | 541 459 | 17654| 0.29 24.86|
Info: 109000 | 28158 80841 | 430 570 | 17579| 0.29 25.15|
Info: 110000 | 28632 81367 | 474 526 | 17391| 0.25 25.40|
Info: 111000 | 29167 81832 | 535 465 | 17254| 0.26 25.66|
Info: 112000 | 29723 82276 | 556 444 | 17125| 0.26 25.92|
Info: 113000 | 30173 82826 | 450 550 | 16916| 0.27 26.18|
Info: 114000 | 30644 83355 | 471 529 | 16780| 0.26 26.44|
Info: 115000 | 31192 83807 | 548 452 | 16552| 0.25 26.69|
Info: 116000 | 31668 84331 | 476 524 | 16314| 0.25 26.94|
Info: 117000 | 32020 84979 | 352 648 | 16183| 0.25 27.19|
Info: 118000 | 32531 85468 | 511 489 | 15954| 0.27 27.46|
Info: 119000 | 32972 86027 | 441 559 | 15764| 0.35 27.81|
Info: 120000 | 33459 86540 | 487 513 | 15532| 0.28 28.09|
Info: 121000 | 33934 87037 | 475 497 | 15327| 0.36 28.45|
Info: 122000 | 34328 87640 | 394 603 | 15272| 0.31 28.76|
Info: 123000 | 34876 88081 | 548 441 | 15074| 0.30 29.06|
Info: 124000 | 35413 88523 | 537 442 | 14907| 0.27 29.33|
Info: 125000 | 36059 88822 | 646 299 | 14634| 0.26 29.59|
Info: 126000 | 36633 89228 | 574 406 | 14476| 0.31 29.89|
Info: 127000 | 37256 89575 | 623 347 | 14260| 0.28 30.18|
Info: 128000 | 37858 89928 | 602 353 | 13976| 0.24 30.41|
Info: 129000 | 38401 90354 | 543 426 | 13770| 0.27 30.69|
Info: 130000 | 38936 90781 | 535 427 | 13517| 0.26 30.95|
Info: 131000 | 39494 91147 | 558 366 | 13185| 0.24 31.19|
Info: 132000 | 39934 91629 | 440 482 | 12855| 0.27 31.46|
Info: 133000 | 40386 92105 | 452 476 | 12499| 0.23 31.70|
Info: 134000 | 40744 92673 | 358 568 | 12146| 0.29 31.99|
Info: 135000 | 41040 93291 | 296 618 | 11561| 0.23 32.21|
Info: 136000 | 41162 94083 | 122 792 | 10738| 0.15 32.36|
Info: 137000 | 41265 94944 | 103 861 | 9879| 0.14 32.51|
Info: 138000 | 41377 95810 | 112 866 | 9043| 0.13 32.63|
Info: 139000 | 41444 96733 | 67 923 | 8155| 0.12 32.75|
Info: 140000 | 41607 97562 | 163 829 | 7483| 0.21 32.97|
Info: 141000 | 41684 98475 | 77 913 | 6570| 0.12 33.08|
Info: 142000 | 41892 99261 | 208 786 | 6019| 0.24 33.32|
Info: 143000 | 41980 100170 | 88 909 | 5120| 0.13 33.45|
Info: 144000 | 42069 101077 | 89 907 | 4222| 0.14 33.59|
Info: 145000 | 42335 101785 | 266 708 | 3653| 0.24 33.83|
Info: 146000 | 42712 102406 | 377 621 | 3137| 0.30 34.13|
Info: 147000 | 43133 102977 | 421 571 | 2643| 0.29 34.42|
Info: 148000 | 43572 103529 | 439 552 | 2440| 0.39 34.81|
Info: 149000 | 44036 104044 | 464 515 | 1994| 0.32 35.13|
Info: 150000 | 44497 104576 | 461 532 | 1670| 0.32 35.45|
Info: 151000 | 44910 105159 | 413 583 | 1296| 0.32 35.76|
Info: 152000 | 45430 105638 | 520 479 | 1072| 0.36 36.13|
Info: 153000 | 45937 106130 | 507 492 | 810| 0.39 36.52|
Info: 154000 | 46493 106565 | 556 435 | 489| 0.35 36.86|
Info: 154535 | 46528 106777 | 35 212 | 0| 0.15 37.02|
Info: Routing complete.
Info: Router1 time 37.02s
Info: Checksum: 0xc396483f
Info: Critical path report for clock '$glbnet$clk_o' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_2.Q
Info: 0.9 1.5 Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_D_LUT4_Z_D_LUT4_D_Z_LUT4_Z_B[2] (29,43) -> (30,42)
Info: Sink SOC.Bus.slave_1_write_LUT4_Z_B_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/core/core.v:97.14-113.2
Info: Risco-5/src/core/control_unit.v:25.11-25.16
Info: Risco-5/src/peripheral/soc.v:25.3-33.2
Info: 0.2 1.7 Source SOC.Bus.slave_1_write_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: 1.5 3.2 Net SOC.Bus.slave_1_write_LUT4_Z_B_LUT4_Z_C[3] (30,42) -> (31,38)
Info: Sink SOC.Bus.slave_1_write_LUT4_Z_B_LUT4_Z_C_LUT4_D.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.4 Source SOC.Bus.slave_1_write_LUT4_Z_B_LUT4_Z_C_LUT4_D.F
Info: 1.4 4.8 Net SOC.Bus.slave_1_write_LUT4_Z_B_LUT4_Z_C_LUT4_D_Z[2] (31,38) -> (37,25)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.1 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.F
Info: 2.1 7.2 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (37,25) -> (33,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.B
Info: 0.4 7.6 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.6 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (33,36) -> (33,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.6 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.6 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (33,36) -> (33,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.7 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.7 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (33,36) -> (33,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.7 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.7 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (33,36) -> (33,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.8 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.8 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (33,36) -> (33,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.8 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.8 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (33,36) -> (33,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.8 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.8 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (33,36) -> (33,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.8 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.8 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (33,36) -> (34,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.9 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.9 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (34,36) -> (34,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.9 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.9 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (34,36) -> (34,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.0 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 8.0 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (34,36) -> (34,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 8.0 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 8.0 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0_CIN (34,36) -> (34,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.1 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 8.1 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (34,36) -> (34,36)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 8.1 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 8.1 Net $nextpnr_CCU2C_5$CIN (34,36) -> (34,36)
Info: Sink $nextpnr_CCU2C_5$CCU2_COMB0.FCI
Info: 0.4 8.5 Source $nextpnr_CCU2C_5$CCU2_COMB0.F
Info: 2.1 10.6 Net SOC.Memory.address_LUT4_Z_1_C[1] (34,36) -> (11,35)
Info: Sink SOC.Memory.address_LUT4_Z_2.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.2 10.8 Source SOC.Memory.address_LUT4_Z_2.F
Info: 2.4 13.2 Net SOC.slave_address[3] (11,35) -> (11,17)
Info: Sink SOC.Memory.memory.0.470$DPRAM_COMB0.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/soc.v:19.5-19.18
Info: 0.2 13.4 Source SOC.Memory.memory.0.470$DPRAM_COMB0.F
Info: 0.9 14.3 Net SOC.Memory.memory.0.470_DO_1[3] (11,17) -> (12,16)
Info: Sink SOC.Memory.memory.0.502_DO_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 14.6 Source SOC.Memory.memory.0.502_DO_LUT4_Z.F
Info: 0.4 15.0 Net SOC.Memory.memory.0.502_DO[3] (12,16) -> (12,16)
Info: Sink SOC.Memory.memory.0.462_DO_3_PFUMX_Z_ALUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 15.2 Source SOC.Memory.memory.0.462_DO_3_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 15.2 Net SOC.Memory.memory.0.462_DO_3_PFUMX_Z_ALUT (12,16) -> (12,16)
Info: Sink SOC.Memory.memory.0.462_DO_3_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info: 0.2 15.4 Source SOC.Memory.memory.0.462_DO_3_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.4 15.8 Net SOC.Memory.memory.0.462_DO_3[3] (12,16) -> (12,16)
Info: Sink SOC.Memory.memory.0.462_DO_3_LUT4_B.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 16.0 Source SOC.Memory.memory.0.462_DO_3_LUT4_B.F
Info: 1.2 17.2 Net SOC.Memory.memory.0.422_DO_LUT4_B_Z[1] (12,16) -> (6,16)
Info: Sink SOC.Core.read_data_PFUMX_Z_7_C0_LUT4_Z_1_B_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 17.4 Source SOC.Core.read_data_PFUMX_Z_7_C0_LUT4_Z_1_B_LUT4_Z.F
Info: 1.2 18.7 Net SOC.Core.read_data_PFUMX_Z_7_C0_LUT4_Z_1_B[3] (6,16) -> (6,20)
Info: Sink SOC.Core.read_data_PFUMX_Z_7_C0_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 18.9 Source SOC.Core.read_data_PFUMX_Z_7_C0_LUT4_Z_1.F
Info: 1.3 20.2 Net SOC.Core.read_data_PFUMX_Z_7_C0[4] (6,20) -> (13,23)
Info: Sink SOC.Core.read_data_PFUMX_Z_7_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 20.5 Source SOC.Core.read_data_PFUMX_Z_7_BLUT_LUT4_Z.OFX
Info: 2.5 22.9 Net SOC.read_data[24] (13,23) -> (28,39)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_7.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/soc.v:18.34-18.43
Info: 0.0 22.9 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_7.M
Info: 4.6 ns logic, 18.3 ns routing
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source ClkDivider.clk_counter_TRELLIS_FF_Q_23.Q
Info: 1.1 1.7 Net ClkDivider.clk_counter[8] (43,16) -> (43,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:14.26-14.37
Info: 0.4 2.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (43,15) -> (43,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (43,15) -> (43,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.2 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.2 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (43,15) -> (43,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.2 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.2 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (43,15) -> (44,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (44,15) -> (44,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (44,15) -> (44,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (44,15) -> (44,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (44,15) -> (44,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.4 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.4 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (44,15) -> (44,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.4 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.4 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (44,15) -> (44,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (44,15) -> (44,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (44,15) -> (45,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (45,15) -> (45,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (45,15) -> (45,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (45,15) -> (45,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (45,15) -> (45,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.7 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.7 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (45,15) -> (45,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.7 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.7 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (45,15) -> (45,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (45,15) -> (45,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (45,15) -> (46,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (46,15) -> (46,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN (46,15) -> (46,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.9 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.9 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (46,15) -> (46,15)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.9 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.9 Net $nextpnr_CCU2C_7$CIN (46,15) -> (46,15)
Info: Sink $nextpnr_CCU2C_7$CCU2_COMB0.FCI
Info: 0.4 3.3 Source $nextpnr_CCU2C_7$CCU2_COMB0.F
Info: 0.7 4.1 Net reset_LUT4_B_C_LUT4_Z_D (46,15) -> (44,17)
Info: Sink reset_LUT4_B_C_LUT4_Z.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.2 4.3 Source reset_LUT4_B_C_LUT4_Z.F
Info: 0.0 4.4 Net reset_LUT4_B_C[1] (44,17) -> (44,17)
Info: Sink reset_LUT4_B.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.6 Source reset_LUT4_B.F
Info: 0.7 5.2 Net reset_LUT4_B_Z (44,17) -> (43,16)
Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_25.LSR
Info: 0.4 5.7 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_25.LSR
Info: 3.1 ns logic, 2.6 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source reset$tr_io.O
Info: 3.1 3.1 Net reset$TRELLIS_IO_IN (0,29) -> (44,17)
Info: Sink reset_LUT4_B.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.3 Source reset_LUT4_B.F
Info: 0.7 3.9 Net reset_LUT4_B_Z (44,17) -> (43,16)
Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_25.LSR
Info: 0.4 4.4 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_25.LSR
Info: 0.7 ns logic, 3.7 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source ClkDivider.clk_o_auto_TRELLIS_FF_Q.Q
Info: 1.0 1.6 Net clk_o (42,15) -> (48,15)
Info: Sink led_LUT4_Z_2.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:9.6-9.11
Info: 0.2 1.8 Source led_LUT4_Z_2.F
Info: 3.4 5.3 Net led[7]$TRELLIS_IO_OUT (48,15) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 4.5 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk_o' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info: 3.0 3.5 Net SOC.Core.read_data_PFUMX_Z_C0[0] (25,43) -> (62,44)
Info: Sink led_LUT4_Z_7.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: Risco-5/src/peripheral/soc.v:74.6-83.2
Info: 0.2 3.7 Source led_LUT4_Z_7.F
Info: 2.3 6.0 Net led[2]$TRELLIS_IO_OUT (62,44) -> (90,44)
Info: Sink led[2]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.3 ns routing
Info: Max frequency for clock '$glbnet$clk_o': 43.60 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 176.30 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.37 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.26 ns
Info: Max delay posedge $glbnet$clk_o -> <async> : 6.02 ns
Info: Slack histogram:
Info: legend: * represents 116 endpoint(s)
Info: + represents [1,116) endpoint(s)
Info: [ 34328, 36723) |+
Info: [ 36723, 39118) |+
Info: [ 39118, 41513) |
Info: [ 41513, 43908) |
Info: [ 43908, 46303) |
Info: [ 46303, 48698) |
Info: [ 48698, 51093) |
Info: [ 51093, 53488) |
Info: [ 53488, 55883) |
Info: [ 55883, 58278) |
Info: [ 58278, 60673) |+
Info: [ 60673, 63068) |+
Info: [ 63068, 65463) |+
Info: [ 65463, 67858) |************+
Info: [ 67858, 70253) |**********************************+
Info: [ 70253, 72648) |************************************************************
Info: [ 72648, 75043) |******+
Info: [ 75043, 77438) |***+
Info: [ 77438, 79833) |********+
Info: [ 79833, 82228) |+
Info: Program finished normally.
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