Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco 5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v
[Pipeline] sh
+ /eda/oss-cad-suite/bin/vvp build/soc_test.o
ERROR: Risco-5/src/peripheral/memory.v:29: $readmemh: Unable to open software/memory/generic.hex for reading.
VCD info: dumpfile build/soc.vcd opened for output.
Risco-5/tests/soc_test.v:34: $finish called at 1206 (1s)
[Pipeline] sh
+ rm -f Risco-5/software/memory/generic.hex
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Síntese)
[Pipeline] parallel
[Pipeline] { (Branch: OSS-Cad-Suite)
[Pipeline] { (Branch: Gowin)
[Pipeline] stage
[Pipeline] { (OSS-Cad-Suite)
[Pipeline] stage
[Pipeline] { (Gowin)
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
+ rm -rf Risco-5/impl/pnr
[Pipeline] sh
[Pipeline] sh
+ /eda/oss-cad-suite/bin/yosys -p                                          read_verilog Risco-5/fpga/ecp5/main.v;                                         read_verilog Risco-5/debug/clk_divider.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)

-- Running command `                                         read_verilog Risco-5/fpga/ecp5/main.v;                                         read_verilog Risco-5/debug/clk_divider.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/debug/clk_divider.v
Parsing Verilog input from `Risco-5/debug/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/debug/reset.v
Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\Alu'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:106: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v
Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation.
Generating RTLIL representation for module `\CSR_Unit'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v
Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

22. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

23. Executing SYNTH_ECP5 pass.

23.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

23.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

23.3. Executing HIERARCHY pass (managing design hierarchy).

23.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: FIFO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   0 design levels: CSR_Unit            
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: Alu                 
root of   0 design levels: ResetBootSystem     
root of   0 design levels: ClkDivider          
root of   3 design levels: top                 
Automatically selected top as design top module.

23.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 2048
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6

23.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 2048
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6
Generating RTLIL representation for module `$paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC'.
Parameter \CYCLES = 20

23.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \WIDHT = 5

23.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 5
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600

23.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

23.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

23.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:106: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

23.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

23.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

23.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

23.3.12. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \WIDHT = 6

23.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 6
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200

23.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Generating RTLIL representation for module `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 2048

23.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 2048
Generating RTLIL representation for module `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

23.3.16. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

23.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

23.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

23.3.19. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100

23.3.20. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\GPIOS'.
Removing unused module `\FIFO'.
Removing unused module `\Core'.
Removing unused module `\ResetBootSystem'.
Removing unused module `\ClkDivider'.
Removed 15 unused modules.

23.4. Executing PROC pass (convert processes to netlists).

23.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$516'.
Found and cleaned up 1 empty switch in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:0$904'.
Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:0$904'.
Cleaned up 2 empty switches.

23.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$623 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$575 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$517 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:24$815 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$997 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$995 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$987 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$984 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$978 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$973 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$968 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$959 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$946 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$944 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$936 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$922 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$916 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$911 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:179$705 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:45$902 in module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:33$865 in module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$236 in module LEDs.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:76$855 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:41$841 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$839 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:22$94 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$84 in module PC.
Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:10$83 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:10$83 in module MUX.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$81 in module Immediate_Generator.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:181$79 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:172$75 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:158$73 in module CSR_Unit.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:113$66 in module CSR_Unit.
Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$626 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Removed 1 dead cases from process $proc$Risco-5/src/core/control_unit.v:122$54 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:122$54 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/control_unit.v:80$52 in module Control_Unit.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:80$52 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:72$51 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$47 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$47 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:23$32 in module Alu.
Removed a total of 4 dead cases.

23.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 11 redundant assignments.
Promoted 146 assignments to connections.

23.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$624'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$999'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$952'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$708'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
  Set init value: \pc_old = 0
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$239'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$858'.
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \buffer_full = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$87'.
  Set init value: \Output = 0
Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$80'.
  Set init value: \csr_mcause = 0
  Set init value: \csr_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mepc = 0
  Set init value: \csr_mie_mfie = 16'0000000000000000
  Set init value: \csr_mie_meie = 1'0
  Set init value: \csr_mie_msie = 1'0
  Set init value: \csr_mie_mtie = 1'0
  Set init value: \csr_mip_mfip = 16'0000000000000000
  Set init value: \csr_mip_meip = 1'0
  Set init value: \csr_mip_mtip = 1'0
  Set init value: \csr_mip_msip = 1'0
  Set init value: \csr_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mscratch = 0
  Set init value: \csr_mstatus_mie = 1'0
  Set init value: \csr_mstatus_mpie = 1'0
  Set init value: \csr_mtvec = 0
  Set init value: \csr_mtval = 0
  Set init value: \csr_write_data = 0
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$632'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$55'.
  Set init value: \state = 4'0000
  Set init value: \is_immediate = 1'0
  Set init value: \lorD = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \reg_write = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \csr_write_enable = 1'0
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 2'00
  Set init value: \alu_src_b = 2'00
  Set init value: \memory_to_reg = 2'00
  Set init value: \nextstate = 4'0000

23.4.5. Executing PROC_ARST pass (detect async resets in processes).

23.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 1 switch.
<suppressed ~88 debug messages>

23.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$624'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$623'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$575'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$574_EN[3:0]$581
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$574_DATA[3:0]$580
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$574_ADDR[3:0]$579
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$517'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$515_EN[3:0]$523
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$515_DATA[3:0]$522
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$515_ADDR[3:0]$521
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$516'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'.
     1/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$827
     2/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_DATA[7:0]$826
     3/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR[5:0]$825
     4/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$822
     5/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_DATA[7:0]$821
     6/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR[5:0]$820
     7/8: $0\write_ptr[5:0]
     8/8: $0\read_ptr[5:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$999'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$997'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$995'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$987'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$984'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$978'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$973'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$968'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$959'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$952'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$946'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$944'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$936'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$922'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$916'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$911'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$708'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'.
     1/6: $0\alu_out_register[31:0]
     2/6: $0\register_data_2[31:0]
     3/6: $0\register_data_1[31:0]
     4/6: $0\memory_register[31:0]
     5/6: $0\pc_old[31:0]
     6/6: $0\instruction_register[31:0]
Creating decoders for process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$902'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$865'.
     1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$898
     2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_DATA[31:0]$897
     3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_ADDR[31:0]$896
     4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$901
     5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_DATA[31:0]$900
     6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_ADDR[31:0]$899
     7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$888
     8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_DATA[31:0]$887
     9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_ADDR[31:0]$886
    10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$894
    11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_DATA[31:0]$893
    12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_ADDR[31:0]$892
    13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$891
    14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_DATA[31:0]$890
    15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_ADDR[31:0]$889
    16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$884
    17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_DATA[31:0]$883
    18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_ADDR[31:0]$882
    19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$881
    20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_DATA[31:0]$880
    21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_ADDR[31:0]$879
    22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$878
    23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_DATA[31:0]$877
    24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_ADDR[31:0]$876
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$239'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$236'.
     1/1: $0\data[32:0]
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$858'.
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$855'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$841'.
     1/9: $0\rx_fifo_write[0:0]
     2/9: $0\rx_fifo_read[0:0]
     3/9: $0\tx_fifo_write[0:0]
     4/9: $0\tx_fifo_read[0:0]
     5/9: $0\uart_tx_en[0:0]
     6/9: $0\rx_fifo_write_data[7:0]
     7/9: $0\tx_fifo_write_data[7:0]
     8/9: $0\uart_tx_data[7:0]
     9/9: $0\buffer_full[0:0]
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$839'.
     1/2: $0\gpio_value[5:0]
     2/2: $0\gpio_direction[5:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$112'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:22$94'.
     1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$109
     2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$90_DATA[31:0]$108
     3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$90_ADDR[4:0]$107
     4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$110
     5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$101
     6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$105
     7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$104
     8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$90_DATA[31:0]$103
     9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$90_ADDR[4:0]$102
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$87'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$84'.
     1/1: $0\Output[31:0]
Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:10$83'.
     1/1: $1\S[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$81'.
     1/4: $4\immediate[31:0]
     2/4: $3\immediate[31:0]
     3/4: $2\immediate[31:0]
     4/4: $1\immediate[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$80'.
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$79'.
     1/1: $1\csr_data_out[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75'.
     1/1: $1\csr_write_data[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'.
     1/4: $0\csr_mip_msip[0:0]
     2/4: $0\csr_mip_mtip[0:0]
     3/4: $0\csr_mip_meip[0:0]
     4/4: $0\csr_mip_mfip[15:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
     1/13: $0\csr_mtval[31:0]
     2/13: $0\csr_mtvec[31:0]
     3/13: $0\csr_mstatus_mpie[0:0]
     4/13: $0\csr_mstatus_mie[0:0]
     5/13: $0\csr_mscratch[31:0]
     6/13: $0\csr_minstret[63:0]
     7/13: $0\csr_mie_mtie[0:0]
     8/13: $0\csr_mie_msie[0:0]
     9/13: $0\csr_mie_meie[0:0]
    10/13: $0\csr_mie_mfie[15:0]
    11/13: $0\csr_mepc[31:0]
    12/13: $0\csr_mcycle[63:0]
    13/13: $0\csr_mcause[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$632'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$626'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$55'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
     1/1: { $1\pc_write[0:0] $1\alu_src_b[1:0] $1\ir_write[0:0] $1\memory_read[0:0] $1\memory_to_reg[1:0] $1\alu_src_a[1:0] $1\aluop[1:0] $1\csr_write_enable[0:0] $1\pc_write_cond[0:0] $1\memory_write[0:0] $1\reg_write[0:0] $1\pc_source[0:0] $1\lorD[0:0] $1\is_immediate[0:0] }
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52'.
     1/3: $3\nextstate[3:0]
     2/3: $2\nextstate[3:0]
     3/3: $1\nextstate[3:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$51'.
     1/1: $0\state[3:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$47'.
     1/4: $4\aluop_out[3:0]
     2/4: $3\aluop_out[3:0]
     3/4: $2\aluop_out[3:0]
     4/4: $1\aluop_out[3:0]
Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:23$32'.
     1/1: $1\ALU_out_S[31:0]

23.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$968'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$911'.
No latch inferred for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.\read_data' from process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$902'.
No latch inferred for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\read_data' from process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$855'.
No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:16$88_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$112'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:10$83'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$81'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_code' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$80'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_interrupt_flag' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$80'.
No latch inferred for signal `\CSR_Unit.\csr_utime' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$80'.
No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$79'.
No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75'.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [0]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [1]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [2]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [3]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [4]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [5]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [6]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [7]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [8]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [9]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [10]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [11]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [12]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [13]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [14]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [15]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [16]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [17]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [18]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [19]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [20]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [21]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [22]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [23]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [24]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [25]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [26]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [27]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [28]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [29]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [30]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [31]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52`.
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$47': $auto$proc_dlatch.cc:433:proc_dlatch$2050
No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:23$32'.

23.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$623'.
  created $dff cell `$procdff$2073' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$559_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$560_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$561_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$562_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$563_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$564_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$565_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$566_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$567_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$568_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$569_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$570_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$571_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$572_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$573_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$574_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$575'.
  created $dff cell `$procdff$2074' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$574_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$575'.
  created $dff cell `$procdff$2075' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$574_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$575'.
  created $dff cell `$procdff$2076' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$499_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$500_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$501_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$502_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$503_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$504_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$505_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$506_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$507_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$508_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$509_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$510_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$511_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$512_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$513_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$514_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$515_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$517'.
  created $dff cell `$procdff$2077' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$515_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$517'.
  created $dff cell `$procdff$2078' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$515_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$517'.
  created $dff cell `$procdff$2079' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$516'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'.
  created $dff cell `$procdff$2080' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'.
  created $dff cell `$procdff$2081' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'.
  created $dff cell `$procdff$2082' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'.
  created $dff cell `$procdff$2083' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'.
  created $dff cell `$procdff$2084' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$997'.
  created $dff cell `$procdff$2085' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$997'.
  created $dff cell `$procdff$2086' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$995'.
  created $dff cell `$procdff$2087' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$987'.
  created $dff cell `$procdff$2088' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$984'.
  created $dff cell `$procdff$2089' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$978'.
  created $dff cell `$procdff$2090' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$973'.
  created $dff cell `$procdff$2091' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$973'.
  created $dff cell `$procdff$2092' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$959'.
  created $dff cell `$procdff$2093' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$946'.
  created $dff cell `$procdff$2094' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$944'.
  created $dff cell `$procdff$2095' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$936'.
  created $dff cell `$procdff$2096' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$922'.
  created $dff cell `$procdff$2097' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$916'.
  created $dff cell `$procdff$2098' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$916'.
  created $dff cell `$procdff$2099' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'.
  created $dff cell `$procdff$2100' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'.
  created $dff cell `$procdff$2101' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'.
  created $dff cell `$procdff$2102' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'.
  created $dff cell `$procdff$2103' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'.
  created $dff cell `$procdff$2104' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'.
  created $dff cell `$procdff$2105' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$865'.
  created $dff cell `$procdff$2106' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$865'.
  created $dff cell `$procdff$2107' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$865'.
  created $dff cell `$procdff$2108' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$865'.
  created $dff cell `$procdff$2109' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$865'.
  created $dff cell `$procdff$2110' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$865'.
  created $dff cell `$procdff$2111' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$865'.
  created $dff cell `$procdff$2112' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$865'.
  created $dff cell `$procdff$2113' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$865'.
  created $dff cell `$procdff$2114' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$236'.
  created $dff cell `$procdff$2115' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_en' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$841'.
  created $dff cell `$procdff$2116' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$841'.
  created $dff cell `$procdff$2117' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$841'.
  created $dff cell `$procdff$2118' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$841'.
  created $dff cell `$procdff$2119' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$841'.
  created $dff cell `$procdff$2120' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\buffer_full' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$841'.
  created $dff cell `$procdff$2121' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$841'.
  created $dff cell `$procdff$2122' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$841'.
  created $dff cell `$procdff$2123' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$841'.
  created $dff cell `$procdff$2124' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$839'.
  created $dff cell `$procdff$2125' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$839'.
  created $dff cell `$procdff$2126' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$94'.
  created $dff cell `$procdff$2127' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$90_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$94'.
  created $dff cell `$procdff$2128' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$90_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$94'.
  created $dff cell `$procdff$2129' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$94'.
  created $dff cell `$procdff$2130' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$94'.
  created $dff cell `$procdff$2131' with positive edge clock.
Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$84'.
  created $dff cell `$procdff$2132' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mfip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'.
  created $dff cell `$procdff$2133' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_meip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'.
  created $dff cell `$procdff$2134' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mtip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'.
  created $dff cell `$procdff$2135' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_msip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'.
  created $dff cell `$procdff$2136' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2137' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcycle' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2138' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2139' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mfie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2140' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_meie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2141' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_msie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2142' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mtie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2143' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_minstret' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2144' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2145' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2146' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mpie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2147' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2148' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
  created $dff cell `$procdff$2149' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$626'.
  created $dff cell `$procdff$2150' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$626'.
  created $dff cell `$procdff$2151' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$626'.
  created $dff cell `$procdff$2152' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$51'.
  created $dff cell `$procdff$2153' with positive edge clock.

23.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$624'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$623'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$623'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$575'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$517'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$516'.
Found and cleaned up 3 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$999'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$997'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$997'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$995'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$995'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$987'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$987'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$984'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$984'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$978'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$978'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$973'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$973'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$968'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$968'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$959'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$959'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$952'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$946'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$946'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$944'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$944'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$936'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$936'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$922'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$922'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$916'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$916'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$911'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$911'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$708'.
Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'.
Found and cleaned up 1 empty switch in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$902'.
Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$902'.
Found and cleaned up 3 empty switches in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$865'.
Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$865'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$239'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$236'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$236'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$858'.
Found and cleaned up 1 empty switch in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$855'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$855'.
Found and cleaned up 5 empty switches in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$841'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$841'.
Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$839'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$839'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$112'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:22$94'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:22$94'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$87'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$84'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$84'.
Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:10$83'.
Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:10$83'.
Found and cleaned up 4 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$81'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$81'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$80'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$79'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$79'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'.
Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$632'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$626'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$626'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$55'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'.
Found and cleaned up 3 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$51'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$51'.
Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$47'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$47'.
Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:23$32'.
Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:23$32'.
Cleaned up 89 empty switches.

23.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~4 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~4 debug messages>
Optimizing module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.
<suppressed ~5 debug messages>
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
<suppressed ~9 debug messages>
Optimizing module GPIO.
<suppressed ~3 debug messages>
Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
<suppressed ~4 debug messages>
Optimizing module BUS.
Optimizing module Registers.
<suppressed ~2 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
<suppressed ~1 debug messages>
Optimizing module CSR_Unit.
<suppressed ~2 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module Control_Unit.
<suppressed ~1 debug messages>
Optimizing module ALU_Control.
<suppressed ~15 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC.
Optimizing module top.

23.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.
Deleting now unused module LEDs.
Deleting now unused module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Deleting now unused module GPIO.
Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module Alu.
Deleting now unused module $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC.
<suppressed ~30 debug messages>

23.6. Executing TRIBUF pass.

23.7. Executing DEMINOUT pass (demote inout ports to input or output).

23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~47 debug messages>

23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
+ mkdir -p Risco-5/impl/pnr
Finding unused cells or wires in module \top..
Removed 64 unused cells and 728 unused wires.
<suppressed ~82 debug messages>

23.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\SOC.Core.PCSourceMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [15] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [14] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [13] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [12] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [11] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [10] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [9] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [8] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [7] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [6] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [5] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [4] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [3] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [2] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [1] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [0] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_external is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_timer is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_software is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [0] is used but has no driver.
Found and reported 211 problems.

23.11. Executing OPT pass (performing simple optimizations).

23.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

23.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~351 debug messages>
Removed a total of 117 cells.

23.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1944.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1972.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1620.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1622.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1633.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1648.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1607.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1607.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1607.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1607.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1567.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1573.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1579.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1585.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1364.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1366.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1373.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1375.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1382.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1384.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1391.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1393.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1400.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1402.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1409.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1411.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1417.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1423.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1429.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1435.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1441.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1447.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1453.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1459.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1465.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1031.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1037.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1043.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1031.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1037.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1043.
Removed 41 multiplexer ports.
<suppressed ~120 debug messages>

23.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1662: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1683_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1682_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1675_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1674_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1673_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1672_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1671_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1670_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1669_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1668_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1667_CMP $auto$opt_reduce.cc:134:opt_pmux$2210 $auto$opt_reduce.cc:134:opt_pmux$2208 $auto$opt_reduce.cc:134:opt_pmux$2206 $auto$opt_reduce.cc:134:opt_pmux$2204 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1961: { $auto$opt_reduce.cc:134:opt_pmux$2212 $flatten\SOC.\Core.\Control_Unit.$procmux$1969_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1968_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1967_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1966_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1965_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1964_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1963_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1962_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1974: { $flatten\SOC.\Core.\Control_Unit.$procmux$1990_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1973_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1945_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1987_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1979_CMP $auto$opt_reduce.cc:134:opt_pmux$2216 $auto$opt_reduce.cc:134:opt_pmux$2214 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2010: { $flatten\SOC.\Core.\ALU_Control.$procmux$2017_CMP $auto$opt_reduce.cc:134:opt_pmux$2218 $flatten\SOC.\Core.\ALU_Control.$procmux$2014_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2013_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2012_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2011_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1645: $auto$opt_reduce.cc:134:opt_pmux$2220
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1651: { $flatten\SOC.\Core.\Control_Unit.$procmux$1966_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1967_CMP $auto$opt_reduce.cc:134:opt_pmux$2224 $flatten\SOC.\Core.\Control_Unit.$procmux$1968_CMP $auto$opt_reduce.cc:134:opt_pmux$2222 $flatten\SOC.\Core.\Control_Unit.$procmux$1962_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1970_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1564:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1582:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1588:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1361:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1361_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1361_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1361_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] $flatten\SOC.\Memory.$procmux$1361_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2024: { $auto$opt_reduce.cc:134:opt_pmux$2228 $auto$opt_reduce.cc:134:opt_pmux$2226 $flatten\SOC.\Core.\ALU_Control.$procmux$2017_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1388:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1388_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1388_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1388_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] $flatten\SOC.\Memory.$procmux$1388_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2033: { $flatten\SOC.\Core.\ALU_Control.$procmux$2035_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2034_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1415:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1415_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1415_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1415_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] $flatten\SOC.\Memory.$procmux$1415_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1028:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1028_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1028_Y [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$1028_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$1028_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1028_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1028_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1028_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1028_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1028_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1028_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1028:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1028_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1028_Y [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$1028_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$1028_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1028_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1028_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1028_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1028_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1028_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1028_Y [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1591:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$110, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1582_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1594:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$109, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1564_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1433:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$901, B=0, Y=$flatten\SOC.\Memory.$procmux$1433_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1388_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1433_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1433_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] $flatten\SOC.\Memory.$procmux$1433_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1451:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$898, B=0, Y=$flatten\SOC.\Memory.$procmux$1451_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1361_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1451_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1451_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] $flatten\SOC.\Memory.$procmux$1451_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1486:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$888, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1415_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_EN[31:0]$868 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1046:
      Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$827, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818
      New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1028_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1046:
      Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$827, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818
      New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1028_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1468:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$894, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1433_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_EN[31:0]$874 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1477:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$891, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1451_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_EN[31:0]$871 [0] }
  Optimizing cells in module \top.
Performed a total of 25 changes.

23.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

23.11.6. Executing OPT_DFF pass (perform DFF optimizations).

23.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 169 unused wires.
<suppressed ~8 debug messages>

23.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.11.9. Rerunning OPT passes. (Maybe there is more to do..)

23.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~119 debug messages>

23.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.11.13. Executing OPT_DFF pass (perform DFF optimizations).

23.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.11.16. Finished OPT passes. (There is nothing left to do.)

23.12. Executing FSM pass (extract and optimize FSM).

23.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.CSR_Unit.csr_mip_mfip as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state.
Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.

23.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$2087
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$961_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$976_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$989_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$975_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$989_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$980_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$976_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$975_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$961_Y
  ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$961_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$975_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$976_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$980_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$989_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'0--0 ->      3'001 8'01010001
  transition:      3'000 4'1--0 ->      3'000 8'01010000
  transition:      3'000 4'---1 ->      3'000 8'01010000
  transition:      3'010 4'--00 ->      3'010 8'00100010
  transition:      3'010 4'--10 ->      3'011 8'00100011
  transition:      3'010 4'---1 ->      3'000 8'00100000
  transition:      3'001 4'-0-0 ->      3'001 8'00011001
  transition:      3'001 4'-1-0 ->      3'010 8'00011010
  transition:      3'001 4'---1 ->      3'000 8'00011000
  transition:      3'011 4'-0-0 ->      3'011 8'10010011
  transition:      3'011 4'-1-0 ->      3'000 8'10010000
  transition:      3'011 4'---1 ->      3'000 8'10010000

23.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2229' from module `\top'.

23.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 7 unused cells and 7 unused wires.
<suppressed ~8 debug messages>

23.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2229' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].

23.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2229' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

23.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2229' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$2229 (\SOC.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_rx.payload_done
    2: \SOC.Uart.i_uart_rx.next_bit
    3: \SOC.Uart.i_uart_rx.rxd_reg

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$989_Y
    1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$980_Y
    2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$976_Y
    3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$975_Y
    4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$961_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'1--0   ->     0 5'01010
      1:     0 4'---1   ->     0 5'01010
      2:     0 4'0--0   ->     2 5'01010
      3:     1 4'---1   ->     0 5'00100
      4:     1 4'--00   ->     1 5'00100
      5:     1 4'--10   ->     3 5'00100
      6:     2 4'---1   ->     0 5'00011
      7:     2 4'-1-0   ->     1 5'00011
      8:     2 4'-0-0   ->     2 5'00011
      9:     3 4'-1-0   ->     0 5'10010
     10:     3 4'---1   ->     0 5'10010
     11:     3 4'-0-0   ->     3 5'10010

-------------------------------------

23.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2229' from module `\top'.

23.13. Executing OPT pass (performing simple optimizations).

23.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

23.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

23.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~118 debug messages>

23.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2099 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1312_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1306_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1297_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1288_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1279_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1270_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1252_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1261_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2279 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$2279 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1306_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1297_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1288_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1279_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1270_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1252_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1261_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2097 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1228_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2284 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1228_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2096 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1217_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$2290 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$943_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2095 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2094 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1206_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2295 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1206_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2093 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1195_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2301 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2092 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1172_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1163_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1154_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1145_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1136_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1127_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1109_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1118_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2303 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2090 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1091_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2307 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$983_Y, Q = \SOC.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2089 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1086_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2311 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2088 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1078_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$2313 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$994_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2086 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2085 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2081 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1055_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2319 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$830_Y, Q = \SOC.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2080 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1060_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2321 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$835_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2081 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1055_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2323 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$830_Y, Q = \SOC.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2080 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1060_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2325 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$835_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2124 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1529_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2327 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2123 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1534_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2329 ($sdff) from module top (D = \SOC.Uart.write_data [7:0], Q = \SOC.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2122 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1539_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2331 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2120 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1504_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2119 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1509_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2118 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1514_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2116 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1519_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$2115 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1494_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2337 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2126 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1550_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2339 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2125 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1558_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2343 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2132 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1602_Y, Q = \SOC.Core.Pc.Output, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2349 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2153 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 4'0000).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2149 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1706_Y, Q = \SOC.Core.CSR_Unit.csr_mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2352 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mtval).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2148 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 1'0 \SOC.Core.CSR_Unit.csr_write_data [0] }, Q = \SOC.Core.CSR_Unit.csr_mtvec).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2147 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1732_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2361 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2146 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1749_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2365 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mstatus_mie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2145 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1765_Y, Q = \SOC.Core.CSR_Unit.csr_mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2369 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mscratch).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2144 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1778_Y, Q = \SOC.Core.CSR_Unit.csr_minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2373 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1778_Y, Q = \SOC.Core.CSR_Unit.csr_minstret).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2143 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1796_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mtie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2377 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mie_mtie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2142 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1814_Y, Q = \SOC.Core.CSR_Unit.csr_mie_msie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2381 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mie_msie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2141 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1832_Y, Q = \SOC.Core.CSR_Unit.csr_mie_meie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2385 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [11], Q = \SOC.Core.CSR_Unit.csr_mie_meie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2140 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1850_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mfie, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2389 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [31:16], Q = \SOC.Core.CSR_Unit.csr_mie_mfie).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2139 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.csr_mepc).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2138 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1873_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2398 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1873_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2137 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1884_Y, Q = \SOC.Core.CSR_Unit.csr_mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2402 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mcause).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2136 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_software, Q = \SOC.Core.CSR_Unit.csr_mip_msip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2135 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_timer, Q = \SOC.Core.CSR_Unit.csr_mip_mtip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2134 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_external, Q = \SOC.Core.CSR_Unit.csr_mip_meip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2133 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_fast, Q = \SOC.Core.CSR_Unit.csr_mip_mfip, rval = 16'0000000000000000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2105 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1344_Y, Q = \SOC.Core.pc_old, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2410 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2104 ($dff) from module top (D = \SOC.Bus.write_data, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2103 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2102 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2101 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2100 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1349_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2416 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2152 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2151 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2150 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2393 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2393 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2356 ($dffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$2338 ($sdffe) from module top.

23.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 130 unused cells and 126 unused wires.
<suppressed ~131 debug messages>

23.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

23.13.9. Rerunning OPT passes. (Maybe there is more to do..)

23.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

23.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2309: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o }
  Optimizing cells in module \top.
Performed a total of 1 changes.

23.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

23.13.13. Executing OPT_DFF pass (perform DFF optimizations).

23.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 6 unused wires.
<suppressed ~2 debug messages>

23.13.15. Executing OPT_EXPR pass (perform const folding).
[Pipeline] }
Optimizing module top.

23.13.16. Rerunning OPT passes. (Maybe there is more to do..)

23.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

23.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.13.20. Executing OPT_DFF pass (perform DFF optimizations).

23.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.13.23. Finished OPT passes. (There is nothing left to do.)

23.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 28 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\Control_Unit.$auto$mem.cc:328:emit$1003 ($flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2158 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2160 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:16$111 (SOC.Core.RegisterBank.registers).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2155 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2156 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2157 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$903 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$863 (SOC.Memory.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2154 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$814 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2154 (SOC.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$814 (SOC.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1901_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$630 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$629 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$629 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$628 ($lt).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2424 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2429 ($ne).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$838 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1501_CMP0 ($eq).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$procmux$1500 ($pmux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1052 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1040 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$835 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$828 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$810 ($eq).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1052 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1040 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$835 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$828 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$810 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$972 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$971 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$970 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$969 ($mux).
Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:111$964 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:109$962 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$938 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$930 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$928 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$925 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$924 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$920 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$915 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$914 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$913 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$912 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$908 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$906 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$235 ($mux).
Removed top 20 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$115 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$118 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$119 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$122 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$123 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$126 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$127 ($le).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:75$157 ($mux).
Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:84$173 ($mux).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$187 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Memory.$procmux$1357_CMP0 ($eq).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1474 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1483 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1492 ($mux).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:100$53 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1610_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1610_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1610_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1987_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1986_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1985_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1984_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1983_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1973_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1970_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1969_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1968_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1965_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1964_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1945_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1942 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2035_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2017_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2016_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2015_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2003 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2048_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2047_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2046_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2045_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$46 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$38 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1688_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1675_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1674_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1673_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1672_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1671_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1670_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1669_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1668_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1667_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$72 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$70 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$69 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$114 ($ge).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1427 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1445 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1463 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1379 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1406 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$165 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$629_Y.
Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$187_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$42_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$38_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$46_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[3:0].
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_ADDR[31:0]$866.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_ADDR[31:0]$869.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_ADDR[31:0]$872.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$859_ADDR[31:0]$886.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_ADDR[31:0]$889.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_ADDR[31:0]$892.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$860_ADDR[31:0]$896.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$861_ADDR[31:0]$899.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR[5:0]$816.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR[5:0]$825.
Removed top 1 bits (of 8) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_DATA[7:0]$826.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$835_Y.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR[5:0]$816.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR[5:0]$825.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$835_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$969_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$970_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$971_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$972_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$912_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$913_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$914_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$915_Y.

23.15. Executing PEEPOPT pass (run peephole optimizers).

23.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 33 unused wires.
<suppressed ~1 debug messages>

23.17. Executing SHARE pass (SAT-based resource sharing).
Found 4 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$814 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:57$124_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:55$120_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$116_Y $flatten\SOC.\Uart.$procmux$1503_CMP $flatten\SOC.\Uart.$procmux$1502_CMP $flatten\SOC.\Uart.$procmux$1501_CMP }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$863 ($memrd):
    Found 5 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1358_CMP $flatten\SOC.\Memory.$procmux$1357_CMP \SOC.Memory.option $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$116_Y \SOC.Bus.slave_0_write \SOC.Bus.slave_0_read }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:44$44 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2040_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:42$43 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2041_CMP.
    No candidates found.

23.18. Executing TECHMAP pass (map to technology primitives).

23.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

23.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~296 debug messages>

23.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.21. Executing TECHMAP pass (map to technology primitives).

23.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

23.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

23.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

23.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$629 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$35 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$36 ($sub).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:141$67 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:142$68 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$69 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$70 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:151$71 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$72 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$807 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$829 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$807 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$829 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$983 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$994 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$932 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$943 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$943.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$932.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$994.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$983.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$829.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$807.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$829.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$807.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$72.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:151$71.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$70.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$69.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:142$68.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:141$67.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$36.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$35.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$629.
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$628 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$114 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$118 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$122 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$126 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$115 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$119 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$123 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$127 ($le): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$45 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$37 ($lt): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$45.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$630 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$628.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$42 ($eq): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$45.
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$127: $auto$alumacc.cc:485:replace_alu$2487
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$123: $auto$alumacc.cc:485:replace_alu$2500
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$119: $auto$alumacc.cc:485:replace_alu$2513
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$115: $auto$alumacc.cc:485:replace_alu$2526
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$126: $auto$alumacc.cc:485:replace_alu$2539
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$122: $auto$alumacc.cc:485:replace_alu$2548
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$118: $auto$alumacc.cc:485:replace_alu$2557
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$114: $auto$alumacc.cc:485:replace_alu$2566
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$628, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$630: $auto$alumacc.cc:485:replace_alu$2575
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$629: $auto$alumacc.cc:485:replace_alu$2586
  creating $alu cell for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$45, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$37, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$42: $auto$alumacc.cc:485:replace_alu$2589
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$35: $auto$alumacc.cc:485:replace_alu$2602
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$36: $auto$alumacc.cc:485:replace_alu$2605
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:141$67: $auto$alumacc.cc:485:replace_alu$2608
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:142$68: $auto$alumacc.cc:485:replace_alu$2611
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$69: $auto$alumacc.cc:485:replace_alu$2614
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$70: $auto$alumacc.cc:485:replace_alu$2617
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:151$71: $auto$alumacc.cc:485:replace_alu$2620
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$72: $auto$alumacc.cc:485:replace_alu$2623
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$829: $auto$alumacc.cc:485:replace_alu$2626
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$807: $auto$alumacc.cc:485:replace_alu$2629
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834: $auto$alumacc.cc:485:replace_alu$2632
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$829: $auto$alumacc.cc:485:replace_alu$2635
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$807: $auto$alumacc.cc:485:replace_alu$2638
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834: $auto$alumacc.cc:485:replace_alu$2641
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$983: $auto$alumacc.cc:485:replace_alu$2644
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$994: $auto$alumacc.cc:485:replace_alu$2647
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$932: $auto$alumacc.cc:485:replace_alu$2650
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$943: $auto$alumacc.cc:485:replace_alu$2653
  created 29 $alu and 0 $macc cells.

23.23. Executing OPT pass (performing simple optimizations).

23.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

23.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~10 debug messages>
Removed a total of 2 cells.

23.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

23.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.23.6. Executing OPT_DFF pass (perform DFF optimizations).

23.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 20 unused wires.
<suppressed ~2 debug messages>

23.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.23.9. Rerunning OPT passes. (Maybe there is more to do..)

23.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

23.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.23.13. Executing OPT_DFF pass (perform DFF optimizations).

23.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.23.16. Finished OPT passes. (There is nothing left to do.)

23.24. Executing MEMORY pass.

23.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

23.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

23.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Core.RegisterBank.registers write port 0.
  Analyzing top.SOC.Core.RegisterBank.registers write port 1.
  Analyzing top.SOC.Core.RegisterBank.registers write port 2.
  Analyzing top.SOC.Memory.memory write port 0.
  Analyzing top.SOC.Memory.memory write port 1.
  Analyzing top.SOC.Memory.memory write port 2.
  Analyzing top.SOC.Uart.RX_FIFO.memory write port 0.
  Analyzing top.SOC.Uart.TX_FIFO.memory write port 0.

23.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

23.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port address `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.
Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': merged address FF to cell.

23.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 44 unused wires.
<suppressed ~7 debug messages>

23.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
[Pipeline] // stage
[Pipeline] }
Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
  Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Memory.memory by address:
  Merging ports 0, 1 (address \SOC.Memory.address [10:2]).
  Merging ports 0, 2 (address \SOC.Memory.address [10:2]).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing:
  Checking group clocked with posedge \clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 6 cells.
  Size of unconstrained SAT problem: 40 variables, 98 clauses
  Merging port 1 into port 0.

23.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

23.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>

23.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

23.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
using FF mapping for memory top.$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001
mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 1 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[1]
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted addr FF from read port 0 of top.SOC.Uart.RX_FIFO.memory: $\SOC.Uart.RX_FIFO.memory$rdreg[0]
mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0]
<suppressed ~1100 debug messages>

23.27. Executing TECHMAP pass (map to technology primitives).

23.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

23.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

23.27.3. Continuing TECHMAP pass.
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1f7528d846def63a25ef79a14688e75507487b07\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$16483afc93766dfb5fb1eddfd226d96b3663d59c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$aaadea22aebcd84c93bb9858adaa720cf09b082d\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$4732e8e929fe8d0a57a6c959ddfc52773439ff42\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5b36af983a34dea819263d47bd985c03f062c03b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5f84a8dd211265fde0680d1329e0aeb011857798\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$65b5a9049f0a0f5b9de58368be8ce2821f51e438\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5a90b288fb430e0f24af5f61ee43ef935b86341e\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$58ddad20e9ef77e6675ec0a973f6df52cac15605\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$569f3b21b6212e6a0e436dd55c34df99d3696e0b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c21745a1d1b8202233eb4fd671436aaa3b71d7e7\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$eabd6f8a46e61d81805337b1dc746bfd80802602\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$98f4fff52781fee114365d416fa097fc5bdcc5a1\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$ef9fccd6f2ebbfd2f9ea51ad76fcd229dd950af9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$f05333f47f0fac035d1d00a83ba1f91fba94d570\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$e060b64551c3d3977f3359c6d9cbc2f183f778aa\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5e6f6332f5b0abb114a71354918e4077127fc51f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$04114c6daf9b714920df2338bb84f1d824cfb28f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$df0229c2445eb19cad504fc663c8894a4b8ad2c2\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$82cf4a0fd82546fec0e453cb163e0b57b514e109\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$05123d0bc673513b0e5ab3de2414f4ca493424ef\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$3d62e89fd9fe82123196169686b7825d33b36c84\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$413228b6beffb528da7ce6c18481e68814727c46\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$74d116fba5fc319cbe4b4ef6fabb137b2ff9e708\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~635 debug messages>

23.28. Executing OPT pass (performing simple optimizations).

23.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~142 debug messages>

23.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~21 debug messages>
Removed a total of 7 cells.

23.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $\SOC.Uart.RX_FIFO.memory$rdreg[0] ($dff) from module top (D = $auto$rtlil.cc:2582:Mux$2707, Q = $\SOC.Uart.RX_FIFO.memory$rdreg[0]$q, rval = 3'000).
Adding SRST signal on $auto$ff.cc:266:slice$2418 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1898_Y, Q = \ResetBootSystem.counter, rval = 6'000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2406 ($sdff) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$2409 ($sdff) from module top.

23.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 20 unused cells and 2124 unused wires.
<suppressed ~21 debug messages>

23.28.5. Rerunning OPT passes. (Removed registers in this run.)

23.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

23.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$3522 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$2444 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

23.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 3 unused wires.
<suppressed ~4 debug messages>

23.28.10. Rerunning OPT passes. (Removed registers in this run.)

23.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.28.13. Executing OPT_DFF pass (perform DFF optimizations).

23.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.28.15. Finished fast OPT passes.

23.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory $flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001 in module \top:
  created 16 $dff cells and 0 static cells of width 18.
  read interface: 0 $dff and 15 $mux cells.
  write interface: 0 write mux blocks.

23.30. Executing OPT pass (performing simple optimizations).

23.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$2729: $auto$rtlil.cc:2489:ReduceOr$2723 -> 1'1
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~59 debug messages>

23.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][3][6]$3567:
      Old ports: A=18'010000010000000000, B=18'010000011000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$a$3547
      New ports: A=1'0, B=1'1, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$a$3547 [9]
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$a$3547 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$a$3547 [8:0] } = 17'01000001000000000
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][3][5]$3564:
      Old ports: A=18'000000001010100100, B=18'101000010000000101, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [17:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [4:1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [0] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [5] 5'00010 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][3][4]$3561:
      Old ports: A=18'010000001100000001, B=18'101000010000000100, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544
      New ports: A=2'01, B=2'10, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [17:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [2] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [0] 6'000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][3][3]$3558:
      Old ports: A=18'000000001100000000, B=18'000000000000001000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$b$3542
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$b$3542 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$b$3542 [3] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$b$3542 [17:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$b$3542 [7:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$b$3542 [2:0] } = { 8'00000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$b$3542 [8] 7'0000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][3][2]$3555:
      Old ports: A=18'000000100000001000, B=18'000000000000010010, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$a$3541
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$a$3541 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$a$3541 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$a$3541 [17:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$a$3541 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$a$3541 [0] } = { 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$a$3541 [3] 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$a$3541 [1] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][3][1]$3552:
      Old ports: A=18'010000001000000000, B=18'000010000000000010, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539 [8:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539 [0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539 [9] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539 [1] 11'00000000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][3][0]$3549:
      Old ports: A=18'101110000000000000, B=18'010000010000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [10] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [17:14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [9:0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [13] 12'000000000000 }
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$2714:
      Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Memory.write_data [15:0] }, B=\SOC.Memory.write_data, Y=$auto$rtlil.cc:2582:Mux$2715
      New ports: A=\SOC.Memory.buffer [31:16], B=\SOC.Memory.write_data [31:16], Y=$auto$rtlil.cc:2582:Mux$2715 [31:16]
      New connections: $auto$rtlil.cc:2582:Mux$2715 [15:0] = \SOC.Memory.write_data [15:0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$1907: { $flatten\ResetBootSystem.$procmux$1902_CMP $flatten\ResetBootSystem.$procmux$1901_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1910:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$1910_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$1910_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$1910_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2003:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$2446 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$2446 [2]
      New connections: $auto$wreduce.cc:461:run$2446 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2024:
      Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0]
      New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] }
      New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1662: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1683_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1682_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1675_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1674_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1673_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1672_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1671_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1670_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1669_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1668_CMP $auto$opt_reduce.cc:134:opt_pmux$2210 $auto$opt_reduce.cc:134:opt_pmux$2208 $auto$opt_reduce.cc:134:opt_pmux$2206 $auto$opt_reduce.cc:134:opt_pmux$2204 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][3][7]$3570:
      Old ports: A=18'010000001000000000, B=18'000001000001001000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548 [3] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548 [8:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548 [2:0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548 [9] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548 [3] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548 [3] 5'00000 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1942:
      Old ports: A=3'101, B=3'011, Y=$auto$wreduce.cc:461:run$2450 [2:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$2450 [2:1]
      New connections: $auto$wreduce.cc:461:run$2450 [0] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1618:
      Old ports: A={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] }, B={ 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [24], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [31:6] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] \SOC.Core.instruction_register [24:20] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1645:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, B={ 19'0000000000000000000 \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [31], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:14] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1356:
      Old ports: A=\SOC.Memory.buffer, B={ 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data
      New ports: A=\SOC.Memory.buffer [31:8], B={ 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8]
      New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1190:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$2468 [0] 1'0 $auto$wreduce.cc:461:run$2469 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$2471 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$2468 [0] $auto$wreduce.cc:461:run$2469 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$2471 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$972:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2471 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2471 [0]
      New connections: $auto$wreduce.cc:461:run$2471 [1] = $auto$wreduce.cc:461:run$2471 [0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1327:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$2473 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$2475 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$2473 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$2475 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$915:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2475 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2475 [0]
      New connections: $auto$wreduce.cc:461:run$2475 [1] = $auto$wreduce.cc:461:run$2475 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$3546:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$a$3547, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536
      New ports: A={ 2'11 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$a$3547 [9] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548 [9] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][3]$b$3548 [3] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536 [3] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536 [15:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536 [8:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536 [2:0] } = { 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536 [3] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536 [3] 5'00000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$3543:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$a$3544 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [5] 1'1 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][2]$b$3545 [0] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [17:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [7:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [4:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [10] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [5] 4'0000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$3540:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$a$3541, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$b$3542, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$a$3541 [3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$a$3541 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$a$3541 [1] }, B={ 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$b$3542 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][1]$b$3542 [3] 1'0 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [17:12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [7:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [0] } = { 7'0000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [8] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [1] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$3537:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$a$3538 [10] 2'00 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539 [9] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539 [1] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][2][0]$b$3539 [1] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [8:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [14] 10'0000000000 }
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$2718:
      Old ports: A=$auto$rtlil.cc:2582:Mux$2715, B={ \SOC.Memory.buffer [31:8] \SOC.Memory.write_data [7:0] }, Y=$auto$rtlil.cc:2582:Mux$2719
      New ports: A={ $auto$rtlil.cc:2582:Mux$2715 [31:16] \SOC.Memory.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$2719 [31:8]
      New connections: $auto$rtlil.cc:2582:Mux$2719 [7:0] = \SOC.Memory.write_data [7:0]
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1916:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$1910_Y, Y=$flatten\ResetBootSystem.$procmux$1916_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$1910_Y [1], Y=$flatten\ResetBootSystem.$procmux$1916_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$1916_Y [0] = 1'0
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1629:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0]
      New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12:5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$3534:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$a$3535 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536 [16] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536 [10:9] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][1]$b$3536 [3] 2'00 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [16:15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [3:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [14:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [7:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [15] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [3] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$3531:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [14:13] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [10:9] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$a$3532 [1] }, B={ 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [11] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [1] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][1][0]$b$3533 [1] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [11:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [4:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [7:5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [14] 6'000000 }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$3528:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530, Y={ \SOC.Core.pc_write \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.MemoryDataMUX.option \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond \SOC.Bus.write \SOC.Core.Control_Unit.reg_write \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.ALU_Control.is_immediate }
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [11:8] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [4:3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$a$3529 [1] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [16:15] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [3:2] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$1001$rdmux[0][0][0]$b$3530 [0] }, Y={ \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.MemoryDataMUX.option [0] \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in [1] \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond \SOC.Bus.write \SOC.Core.Control_Unit.reg_write \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.ALU_Control.is_immediate }
      New connections: { \SOC.Core.pc_write \SOC.Core.MemoryDataMUX.option [1] \SOC.Core.ALU_Control.aluop_in [0] } = { \SOC.Core.AluInputBMUX.option [0] \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond }
  Optimizing cells in module \top.
Performed a total of 34 changes.

23.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

23.30.6. Executing OPT_DFF pass (perform DFF optimizations).

23.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 22 unused wires.
<suppressed ~2 debug messages>

23.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~1 debug messages>

23.30.9. Rerunning OPT passes. (Maybe there is more to do..)

23.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~62 debug messages>

23.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2294 ($sdff) from module top.

23.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

23.30.16. Rerunning OPT passes. (Maybe there is more to do..)

23.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~62 debug messages>

23.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.30.20. Executing OPT_DFF pass (perform DFF optimizations).

23.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.30.23. Finished OPT passes. (There is nothing left to do.)

23.31. Executing TECHMAP pass (map to technology primitives).

23.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

23.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

23.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $sdffe.
Using template $paramod$3111a1a8e90c88cc8c163ba5aed0203d96ddc46d\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $bmux.
Using extmapper simplemap for cells of type $tribuf.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using template $paramod$41ef080258eed1ff8fcfbb7776f540ab469a3d7b\_80_ecp5_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c4ef20b21801b37ea2d65c32a05dfe56e84a870d\_80_ecp5_alu for cells of type $alu.
Using template $paramod$2407ada40cc3dda6c6015be2b49b748cddb5a800\_90_demux for cells of type $demux.
Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux.
Using template $paramod$f1fc4bc1d42e857fca43ce0fdd0da6ff25c612c4\_90_pmux for cells of type $pmux.
Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux.
Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $dlatch.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu.
Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~4252 debug messages>

23.32. Executing OPT pass (performing simple optimizations).

23.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6087 debug messages>

23.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~4107 debug messages>
Removed a total of 1369 cells.

23.32.3. Executing OPT_DFF pass (perform DFF optimizations).

23.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 758 unused cells and 4043 unused wires.
<suppressed ~759 debug messages>

23.32.5. Finished fast OPT passes.

23.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

23.35. Executing TECHMAP pass (map to technology primitives).

23.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

23.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
No more expansions possible.
<suppressed ~817 debug messages>

23.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~31 debug messages>

23.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

23.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

23.39. Executing ATTRMVCP pass (move or copy attributes).

23.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3995 unused wires.
<suppressed ~1 debug messages>

23.41. Executing TECHMAP pass (map to technology primitives).

23.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

23.41.2. Continuing TECHMAP pass.

23.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$22302 ($mux).
Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$22301 ($logic_not).
<suppressed ~4 debug messages>

23.41.4. Executing OPT pass (performing simple optimizations).

23.41.4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.
<suppressed ~1 debug messages>

23.41.4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

23.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

23.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

23.41.4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

23.41.4.6. Executing OPT_DFF pass (perform DFF optimizations).

23.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

23.41.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

23.41.4.9. Rerunning OPT passes. (Maybe there is more to do..)

23.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

23.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

23.41.4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

23.41.4.13. Executing OPT_DFF pass (perform DFF optimizations).

23.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..

23.41.4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

23.41.4.16. Finished OPT passes. (There is nothing left to do.)
Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_.
No more expansions possible.
<suppressed ~4 debug messages>

23.42. Executing ABC9 pass.

23.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

23.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

23.42.3. Executing PROC pass (convert processes to netlists).

23.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22406'.
Cleaned up 1 empty switch.

23.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22407 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.3.4. Executing PROC_INIT pass (extract init attributes).

23.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22407'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22405_EN[3:0]$22411
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22405_DATA[3:0]$22413
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22405_ADDR[3:0]$22412
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22406'.

23.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22400_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22396_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22390_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22403_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22391_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22395_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22402_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22398_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22392_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22401_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22397_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22393_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22404_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22399_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22394_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22389_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22405_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22407'.
  created $dff cell `$procdff$22457' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22405_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22407'.
  created $dff cell `$procdff$22458' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22405_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22407'.
  created $dff cell `$procdff$22459' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22406'.
  created direct connection (no actual register cell created).

23.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22431'.
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22407'.
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22406'.
Cleaned up 1 empty switch.

23.42.3.12. Executing OPT_EXPR pass (perform const folding).

23.42.4. Executing PROC pass (convert processes to netlists).

23.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22477'.
Cleaned up 1 empty switch.

23.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22478 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.4.4. Executing PROC_INIT pass (extract init attributes).

23.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22478'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22476_EN[3:0]$22482
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22476_DATA[3:0]$22484
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22476_ADDR[3:0]$22483
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22477'.

23.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22468_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22463_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22469_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22465_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22474_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22473_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22461_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22470_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22466_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22471_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22475_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22464_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22472_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22467_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22462_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22460_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22476_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22478'.
  created $dff cell `$procdff$22528' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22476_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22478'.
  created $dff cell `$procdff$22529' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22476_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22478'.
  created $dff cell `$procdff$22530' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22477'.
  created direct connection (no actual register cell created).

23.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22502'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22478'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22477'.
Cleaned up 1 empty switch.

23.42.4.12. Executing OPT_EXPR pass (perform const folding).

23.42.5. Executing PROC pass (convert processes to netlists).

23.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22548'.
Cleaned up 1 empty switch.

23.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22549 in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.5.4. Executing PROC_INIT pass (extract init attributes).

23.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22549'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22547_EN[3:0]$22554
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22547_DATA[3:0]$22555
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22547_ADDR[3:0]$22553
Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22548'.

23.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.\i' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22531_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22536_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22537_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22533_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22542_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22541_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22534_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22538_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22546_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22543_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22544_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22539_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22532_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22545_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22540_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22535_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22547_ADDR' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22549'.
  created $dff cell `$procdff$22599' with positive edge clock.
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22547_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22549'.
  created $dff cell `$procdff$22600' with positive edge clock.
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22547_DATA' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22549'.
  created $dff cell `$procdff$22601' with positive edge clock.
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.\muxwre' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22548'.
  created direct connection (no actual register cell created).

23.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22573'.
Found and cleaned up 1 empty switch in `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22549'.
Removing empty process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22548'.
Cleaned up 1 empty switch.

23.42.5.12. Executing OPT_EXPR pass (perform const folding).

23.42.6. Executing PROC pass (convert processes to netlists).

23.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22619'.
Cleaned up 1 empty switch.

23.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22620 in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.6.4. Executing PROC_INIT pass (extract init attributes).

23.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22620'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22618_EN[3:0]$22624
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22618_DATA[3:0]$22626
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22618_ADDR[3:0]$22625
Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22619'.

23.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.\i' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22602_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22603_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22608_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22609_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22614_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22615_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22606_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22616_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22612_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22617_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22611_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22605_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22604_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22610_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22613_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22607_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22618_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22620'.
  created $dff cell `$procdff$22670' with positive edge clock.
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22618_ADDR' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22620'.
  created $dff cell `$procdff$22671' with positive edge clock.
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22618_DATA' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22620'.
  created $dff cell `$procdff$22672' with positive edge clock.
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22619'.
  created direct connection (no actual register cell created).

23.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22644'.
Found and cleaned up 1 empty switch in `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22620'.
Removing empty process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22619'.
Cleaned up 1 empty switch.

23.42.6.12. Executing OPT_EXPR pass (perform const folding).

23.42.7. Executing PROC pass (convert processes to netlists).

23.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22690'.
Cleaned up 1 empty switch.

23.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22691 in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.7.4. Executing PROC_INIT pass (extract init attributes).

23.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22691'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22689_EN[3:0]$22695
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22689_DATA[3:0]$22696
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22689_ADDR[3:0]$22697
Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22690'.

23.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.\i' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22673_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22674_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22679_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22680_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22685_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22684_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22675_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22676_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22681_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22682_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22687_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22688_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22678_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22686_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22683_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22677_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22689_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22691'.
  created $dff cell `$procdff$22741' with positive edge clock.
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22689_DATA' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22691'.
  created $dff cell `$procdff$22742' with positive edge clock.
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22689_ADDR' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22691'.
  created $dff cell `$procdff$22743' with positive edge clock.
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22690'.
  created direct connection (no actual register cell created).

23.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22715'.
Found and cleaned up 1 empty switch in `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22691'.
Removing empty process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22690'.
Cleaned up 1 empty switch.

23.42.7.12. Executing OPT_EXPR pass (perform const folding).

23.42.8. Executing PROC pass (convert processes to netlists).

23.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22761'.
Cleaned up 1 empty switch.

23.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22762 in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.8.4. Executing PROC_INIT pass (extract init attributes).

23.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22762'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22760_EN[3:0]$22766
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22760_DATA[3:0]$22767
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22760_ADDR[3:0]$22768
Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22761'.

23.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.\i' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22744_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22749_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22748_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22756_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22750_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22757_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22758_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22755_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22754_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22745_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22746_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22751_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22752_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22759_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22753_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22747_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22760_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22762'.
  created $dff cell `$procdff$22812' with positive edge clock.
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22760_DATA' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22762'.
  created $dff cell `$procdff$22813' with positive edge clock.
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22760_ADDR' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22762'.
  created $dff cell `$procdff$22814' with positive edge clock.
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.\muxwre' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22761'.
  created direct connection (no actual register cell created).

23.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22786'.
Found and cleaned up 1 empty switch in `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22762'.
Removing empty process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22761'.
Cleaned up 1 empty switch.

23.42.8.12. Executing OPT_EXPR pass (perform const folding).

23.42.9. Executing PROC pass (convert processes to netlists).

23.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22832'.
Cleaned up 1 empty switch.

23.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22833 in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.9.4. Executing PROC_INIT pass (extract init attributes).

23.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22833'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22831_EN[3:0]$22839
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22831_DATA[3:0]$22838
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22831_ADDR[3:0]$22837
Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22832'.

23.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.\i' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22818_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22819_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22820_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22824_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22825_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22826_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22830_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22816_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22821_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22822_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22827_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22828_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22829_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22823_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22817_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22815_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22831_ADDR' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22833'.
  created $dff cell `$procdff$22883' with positive edge clock.
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22831_DATA' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22833'.
  created $dff cell `$procdff$22884' with positive edge clock.
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22831_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22833'.
  created $dff cell `$procdff$22885' with positive edge clock.
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.\muxwre' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22832'.
  created direct connection (no actual register cell created).

23.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22857'.
Found and cleaned up 1 empty switch in `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22833'.
Removing empty process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22832'.
Cleaned up 1 empty switch.

23.42.9.12. Executing OPT_EXPR pass (perform const folding).

23.42.10. Executing PROC pass (convert processes to netlists).

23.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22903'.
Cleaned up 1 empty switch.

23.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22904 in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.10.4. Executing PROC_INIT pass (extract init attributes).

23.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22904'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22902_EN[3:0]$22909
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22902_DATA[3:0]$22908
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22902_ADDR[3:0]$22910
Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22903'.

23.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.\i' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22894_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22895_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22896_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22886_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22901_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22888_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22889_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22890_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22892_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22897_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22898_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22900_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22891_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22899_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22893_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22887_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22902_DATA' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22904'.
  created $dff cell `$procdff$22954' with positive edge clock.
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22902_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22904'.
  created $dff cell `$procdff$22955' with positive edge clock.
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22902_ADDR' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22904'.
  created $dff cell `$procdff$22956' with positive edge clock.
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.\muxwre' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22903'.
  created direct connection (no actual register cell created).

23.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22928'.
Found and cleaned up 1 empty switch in `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22904'.
Removing empty process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22903'.
Cleaned up 1 empty switch.

23.42.10.12. Executing OPT_EXPR pass (perform const folding).

23.42.11. Executing PROC pass (convert processes to netlists).

23.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22974'.
Cleaned up 1 empty switch.

23.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22975 in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.11.4. Executing PROC_INIT pass (extract init attributes).

23.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22975'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22973_EN[3:0]$22981
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22973_DATA[3:0]$22979
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22973_ADDR[3:0]$22980
Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22974'.

23.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.\i' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22968_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22972_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22961_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22971_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22970_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22966_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22965_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22959_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22958_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22957_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22962_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22960_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22964_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22967_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22969_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22963_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22973_DATA' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22975'.
  created $dff cell `$procdff$23025' with positive edge clock.
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22973_ADDR' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22975'.
  created $dff cell `$procdff$23026' with positive edge clock.
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22973_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22975'.
  created $dff cell `$procdff$23027' with positive edge clock.
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22974'.
  created direct connection (no actual register cell created).

23.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22999'.
Found and cleaned up 1 empty switch in `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22975'.
Removing empty process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22974'.
Cleaned up 1 empty switch.

23.42.11.12. Executing OPT_EXPR pass (perform const folding).

23.42.12. Executing PROC pass (convert processes to netlists).

23.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23045'.
Cleaned up 1 empty switch.

23.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23046 in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.12.4. Executing PROC_INIT pass (extract init attributes).

23.42.12.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.12.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23046'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23044_EN[3:0]$23051
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23044_DATA[3:0]$23052
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23044_ADDR[3:0]$23050
Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23045'.

23.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23028_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23043_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.\i' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23038_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23037_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23032_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23042_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23031_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23041_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23040_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23035_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23034_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23036_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23030_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23029_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23039_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23033_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23044_ADDR' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23046'.
  created $dff cell `$procdff$23096' with positive edge clock.
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23044_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23046'.
  created $dff cell `$procdff$23097' with positive edge clock.
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23044_DATA' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23046'.
  created $dff cell `$procdff$23098' with positive edge clock.
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.\muxwre' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23045'.
  created direct connection (no actual register cell created).

23.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23070'.
Found and cleaned up 1 empty switch in `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23046'.
Removing empty process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23045'.
Cleaned up 1 empty switch.

23.42.12.12. Executing OPT_EXPR pass (perform const folding).

23.42.13. Executing PROC pass (convert processes to netlists).

23.42.13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23116'.
Cleaned up 1 empty switch.

23.42.13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23117 in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.13.4. Executing PROC_INIT pass (extract init attributes).

23.42.13.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.13.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.13.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23117'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23115_EN[3:0]$23121
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23115_DATA[3:0]$23122
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23115_ADDR[3:0]$23123
Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23116'.

23.42.13.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.13.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.\i' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23113_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23114_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23108_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23107_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23102_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23112_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23101_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23111_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23110_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23106_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23105_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23104_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23100_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23099_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23109_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23103_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23115_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23117'.
  created $dff cell `$procdff$23167' with positive edge clock.
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23115_DATA' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23117'.
  created $dff cell `$procdff$23168' with positive edge clock.
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23115_ADDR' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23117'.
  created $dff cell `$procdff$23169' with positive edge clock.
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.\muxwre' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23116'.
  created direct connection (no actual register cell created).

23.42.13.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23141'.
Found and cleaned up 1 empty switch in `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23117'.
Removing empty process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23116'.
Cleaned up 1 empty switch.

23.42.13.12. Executing OPT_EXPR pass (perform const folding).

23.42.14. Executing PROC pass (convert processes to netlists).

23.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23187'.
Cleaned up 1 empty switch.

23.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23188 in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.14.4. Executing PROC_INIT pass (extract init attributes).

23.42.14.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.14.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23188'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23186_EN[3:0]$23194
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23186_DATA[3:0]$23193
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23186_ADDR[3:0]$23192
Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23187'.

23.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.\i' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23178_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23172_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23177_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23171_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23181_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23180_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23176_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23175_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23174_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23170_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23182_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23183_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23184_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23185_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23179_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23173_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23186_ADDR' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23188'.
  created $dff cell `$procdff$23238' with positive edge clock.
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23186_DATA' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23188'.
  created $dff cell `$procdff$23239' with positive edge clock.
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23186_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23188'.
  created $dff cell `$procdff$23240' with positive edge clock.
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23187'.
  created direct connection (no actual register cell created).

23.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23212'.
Found and cleaned up 1 empty switch in `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23188'.
Removing empty process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23187'.
Cleaned up 1 empty switch.

23.42.14.12. Executing OPT_EXPR pass (perform const folding).

23.42.15. Executing PROC pass (convert processes to netlists).

23.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23258'.
Cleaned up 1 empty switch.

23.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23259 in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.15.4. Executing PROC_INIT pass (extract init attributes).

23.42.15.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.15.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23259'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23257_EN[3:0]$23263
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23257_DATA[3:0]$23264
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23257_ADDR[3:0]$23265
Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23258'.

23.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23254_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23253_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23248_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23247_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23242_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23256_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23252_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23251_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23250_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23246_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23245_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23244_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.\i' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23255_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23249_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23243_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23241_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23257_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23259'.
  created $dff cell `$procdff$23309' with positive edge clock.
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23257_DATA' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23259'.
  created $dff cell `$procdff$23310' with positive edge clock.
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23257_ADDR' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23259'.
  created $dff cell `$procdff$23311' with positive edge clock.
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23258'.
  created direct connection (no actual register cell created).

23.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23283'.
Found and cleaned up 1 empty switch in `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23259'.
Removing empty process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23258'.
Cleaned up 1 empty switch.

23.42.15.12. Executing OPT_EXPR pass (perform const folding).

23.42.16. Executing PROC pass (convert processes to netlists).

23.42.16.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23329'.
Cleaned up 1 empty switch.

23.42.16.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23330 in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.16.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.16.4. Executing PROC_INIT pass (extract init attributes).

23.42.16.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.16.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.16.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23330'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23328_EN[3:0]$23334
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23328_DATA[3:0]$23335
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23328_ADDR[3:0]$23336
Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23329'.

23.42.16.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.16.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.\i' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23324_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23323_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23318_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23317_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23327_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23326_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23322_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23321_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23320_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23316_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23315_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23314_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23312_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23325_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23319_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23313_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23328_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23330'.
  created $dff cell `$procdff$23380' with positive edge clock.
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23328_DATA' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23330'.
  created $dff cell `$procdff$23381' with positive edge clock.
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23328_ADDR' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23330'.
  created $dff cell `$procdff$23382' with positive edge clock.
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.\muxwre' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23329'.
  created direct connection (no actual register cell created).

23.42.16.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.16.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23354'.
Found and cleaned up 1 empty switch in `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23330'.
Removing empty process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23329'.
Cleaned up 1 empty switch.

23.42.16.12. Executing OPT_EXPR pass (perform const folding).

23.42.17. Executing PROC pass (convert processes to netlists).

23.42.17.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23400'.
Cleaned up 1 empty switch.

23.42.17.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23401 in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.17.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.17.4. Executing PROC_INIT pass (extract init attributes).

23.42.17.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.17.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.17.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23401'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23399_EN[3:0]$23407
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23399_DATA[3:0]$23406
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23399_ADDR[3:0]$23405
Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23400'.

23.42.17.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.17.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.\i' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23394_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23393_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23388_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23398_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23387_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23397_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23396_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23392_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23391_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23390_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23384_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23386_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23385_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23383_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23395_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23389_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23399_ADDR' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23401'.
  created $dff cell `$procdff$23451' with positive edge clock.
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23399_DATA' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23401'.
  created $dff cell `$procdff$23452' with positive edge clock.
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23399_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23401'.
  created $dff cell `$procdff$23453' with positive edge clock.
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.\muxwre' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23400'.
  created direct connection (no actual register cell created).

23.42.17.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.17.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23425'.
Found and cleaned up 1 empty switch in `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23401'.
Removing empty process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23400'.
Cleaned up 1 empty switch.

23.42.17.12. Executing OPT_EXPR pass (perform const folding).

23.42.18. Executing PROC pass (convert processes to netlists).

23.42.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23471'.
Cleaned up 1 empty switch.

23.42.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23472 in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.18.4. Executing PROC_INIT pass (extract init attributes).

23.42.18.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.18.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23472'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23470_EN[3:0]$23477
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23470_DATA[3:0]$23478
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23470_ADDR[3:0]$23476
Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23471'.

23.42.18.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.18.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.\i' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23468_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23458_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23463_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23464_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23469_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23467_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23457_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23466_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23462_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23461_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23460_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23456_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23455_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23454_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23465_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23459_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23470_ADDR' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23472'.
  created $dff cell `$procdff$23522' with positive edge clock.
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23470_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23472'.
  created $dff cell `$procdff$23523' with positive edge clock.
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23470_DATA' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23472'.
  created $dff cell `$procdff$23524' with positive edge clock.
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23471'.
  created direct connection (no actual register cell created).

23.42.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23496'.
Found and cleaned up 1 empty switch in `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23472'.
Removing empty process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23471'.
Cleaned up 1 empty switch.

23.42.18.12. Executing OPT_EXPR pass (perform const folding).

23.42.19. Executing PROC pass (convert processes to netlists).

23.42.19.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23542'.
Cleaned up 1 empty switch.

23.42.19.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23543 in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.19.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.19.4. Executing PROC_INIT pass (extract init attributes).

23.42.19.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.19.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.19.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23543'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23541_EN[3:0]$23547
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23541_DATA[3:0]$23548
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23541_ADDR[3:0]$23549
Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23542'.

23.42.19.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.19.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.\i' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23540_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23539_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23534_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23533_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23528_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23538_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23527_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23537_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23536_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23532_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23531_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23530_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23526_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23525_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23535_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23529_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23541_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23543'.
  created $dff cell `$procdff$23593' with positive edge clock.
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23541_DATA' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23543'.
  created $dff cell `$procdff$23594' with positive edge clock.
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23541_ADDR' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23543'.
  created $dff cell `$procdff$23595' with positive edge clock.
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.\muxwre' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23542'.
  created direct connection (no actual register cell created).

23.42.19.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.19.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23567'.
Found and cleaned up 1 empty switch in `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23543'.
Removing empty process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23542'.
Cleaned up 1 empty switch.

23.42.19.12. Executing OPT_EXPR pass (perform const folding).

23.42.20. Executing PROC pass (convert processes to netlists).

23.42.20.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23613'.
Cleaned up 1 empty switch.

23.42.20.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23614 in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.20.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.20.4. Executing PROC_INIT pass (extract init attributes).

23.42.20.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.20.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.20.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23614'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23612_EN[3:0]$23618
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23612_DATA[3:0]$23619
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23612_ADDR[3:0]$23620
Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23613'.

23.42.20.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.20.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.\i' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23603_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23610_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23609_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23604_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23598_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23608_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23597_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23607_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23606_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23602_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23601_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23600_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23596_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23611_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23605_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23599_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23612_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23614'.
  created $dff cell `$procdff$23664' with positive edge clock.
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23612_DATA' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23614'.
  created $dff cell `$procdff$23665' with positive edge clock.
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23612_ADDR' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23614'.
  created $dff cell `$procdff$23666' with positive edge clock.
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23613'.
  created direct connection (no actual register cell created).

23.42.20.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.20.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23638'.
Found and cleaned up 1 empty switch in `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23614'.
Removing empty process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23613'.
Cleaned up 1 empty switch.

23.42.20.12. Executing OPT_EXPR pass (perform const folding).

23.42.21. Executing PROC pass (convert processes to netlists).

23.42.21.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23684'.
Cleaned up 1 empty switch.

23.42.21.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23685 in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.21.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.21.4. Executing PROC_INIT pass (extract init attributes).

23.42.21.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.21.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.21.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23685'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23683_EN[3:0]$23689
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23683_DATA[3:0]$23690
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23683_ADDR[3:0]$23691
Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23684'.

23.42.21.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.21.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.\i' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23680_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23679_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23668_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23682_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23673_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23674_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23678_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23670_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23671_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23672_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23676_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23677_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23681_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23675_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23669_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23667_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23683_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23685'.
  created $dff cell `$procdff$23735' with positive edge clock.
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23683_DATA' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23685'.
  created $dff cell `$procdff$23736' with positive edge clock.
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23683_ADDR' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23685'.
  created $dff cell `$procdff$23737' with positive edge clock.
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.\muxwre' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23684'.
  created direct connection (no actual register cell created).

23.42.21.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.21.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23709'.
Found and cleaned up 1 empty switch in `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23685'.
Removing empty process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23684'.
Cleaned up 1 empty switch.

23.42.21.12. Executing OPT_EXPR pass (perform const folding).

23.42.22. Executing PROC pass (convert processes to netlists).

23.42.22.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23755'.
Cleaned up 1 empty switch.

23.42.22.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23756 in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.22.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.22.4. Executing PROC_INIT pass (extract init attributes).

23.42.22.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.22.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.22.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23756'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23754_EN[3:0]$23761
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23754_DATA[3:0]$23762
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23754_ADDR[3:0]$23760
Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23755'.

23.42.22.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.22.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.\i' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23738_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23753_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23743_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23744_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23749_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23750_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23752_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23748_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23747_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23746_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23742_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23741_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23740_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23751_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23745_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23739_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23754_ADDR' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23756'.
  created $dff cell `$procdff$23806' with positive edge clock.
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23754_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23756'.
  created $dff cell `$procdff$23807' with positive edge clock.
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23754_DATA' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23756'.
  created $dff cell `$procdff$23808' with positive edge clock.
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.\muxwre' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23755'.
  created direct connection (no actual register cell created).

23.42.22.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.22.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23780'.
Found and cleaned up 1 empty switch in `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23756'.
Removing empty process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23755'.
Cleaned up 1 empty switch.

23.42.22.12. Executing OPT_EXPR pass (perform const folding).

23.42.23. Executing PROC pass (convert processes to netlists).

23.42.23.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23826'.
Cleaned up 1 empty switch.

23.42.23.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23827 in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.23.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.23.4. Executing PROC_INIT pass (extract init attributes).

23.42.23.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.23.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.23.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23827'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23825_EN[3:0]$23831
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23825_DATA[3:0]$23832
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23825_ADDR[3:0]$23833
Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23826'.

23.42.23.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.23.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.\i' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23823_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23818_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23817_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23812_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23822_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23811_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23821_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23820_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23816_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23815_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23814_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23810_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23809_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23824_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23819_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23813_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23825_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23827'.
  created $dff cell `$procdff$23877' with positive edge clock.
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23825_DATA' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23827'.
  created $dff cell `$procdff$23878' with positive edge clock.
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23825_ADDR' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23827'.
  created $dff cell `$procdff$23879' with positive edge clock.
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.\muxwre' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23826'.
  created direct connection (no actual register cell created).

23.42.23.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.23.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23851'.
Found and cleaned up 1 empty switch in `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23827'.
Removing empty process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23826'.
Cleaned up 1 empty switch.

23.42.23.12. Executing OPT_EXPR pass (perform const folding).

23.42.24. Executing PROC pass (convert processes to netlists).

23.42.24.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23897'.
Cleaned up 1 empty switch.

23.42.24.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23898 in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.24.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.24.4. Executing PROC_INIT pass (extract init attributes).

23.42.24.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.24.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.24.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23898'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23896_EN[3:0]$23903
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23896_DATA[3:0]$23904
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23896_ADDR[3:0]$23902
Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23897'.

23.42.24.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.24.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23885_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.\i' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23882_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23883_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23887_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23888_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23892_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23884_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23893_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23894_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23889_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23890_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23895_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23880_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23891_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23886_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23881_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23896_ADDR' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23898'.
  created $dff cell `$procdff$23948' with positive edge clock.
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23896_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23898'.
  created $dff cell `$procdff$23949' with positive edge clock.
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23896_DATA' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23898'.
  created $dff cell `$procdff$23950' with positive edge clock.
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23897'.
  created direct connection (no actual register cell created).

23.42.24.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.24.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23922'.
Found and cleaned up 1 empty switch in `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23898'.
Removing empty process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23897'.
Cleaned up 1 empty switch.

23.42.24.12. Executing OPT_EXPR pass (perform const folding).

23.42.25. Executing PROC pass (convert processes to netlists).

23.42.25.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23968'.
Cleaned up 1 empty switch.

23.42.25.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23969 in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.25.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.25.4. Executing PROC_INIT pass (extract init attributes).

23.42.25.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.25.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.25.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23969'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23967_EN[3:0]$23975
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23967_DATA[3:0]$23973
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23967_ADDR[3:0]$23974
Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23968'.

23.42.25.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.25.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.\i' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23957_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23951_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23952_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23966_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23962_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23961_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23960_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23956_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23955_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23954_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23964_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23963_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23958_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23965_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23959_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23953_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23967_DATA' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23969'.
  created $dff cell `$procdff$24019' with positive edge clock.
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23967_ADDR' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23969'.
  created $dff cell `$procdff$24020' with positive edge clock.
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23967_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23969'.
  created $dff cell `$procdff$24021' with positive edge clock.
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23968'.
  created direct connection (no actual register cell created).

23.42.25.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.25.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23993'.
Found and cleaned up 1 empty switch in `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23969'.
Removing empty process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23968'.
Cleaned up 1 empty switch.

23.42.25.12. Executing OPT_EXPR pass (perform const folding).

23.42.26. Executing PROC pass (convert processes to netlists).

23.42.26.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24039'.
Cleaned up 1 empty switch.

23.42.26.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24040 in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.26.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.26.4. Executing PROC_INIT pass (extract init attributes).

23.42.26.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.26.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.26.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24040'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24038_EN[3:0]$24046
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24038_DATA[3:0]$24045
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24038_ADDR[3:0]$24044
Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24039'.

23.42.26.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.26.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.\i' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24022_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24037_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24031_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24025_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24027_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24028_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24034_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24026_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24032_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24033_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24023_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24024_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24029_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24030_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24035_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24036_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24038_ADDR' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24040'.
  created $dff cell `$procdff$24090' with positive edge clock.
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24038_DATA' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24040'.
  created $dff cell `$procdff$24091' with positive edge clock.
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24038_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24040'.
  created $dff cell `$procdff$24092' with positive edge clock.
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.\muxwre' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24039'.
  created direct connection (no actual register cell created).

23.42.26.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.26.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24064'.
Found and cleaned up 1 empty switch in `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24040'.
Removing empty process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24039'.
Cleaned up 1 empty switch.

23.42.26.12. Executing OPT_EXPR pass (perform const folding).

23.42.27. Executing PROC pass (convert processes to netlists).

23.42.27.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24110'.
Cleaned up 1 empty switch.

23.42.27.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24111 in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.27.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.27.4. Executing PROC_INIT pass (extract init attributes).

23.42.27.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.27.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.27.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24111'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24109_EN[3:0]$24115
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24109_DATA[3:0]$24117
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24109_ADDR[3:0]$24116
Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24110'.

23.42.27.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.27.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.\i' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24105_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24099_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24093_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24106_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24097_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24094_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24095_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24096_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24100_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24101_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24102_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24107_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24108_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24098_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24103_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24104_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24109_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24111'.
  created $dff cell `$procdff$24161' with positive edge clock.
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24109_ADDR' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24111'.
  created $dff cell `$procdff$24162' with positive edge clock.
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24109_DATA' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24111'.
  created $dff cell `$procdff$24163' with positive edge clock.
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.\muxwre' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24110'.
  created direct connection (no actual register cell created).

23.42.27.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.27.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24135'.
Found and cleaned up 1 empty switch in `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24111'.
Removing empty process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24110'.
Cleaned up 1 empty switch.

23.42.27.12. Executing OPT_EXPR pass (perform const folding).

23.42.28. Executing PROC pass (convert processes to netlists).

23.42.28.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24181'.
Cleaned up 1 empty switch.

23.42.28.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24182 in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.28.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.28.4. Executing PROC_INIT pass (extract init attributes).

23.42.28.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.28.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.28.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24182'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24180_EN[3:0]$24188
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24180_DATA[3:0]$24187
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24180_ADDR[3:0]$24186
Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24181'.

23.42.28.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.28.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.\i' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24179_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24173_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24167_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24169_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24170_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24174_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24175_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24176_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24164_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24168_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24165_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24166_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24171_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24172_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24177_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24178_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24180_ADDR' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24182'.
  created $dff cell `$procdff$24232' with positive edge clock.
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24180_DATA' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24182'.
  created $dff cell `$procdff$24233' with positive edge clock.
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24180_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24182'.
  created $dff cell `$procdff$24234' with positive edge clock.
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24181'.
  created direct connection (no actual register cell created).

23.42.28.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.28.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24206'.
Found and cleaned up 1 empty switch in `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24182'.
Removing empty process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24181'.
Cleaned up 1 empty switch.

23.42.28.12. Executing OPT_EXPR pass (perform const folding).

23.42.29. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$8073.$auto$simplemap.cc:267:simplemap_mux$22304
Found an SCC: $techmap$auto$ff.cc:266:slice$8072.$auto$simplemap.cc:267:simplemap_mux$22304
Found an SCC: $techmap$auto$ff.cc:266:slice$8071.$auto$simplemap.cc:267:simplemap_mux$22304
Found an SCC: $techmap$auto$ff.cc:266:slice$8070.$auto$simplemap.cc:267:simplemap_mux$22304
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$21415 $auto$ff.cc:266:slice$6138 $auto$simplemap.cc:126:simplemap_reduce$6245 $auto$simplemap.cc:126:simplemap_reduce$6260 $auto$ff.cc:266:slice$6139 $auto$ff.cc:266:slice$6140 $auto$opt_expr.cc:613:replace_const_cells$21403 $auto$simplemap.cc:267:simplemap_mux$12899 $auto$simplemap.cc:126:simplemap_reduce$12921 $auto$simplemap.cc:126:simplemap_reduce$12918 $auto$simplemap.cc:75:simplemap_bitop$12900 $auto$simplemap.cc:267:simplemap_mux$6226 $auto$simplemap.cc:225:simplemap_logbin$6235 $auto$simplemap.cc:196:simplemap_lognot$6250 $auto$simplemap.cc:126:simplemap_reduce$6248 $auto$simplemap.cc:126:simplemap_reduce$6246 $auto$simplemap.cc:126:simplemap_reduce$12909 $auto$simplemap.cc:75:simplemap_bitop$12902 $auto$simplemap.cc:196:simplemap_lognot$6265 $auto$simplemap.cc:126:simplemap_reduce$6263 $auto$simplemap.cc:126:simplemap_reduce$6261 $auto$opt_expr.cc:613:replace_const_cells$21247 $auto$ff.cc:266:slice$6141 $auto$simplemap.cc:126:simplemap_reduce$4241 $auto$simplemap.cc:126:simplemap_reduce$4239 $auto$simplemap.cc:225:simplemap_logbin$6185 $auto$simplemap.cc:196:simplemap_lognot$6195 $auto$simplemap.cc:126:simplemap_reduce$6193 $auto$opt_expr.cc:613:replace_const_cells$21257 $auto$simplemap.cc:267:simplemap_mux$12898 $auto$simplemap.cc:126:simplemap_reduce$12912
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$21281 $auto$ff.cc:266:slice$6142 $auto$simplemap.cc:38:simplemap_not$11507 $auto$ff.cc:266:slice$6148 $auto$simplemap.cc:126:simplemap_reduce$6283 $auto$simplemap.cc:38:simplemap_not$11508 $auto$ff.cc:266:slice$6149 $auto$ff.cc:266:slice$6150 $auto$ff.cc:266:slice$6145 $auto$ff.cc:266:slice$6144 $auto$simplemap.cc:126:simplemap_reduce$6280 $auto$ff.cc:266:slice$6143 $auto$simplemap.cc:38:simplemap_not$11505 $auto$ff.cc:266:slice$6146 $auto$simplemap.cc:126:simplemap_reduce$6286 $auto$simplemap.cc:126:simplemap_reduce$6282 $auto$ff.cc:266:slice$6147 $auto$simplemap.cc:126:simplemap_reduce$4268 $auto$simplemap.cc:196:simplemap_lognot$6292 $auto$simplemap.cc:126:simplemap_reduce$6290 $auto$simplemap.cc:126:simplemap_reduce$6288 $auto$simplemap.cc:126:simplemap_reduce$6285 $auto$simplemap.cc:126:simplemap_reduce$6281 $auto$simplemap.cc:38:simplemap_not$11504
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$21283 $auto$ff.cc:266:slice$5998 $auto$simplemap.cc:126:simplemap_reduce$6120 $auto$simplemap.cc:126:simplemap_reduce$6093 $auto$ff.cc:266:slice$5999 $auto$simplemap.cc:38:simplemap_not$11536 $auto$ff.cc:266:slice$6000 $auto$simplemap.cc:126:simplemap_reduce$6125 $auto$simplemap.cc:126:simplemap_reduce$6121 $auto$simplemap.cc:126:simplemap_reduce$6098 $auto$simplemap.cc:126:simplemap_reduce$6094 $auto$simplemap.cc:38:simplemap_not$11537 $auto$ff.cc:266:slice$6001 $auto$simplemap.cc:38:simplemap_not$11538 $auto$ff.cc:266:slice$6002 $auto$simplemap.cc:126:simplemap_reduce$6122 $auto$simplemap.cc:126:simplemap_reduce$6095 $auto$simplemap.cc:38:simplemap_not$11539 $auto$ff.cc:266:slice$6003 $auto$simplemap.cc:38:simplemap_not$11540 $auto$ff.cc:266:slice$6004 $auto$simplemap.cc:126:simplemap_reduce$6101 $auto$simplemap.cc:126:simplemap_reduce$6099 $auto$simplemap.cc:126:simplemap_reduce$6096 $auto$simplemap.cc:126:simplemap_reduce$6123 $auto$simplemap.cc:38:simplemap_not$11541 $auto$ff.cc:266:slice$6005 $auto$simplemap.cc:225:simplemap_logbin$6078 $auto$simplemap.cc:196:simplemap_lognot$6105 $auto$simplemap.cc:126:simplemap_reduce$6103 $auto$ff.cc:266:slice$6006 $auto$simplemap.cc:167:logic_reduce$4220 $auto$simplemap.cc:225:simplemap_logbin$6077 $auto$simplemap.cc:196:simplemap_lognot$6132 $auto$simplemap.cc:126:simplemap_reduce$6130 $auto$simplemap.cc:126:simplemap_reduce$6128 $auto$simplemap.cc:126:simplemap_reduce$6126
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$4457 $auto$simplemap.cc:38:simplemap_not$4156 $auto$simplemap.cc:38:simplemap_not$14981 $auto$ff.cc:266:slice$3681 $auto$ff.cc:479:convert_ce_over_srst$21589 $auto$ff.cc:266:slice$3682 $auto$ff.cc:479:convert_ce_over_srst$21591 $auto$simplemap.cc:126:simplemap_reduce$4160 $auto$ff.cc:266:slice$3680 $auto$ff.cc:479:convert_ce_over_srst$21587 $auto$simplemap.cc:38:simplemap_not$14979 $auto$ff.cc:266:slice$3679 $auto$ff.cc:479:convert_ce_over_srst$21585 $auto$simplemap.cc:126:simplemap_reduce$4163 $auto$simplemap.cc:126:simplemap_reduce$4159 $auto$opt_expr.cc:613:replace_const_cells$21537 $auto$simplemap.cc:38:simplemap_not$4073 $auto$alumacc.cc:485:replace_alu$2575.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$2575.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2575.slice[0].ccu2c_i $auto$ff.cc:266:slice$3678 $auto$ff.cc:479:convert_ce_over_srst$21583 $auto$simplemap.cc:126:simplemap_reduce$4396 $auto$simplemap.cc:75:simplemap_bitop$4157 $auto$simplemap.cc:126:simplemap_reduce$4370 $auto$simplemap.cc:126:simplemap_reduce$4459 $auto$simplemap.cc:126:simplemap_reduce$4456 $auto$simplemap.cc:126:simplemap_reduce$4165 $auto$simplemap.cc:126:simplemap_reduce$4161 $auto$simplemap.cc:38:simplemap_not$20126 $auto$ff.cc:266:slice$3683 $auto$ff.cc:479:convert_ce_over_srst$21593 $auto$simplemap.cc:126:simplemap_reduce$4372
Found 8 SCCs in module top.
Found 8 SCCs.

23.42.30. Executing ABC9_OPS pass (helper functions for ABC9).

23.42.31. Executing PROC pass (convert processes to netlists).

23.42.31.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

23.42.31.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

23.42.31.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

23.42.31.4. Executing PROC_INIT pass (extract init attributes).

23.42.31.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.31.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

23.42.31.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

23.42.31.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.31.9. Executing PROC_DFF pass (convert process syncs to FFs).

23.42.31.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.31.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

23.42.31.12. Executing OPT_EXPR pass (perform const folding).

23.42.32. Executing TECHMAP pass (map to technology primitives).

23.42.32.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

23.42.32.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~212 debug messages>

23.42.33. Executing OPT pass (performing simple optimizations).

23.42.33.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Optimizing module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Optimizing module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Optimizing module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Optimizing module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Optimizing module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Optimizing module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Optimizing module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Optimizing module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Optimizing module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Optimizing module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Optimizing module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Optimizing module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Optimizing module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Optimizing module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Optimizing module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Optimizing module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
Optimizing module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Optimizing module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
Optimizing module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Optimizing module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Optimizing module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Optimizing module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Optimizing module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.

23.42.33.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

23.42.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

23.42.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Performed a total of 0 changes.

23.42.33.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

23.42.33.6. Executing OPT_DFF pass (perform DFF optimizations).

23.42.33.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4..

23.42.33.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Optimizing module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Optimizing module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Optimizing module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Optimizing module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Optimizing module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Optimizing module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Optimizing module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Optimizing module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Optimizing module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Optimizing module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Optimizing module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Optimizing module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Optimizing module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Optimizing module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Optimizing module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Optimizing module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Optimizing module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Optimizing module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Optimizing module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Optimizing module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Optimizing module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.

23.42.33.9. Finished OPT passes. (There is nothing left to do.)

23.42.34. Executing TECHMAP pass (map to technology primitives).

23.42.34.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

23.42.34.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4 for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4 for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4 for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4 for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4 for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4 for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4 for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4 for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4 for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4 for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4 for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4 for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4 for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4 for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4 for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4 for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4 for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4 for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4 for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4 for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4 for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4 for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4 for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4 for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~320 debug messages>

23.42.35. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

23.42.36. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

23.42.37. Executing ABC9_OPS pass (helper functions for ABC9).

23.42.38. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

23.42.39. Executing TECHMAP pass (map to technology primitives).

23.42.39.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

23.42.39.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~251 debug messages>

23.42.40. Executing OPT pass (performing simple optimizations).

23.42.40.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

23.42.40.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

23.42.40.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

23.42.40.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.42.40.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.42.40.6. Executing OPT_DFF pass (perform DFF optimizations).

23.42.40.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

23.42.40.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.42.40.9. Rerunning OPT passes. (Maybe there is more to do..)

23.42.40.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

23.42.40.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.42.40.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.42.40.13. Executing OPT_DFF pass (perform DFF optimizations).

23.42.40.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.42.40.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.42.40.16. Finished OPT passes. (There is nothing left to do.)

23.42.41. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

23.42.42. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 3987 cells with 23913 new cells, skipped 3326 cells.
  replaced 3 cell types:
    1332 $_OR_
      94 $_XOR_
    2561 $_MUX_
  not replaced 59 cell types:
      30 $scopeinfo
     360 $_NOT_
    1255 $_AND_
       6 $_TBUF_
       1 $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4
       1 $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4
       1 $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4
       1 $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4
     702 TRELLIS_FF
       1 $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4
       1 $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4
       1 $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4
       1 $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4
       1 $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4
       1 $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4
       1 $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4
       1 $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4
       1 $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4
       1 $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4
       1 $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4
       1 $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp
     252 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
       1 $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4
       1 $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER
       1 $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp
      16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4
       1 $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4
       1 $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4
      16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4
       1 $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4
       1 $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4
       1 $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4
       1 $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4
       1 $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4
       1 $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp
     252 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp
     388 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C

23.42.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

23.42.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

23.42.42.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 10552 AND gates and 30405 wires from module `top' to a netlist network with 1887 inputs and 733 outputs.

23.42.42.4. Executing ABC9_EXE pass (technology mapping using ABC9).

23.42.42.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   1887/    733  and =    9143  lev =   46 (5.17)  mem = 0.27 MB  box = 680  bb = 292
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   1887/    733  and =   12047  lev =   62 (3.19)  mem = 0.29 MB  ch = 1378  box = 618  bb = 292
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   60. Obj =  140. Set =  636. CutMin = no
ABC: Node =   12047.  Ch =  1245.  Total mem =    3.29 MB. Peak cut mem =    0.27 MB.
ABC: P:  Del = 6898.00.  Ar =   11580.0.  Edge =    14094.  Cut =   176076.  T =     0.04 sec
ABC: P:  Del = 6884.00.  Ar =   12458.0.  Edge =    14903.  Cut =   173815.  T =     0.04 sec
ABC: P:  Del = 6884.00.  Ar =    6955.0.  Edge =    12560.  Cut =   357389.  T =     0.08 sec
ABC: F:  Del = 6884.00.  Ar =    4390.0.  Edge =    11074.  Cut =   322047.  T =     0.08 sec
ABC: A:  Del = 6884.00.  Ar =    3944.0.  Edge =     9900.  Cut =   280360.  T =     0.11 sec
ABC: A:  Del = 6884.00.  Ar =    3897.0.  Edge =     9817.  Cut =   286148.  T =     0.11 sec
ABC: Total time =     0.46 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   1887/    733  and =    8447  lev =   39 (3.38)  mem = 0.25 MB  box = 618  bb = 292
ABC: Mapping (K=7)  :  lut =   2516  edge =    9758  lev =   14 (1.43)  levB =   42  mem = 0.13 MB
ABC: LUT = 2516 : 2=265 10.5 %  3=624 24.8 %  4=1074 42.7 %  5=364 14.5 %  6=83 3.3 %  7=106 4.2 %  Ave = 3.88
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 4.90 seconds, total: 4.90 seconds

23.42.42.6. Executing AIGER frontend.
<suppressed ~5314 debug messages>
Removed 11643 unused cells and 23129 unused wires.

23.42.42.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     2541
ABC RESULTS:   $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells:       16
ABC RESULTS:   $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:      252
ABC RESULTS:   $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      326
ABC RESULTS:           input signals:      337
ABC RESULTS:          output signals:      131
Removing temp directory.

23.42.43. Executing TECHMAP pass (map to technology primitives).

23.42.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

23.42.43.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4 for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4 for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4 for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4 for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4 for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4 for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4 for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4 for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4 for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4 for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4 for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4 for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4 for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4 for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4 for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4 for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4 for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4 for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4 for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4 for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4 for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4 for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4 for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4 for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001000 for cells of type $__ABC9_SCC_BREAKER.
No more expansions possible.
<suppressed ~980 debug messages>
Removed 322 unused cells and 36632 unused wires.

23.43. Executing TECHMAP pass (map to technology primitives).

23.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

23.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$d2d50fced6e06d123321409eee0a12cd3b79fb8c\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut.
Using template $paramod$7a9b7d7d96d5349b2a3f800b325795fd17e50692\$lut for cells of type $lut.
Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$633ae299df262467973f925d88826d85d4a12fb4\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut.
Using template $paramod$052ca015f1400ebf950f85d5f181f7a5865c336c\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut.
Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut.
Using template $paramod$b97ff285770a798ba31d840db2ce52fdc36910ae\$lut for cells of type $lut.
Using template $paramod$a8f200f2806e23893fd75a1574871ecd897f762e\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$b18a3edb490ff3a49fefc94182a05f36efbdbba2\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut.
Using template $paramod$de8f8bba29d56316e95e77d4f2a0bc9ef73137bb\$lut for cells of type $lut.
Using template $paramod$5c3294d2efb88caf0474e72690e5c12ab871a3e8\$lut for cells of type $lut.
Using template $paramod$73168779d124d0e86f3f4da4f351086f6646bb40\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut.
Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut.
Using template $paramod$ce44877a8aba311086973ef3ef648b154684306e\$lut for cells of type $lut.
Using template $paramod$f28a4401e00366386f5c9da01093cb438d2ef37a\$lut for cells of type $lut.
Using template $paramod$173257c402a3003de28bff8c2a49d358e5f4004c\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut.
Using template $paramod$5400b6807adef39a9693b2fbff17f8c0ab116b66\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$23ba03b3f106a8b0f20f18bfebd862b419996ddc\$lut for cells of type $lut.
Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut.
Using template $paramod$c20bb0ec9b7ffe048b440bc5b52865dca055e17d\$lut for cells of type $lut.
Using template $paramod$394086530b97e2ede4325cfef07483589916f736\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$9c6e6a10ea00e5b0682f6243b802d7839a398197\$lut for cells of type $lut.
Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut.
Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$4e45a60feb8bbe3cabd280417c9ffbefad6f6ef3\$lut for cells of type $lut.
Using template $paramod$d54d0e440c49fc9214ad93b5a7a39944cc09a889\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod$38400b76de2b00d7d5f8f09de118b82fd1b8be0a\$lut for cells of type $lut.
Using template $paramod$08466811901d5e03ed77c75ae1ee4f324a7c22b7\$lut for cells of type $lut.
Using template $paramod$35e780f9333f3666b86f6bdeb5e6c5f65477f87e\$lut for cells of type $lut.
Using template $paramod$48f2db66c872c1f64faeb797c1719c912a15a86f\$lut for cells of type $lut.
Using template $paramod$c19ac226b2328a9dc00b76bc0a6d1e025c6f4fca\$lut for cells of type $lut.
Using template $paramod$1df6d41de86e48fa0e114cfe35ac61195abc3952\$lut for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut.
Using template $paramod$bed770a996b91d26bd8ec11fab40ed5b998c6937\$lut for cells of type $lut.
Using template $paramod$b2b8f14c1dc45737f0261c4484079d734f30d41f\$lut for cells of type $lut.
Using template $paramod$05402c79be82cc63a2eaed19f98c2af9df54d241\$lut for cells of type $lut.
Using template $paramod$d7a87ca2ecbda1d431eb014d7af4b3bc1067b28d\$lut for cells of type $lut.
Using template $paramod$b2b362fa866354d5936edc937d825ffc48772447\$lut for cells of type $lut.
Using template $paramod$3cc80e2a63856e1f46075e358d1c072c35cc4ca8\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$ee3ba3939f6ccdb74bf420a252d58cdb86511937\$lut for cells of type $lut.
Using template $paramod$473fcd371d91799964bc73c98ad44aa026e26f19\$lut for cells of type $lut.
Using template $paramod$db8547c0ce3f404162c765a55df5db805b4e10bc\$lut for cells of type $lut.
Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6\$lut for cells of type $lut.
Using template $paramod$2e6f7636c4430e71acfafacf89034290c19a68d2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut.
Using template $paramod$b8113752b08bd47f69a1c8c2bca1cfb157e800c9\$lut for cells of type $lut.
Using template $paramod$9b5adbcc1983522e183f7d22bb4ef0787febf9d7\$lut for cells of type $lut.
Using template $paramod$a05170b3f2d3fcb0bf88d37e810984e864962880\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$8cb91cbdb27a134cadb0a6f504fee8b3a31c5a5c\$lut for cells of type $lut.
Using template $paramod$b687dc07959af1fa40c448af298b5a8ef545da15\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut.
Using template $paramod$f672f1e5ea7eaf40630014635549af40fc023a51\$lut for cells of type $lut.
Using template $paramod$eb8f2bc04935cf1688579aec50dd83b80f48ac67\$lut for cells of type $lut.
Using template $paramod$47a326ee296feaca60c97add5a2f7670de259bd9\$lut for cells of type $lut.
Using template $paramod$4db3f0d067a6794efd5979ea33ffc0ce06e2e75c\$lut for cells of type $lut.
Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$6fc23ce09f2013cb9de2228dbcdda21841008f92\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$3416dacc8eaab1f89b3d6b7398df3da766d29ef2\$lut for cells of type $lut.
Using template $paramod$5afdc7428159757eedf89ce514f7efa32b31c8e7\$lut for cells of type $lut.
Using template $paramod$51307cdec77060d17363ea3d60427c9afef1ddc2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut.
Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$89ca3723ebb4dfdb3c4024f3f04b784a3e88f188\$lut for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$be95f3a2132281eadd1adcfe6229e43dbc3353c9\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$d68ac1ca8168da167c4a0636e5d58dad0d518580\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$cedf4e85fa7d99c3f6bd280e7df7624d55412661\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$723be7177967d6866729df0ff463a602326a012e\$lut for cells of type $lut.
Using template $paramod$3ee26675fdb86c62f9449255b242f36533c51cab\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$70a934594406e8042bf2854c778fef542ef3ea5f\$lut for cells of type $lut.
Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$2cfa4f9230599d40df4d62f018533659bb2a6afc\$lut for cells of type $lut.
Using template $paramod$90418f71a1b3e98f36d147df874dd839b0e31579\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$26d876869d6ab003366d0470e095daef2ccfcbd7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$4b7a2575a604aa21eec6378b6833292a7c6978f8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut.
Using template $paramod$bbd5b4ecadbcba9cd650db194969a7dcc71fef11\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$f109125ffdede8321ac65719b1066c75ff1eaef0\$lut for cells of type $lut.
Using template $paramod$a29dc9226a883358910d3758606f48686bda2689\$lut for cells of type $lut.
Using template $paramod$050221686252202c3dcb014324b7b753c760a3f5\$lut for cells of type $lut.
Using template $paramod$e9d317c55f397705fc52599574a03ca7c6820239\$lut for cells of type $lut.
Using template $paramod$ec77ef2f39e0c5347eaada9711f26fca6a276050\$lut for cells of type $lut.
Using template $paramod$87e6e9473ffb0bf8a44e05d4dfdfaa6b36c50fee\$lut for cells of type $lut.
Using template $paramod$e0a16b39d62021fbd2d1c105eda1b9c3b86f8b30\$lut for cells of type $lut.
Using template $paramod$acf008c194939dd533849530b1ab63c5c671b3d9\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$df3b65132f7020afafd5e2001ca04b29f12adcb4\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod$7bd4b706939e5093319bef1818c333b8e6cc608d\$lut for cells of type $lut.
Using template $paramod$30ccc2d02d561628bd3e8ba21431cf11015685a5\$lut for cells of type $lut.
Using template $paramod$a48d96b3084901aac1f541d9be59ab6aad37df36\$lut for cells of type $lut.
Using template $paramod$7a73f9756d5c153bcd3667a54c2eeb22386fe779\$lut for cells of type $lut.
Using template $paramod$ca251f67c134fb1f7331fe7a90a5e58854a141ab\$lut for cells of type $lut.
Using template $paramod$21a1ca6f9f5c15b304c8c46ce6cda8b91e063cf1\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$6e3a03c79073e44642e8ed2dab4ee82dfd40dfba\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$9beb44c871dc113256524d05c106f4bc7c649829\$lut for cells of type $lut.
Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut.
Using template $paramod$efd9db50f639c84b61057002b4119366b96c7abc\$lut for cells of type $lut.
Using template $paramod$57cf7fbf84518d9e7604ec42b59ba9511e1f3caf\$lut for cells of type $lut.
Using template $paramod$06425c2b6ffe99b55d5890d2889b3236602f0684\$lut for cells of type $lut.
Using template $paramod$682dcf7a44e09cdf417bc55247ac658426f4c8e6\$lut for cells of type $lut.
Using template $paramod$9a6965d4f53d69e345bd8d48283856520a30225e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut.
Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut.
Using template $paramod$e50929688d8319f8cd7bdd627065cd59d2e91fe4\$lut for cells of type $lut.
Using template $paramod$34e326867bb04eb7166eb385de03f3f07fdc4c23\$lut for cells of type $lut.
Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut.
Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut.
Using template $paramod$18b66a2dc66be2a0d172c3d50ba03932f5924e22\$lut for cells of type $lut.
Using template $paramod$a81cf453a316218febe7a33c0cf3157f69dfa7dc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$5c76169916ad2852767adcbddee054887cf9226f\$lut for cells of type $lut.
Using template $paramod$c6a0421f5b5114b68e9782f0585d571421cf8f01\$lut for cells of type $lut.
Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut.
Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut.
Using template $paramod$b4f1ff03306381fb789e7dc9f7ae1800352ea61b\$lut for cells of type $lut.
Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110101 for cells of type $lut.
Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut.
Using template $paramod$c5e227af307b9c53329a9bcea914f98030ca9bc6\$lut for cells of type $lut.
Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut.
Using template $paramod$d7ff9632f3f772df7b9e3f4f831545c90be781f2\$lut for cells of type $lut.
Using template $paramod$60b99ddfae8ffcebbb1fe7f9e676a60f7472edd5\$lut for cells of type $lut.
Using template $paramod$d08ae3e2fee668f1a68bd32fd012d46d229cb782\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$f8b5a2092e0c5e20cb9d3c609617b439b0653eaf\$lut for cells of type $lut.
Using template $paramod$7ff054bf1849e35157c5493ac1b0fb5805fe014a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$39825c5ed3d135e502be79829033166f1762d78b\$lut for cells of type $lut.
Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut.
Using template $paramod$94cc9dc7ba20eb6ef27973e1d776ca04cbc15deb\$lut for cells of type $lut.
Using template $paramod$dea4eab506a4d838639e9279ae49ed014dea336b\$lut for cells of type $lut.
Using template $paramod$a2f141f8bc225b017c3d20a6a6829e76a46c8ea4\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut.
Using template $paramod$c581f6382c881129fac55eec32fe31b4c289a2e5\$lut for cells of type $lut.
Using template $paramod$f481c9367ffbae70fef7d0e4e363727ecca829aa\$lut for cells of type $lut.
Using template $paramod$fd2471a9c36b8c467f4768e647c392abe481a536\$lut for cells of type $lut.
Using template $paramod$1144da1bb095789dfe940dea3c7abeb9e625715c\$lut for cells of type $lut.
Using template $paramod$bd57e9718a938c253993cb582d13218a9bcdcc54\$lut for cells of type $lut.
Using template $paramod$d575d3554e876f643193272ee6813447059f103f\$lut for cells of type $lut.
Using template $paramod$8bed57bd1ff6d4db69d51a3254e9f8d0251c7445\$lut for cells of type $lut.
Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut.
Using template $paramod$207c2001fd1e6bfcc3600a2acf24d4fca014d82c\$lut for cells of type $lut.
Using template $paramod$3751cff910103888107374559f35d9f1f2f94946\$lut for cells of type $lut.
Using template $paramod$f9d6cf7b82717ecd056d1083bbabf4567325a5dd\$lut for cells of type $lut.
Using template $paramod$15ac410ea5b84c303864da98179081473b96983a\$lut for cells of type $lut.
Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut.
Using template $paramod$c08a774c89ef1ea6ee2ef4d8c3b071eb141d4259\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$f25cfeb07793f4c9b87758158af8df76472138cf\$lut for cells of type $lut.
Using template $paramod$3dc8df1b07971bda7726ddf94f6377e60804ab64\$lut for cells of type $lut.
Using template $paramod$40d69998ba7a81b693891a12ccf41c6e6085fe2f\$lut for cells of type $lut.
Using template $paramod$1ca1065a81438079a436702d0392678eec5bbc1c\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$d63701c28b42c937689bb584703a3d682631db04\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$286ed3273cbe066b6afe10d043ec3b66405aa78e\$lut for cells of type $lut.
Using template $paramod$6d64ca8087b2277f29d14a24ca6148e7bee3bdb7\$lut for cells of type $lut.
Using template $paramod$793fc28cf61120083daef76d0ad6adfe307204e0\$lut for cells of type $lut.
Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut.
Using template $paramod$cf3708160c4adac67b373267f481e84efabd43e9\$lut for cells of type $lut.
Using template $paramod$8f87fd1c60e0e6eacbe12f91c6c6a82b9299ed94\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$a9ba23df824f693c44e722629fd8c1fae157385c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut.
Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut.
Using template $paramod$00da6ee835349555028231ae835c9b401a5c1dee\$lut for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$97c37e63ac405dfc21dce5dbdf299a88a7671fdc\$lut for cells of type $lut.
Using template $paramod$9e1755e3954600257bb9b9ab192e2c0243b0f35a\$lut for cells of type $lut.
Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$f34232779a0569d5ac41d2d692536961128467b0\$lut for cells of type $lut.
Using template $paramod$d1239dea58a04f3eb43994cd44236e98b306ac2c\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut.
Using template $paramod$879e9a0dab05f8e280ee5baa386b77b06bc569e2\$lut for cells of type $lut.
Using template $paramod$d8c15619e14e23259772acc1552b8b29afbd81c5\$lut for cells of type $lut.
Using template $paramod$022f25e351f4370d3db4af915ee589ef82048c31\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut.
Using template $paramod$38ddb5cd59e13482af3017fd3f8559df8cf1d4b7\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$4cdcdf18abd83cce71e47573cd39a082eb3b2c66\$lut for cells of type $lut.
Using template $paramod$973394a6f8c13a435c2fa950b3fc699e041032a1\$lut for cells of type $lut.
Using template $paramod$d2f36c73302c08bbdc72fbc9881a616e0b9b0bb5\$lut for cells of type $lut.
Using template $paramod$6109b56fd0d3cc77be6b58eebcaf51991ca468c6\$lut for cells of type $lut.
Using template $paramod$5b5755730b9a53f6c50cca29ba2f99d7e0bc0fe6\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$7d174b298fa6e4dca03e5769428f20c9f0715d7b\$lut for cells of type $lut.
Using template $paramod$7dff6c14a102b6aad05ad3f9762bd5a7a578476f\$lut for cells of type $lut.
Using template $paramod$0a85ef24bbe0af4c0a398eda4c9c483e3a950ffc\$lut for cells of type $lut.
Using template $paramod$f8af7a783767baccc79938dbe6fbfb54437f700b\$lut for cells of type $lut.
Using template $paramod$31f64b4b2cb5d8113d9a1455af902b3edbe63394\$lut for cells of type $lut.
Using template $paramod$6069048ea7c45159713a0558424cdfb243a46dfe\$lut for cells of type $lut.
Using template $paramod$e6062a78edaf68ec0dbea59d4c8352dcb2ce0366\$lut for cells of type $lut.
Using template $paramod$81f38dbe34c0131668a5f4192c3c2c07e8338073\$lut for cells of type $lut.
Using template $paramod$bf00427ade60df6ecbee879d4a17f97643fe237b\$lut for cells of type $lut.
Using template $paramod$ee04a7397c7e60ad1a187fa314ed449c24407f97\$lut for cells of type $lut.
Using template $paramod$0be9a3a6d335d09edc9d1d9b6dee1df2c9bbf7ba\$lut for cells of type $lut.
Using template $paramod$7c085cdbf0919cd3ad402d9495d97f0d71e4db93\$lut for cells of type $lut.
Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut.
Using template $paramod$3f8ab0c6399ace446e81cbf7429a92d3905b752a\$lut for cells of type $lut.
Using template $paramod$c523ec4a0d5c6240004e942cc7592145bf160b31\$lut for cells of type $lut.
Using template $paramod$f4d1fc532e5ae7ff2ff042c88092a38a9c740b87\$lut for cells of type $lut.
Using template $paramod$fbd55d1b12935a22902cde46a0a7b6e309d6aa42\$lut for cells of type $lut.
Using template $paramod$77ae9444eaefc79a2bbeeba6c400946d1071bbf4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod$584e4a38268562e2142ef24a574198cdf8d42be8\$lut for cells of type $lut.
Using template $paramod$0372831f518ad10f4f37af80614ae8119229029c\$lut for cells of type $lut.
Using template $paramod$746e6bafd4fb1228a1f09f860e2141d0172b6dc4\$lut for cells of type $lut.
Using template $paramod$20f3f4b8e32f8a8b038b0056872dc94926194798\$lut for cells of type $lut.
Using template $paramod$3a313ff02d51d1203c8a57fd50d2cde2804e4da1\$lut for cells of type $lut.
Using template $paramod$6ff81f730f8b59d892f57895d61776245fbfaaec\$lut for cells of type $lut.
Using template $paramod$d491a266f9662a297987d35d4b16957a59e4712a\$lut for cells of type $lut.
Using template $paramod$4e1dc72d6980b77724f22d4f16d0e27813749ffa\$lut for cells of type $lut.
Using template $paramod$a7f1f4ee61dc2b9dc3aa578186b5cbb3eaddedc3\$lut for cells of type $lut.
Using template $paramod$8c11a155773d2e4aba9b1022fc059160b55313e8\$lut for cells of type $lut.
Using template $paramod$e2d4399e1e149b2bd3c04b32fc0d847bb8cdd6d6\$lut for cells of type $lut.
Using template $paramod$b9faa5a9398e4218347b9a72d784f8727e636b07\$lut for cells of type $lut.
Using template $paramod$d221c4378f7c6f149440ea5d85a23b3902af623b\$lut for cells of type $lut.
Using template $paramod$6157bfed25b82cd5445ec052da77ff3f5845cd73\$lut for cells of type $lut.
Using template $paramod$72148f3545efac6f48701d6c21ae5eeb7a5f865b\$lut for cells of type $lut.
Using template $paramod$40f50322426372d948aaadc2f14dc77fbf5a9200\$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod$d0e42eec83ea592bf45e9ec906447f1ed04bd355\$lut for cells of type $lut.
Using template $paramod$d9922e15eb5da1acc26e937540cc16b16c2ad42c\$lut for cells of type $lut.
Using template $paramod$8075729953f49b6cb1b4d863b2fb20da9818d304\$lut for cells of type $lut.
Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut.
Using template $paramod$ec6bb3db7c80c492ce6110718f99328a4ab7f019\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$c9355c14671e8569b2b55b2828d4fd95591ab987\$lut for cells of type $lut.
Using template $paramod$7ce7683c590e6b9a2ebd543a8f468551f1af24cf\$lut for cells of type $lut.
Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut.
Using template $paramod$05f66240810e81b1a2e698a1f280f5252768dc46\$lut for cells of type $lut.
Using template $paramod$50d0ed5c234a7335fb0b9558be3cce3681aa07a6\$lut for cells of type $lut.
Using template $paramod$7f1ac77c5d84ef62fa0ac317f9798af74d02a33d\$lut for cells of type $lut.
Using template $paramod$023d9d13c9ddd8e6cbda8fa49753038bbbacbfa4\$lut for cells of type $lut.
Using template $paramod$ddce54e04aa2e21dc36c3f216625e49798f2ceb0\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$cba7d4f63aea5e4b3faf052f9f9805e0c6d202cb\$lut for cells of type $lut.
Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut.
Using template $paramod$6d23198eb2b8f79a41c7626605a61009695893b1\$lut for cells of type $lut.
Using template $paramod$54af1cf84b203d109372f5e5f555e8e4316843f8\$lut for cells of type $lut.
Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da\$lut for cells of type $lut.
Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut.
Using template $paramod$8d8a6111e2a82db0bfbd78666fa69c753d8df004\$lut for cells of type $lut.
Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut.
Using template $paramod$ebc2bffeb14d72cac79dd0d6e85ade2c5c402e42\$lut for cells of type $lut.
Using template $paramod$aaf2ef5cf75121bbc717334d538c8a2de3e26e03\$lut for cells of type $lut.
Using template $paramod$b550af252509990ee3afc0caaa2538b6a7cde382\$lut for cells of type $lut.
Using template $paramod$ea9f0804ffa1047d479d3e00429394419ff5856b\$lut for cells of type $lut.
Using template $paramod$4f6ef5838c139220e91b3d9534b74e9d61193cac\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$b574c1df31b19134bcccccd0450f90abe2dd8f26\$lut for cells of type $lut.
Using template $paramod$39fecdaa624309b39c1f847c4e14205177fabf73\$lut for cells of type $lut.
Using template $paramod$263b613d26e59958a0d1e36903a2016b82f2f359\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut.
Using template $paramod$505ca6f83efadae0442899a08af73f5288142a52\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut.
Using template $paramod$75020cdf7715bd4a5f7067d80cafc74eabba6a01\$lut for cells of type $lut.
Using template $paramod$1e414bc4ae1aa2b560feb671e36085e722850812\$lut for cells of type $lut.
Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$717dae7a4b4d98fb824634d546043d165e3cf20a\$lut for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Using template $paramod$95f9b81027e0efcb4250de73f2fadc287f9fe7c2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$5d91ae8bf13f169f64fe2e993cae12295d19d8d3\$lut for cells of type $lut.
Using template $paramod$de5328836923c44c99600bcab852423201246f91\$lut for cells of type $lut.
Using template $paramod$71b6d833a4170eede1dcc8409c3fc7460c2df8d9\$lut for cells of type $lut.
Using template $paramod$d657361b360a152b4018b0283df55e5626273e96\$lut for cells of type $lut.
Using template $paramod$f00c0376cdf8518a9288594305173c177a0a27e2\$lut for cells of type $lut.
Using template $paramod$95e069858cb2e42f0b23620675213cfe73b02fff\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$53f13458d230ab667f8d3f784da9668ec43fe210\$lut for cells of type $lut.
Using template $paramod$561d2773f8d56e396c30ee941900c9935428585f\$lut for cells of type $lut.
Using template $paramod$0e6f7067c2a44b2e3cbef1e1c87513a6042c22b4\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~7528 debug messages>

23.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$8645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$8137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$8132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$8091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$8086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$7277.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$6741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6725.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6603.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$5378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$5378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$5378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$5378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$5378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$5119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5744.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$5661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$5661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$5661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$5628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6893.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$7167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$5707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$5843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$7212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$5791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$4774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$4769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$4112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$4169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$4169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$4132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$10009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$10028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$10489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$10892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$10954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$11735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$11761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$11941.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$12008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$12023.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$12045.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$12052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$12063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$12070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$4119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$4132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$4174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4733.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4747.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$4922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$5386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$5539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$5661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$5822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5861.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$5990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$6002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$4997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6412.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$5843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6733.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6793.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$6925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$6988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$7019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7073.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$5668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7249.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$7277.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$7284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7441.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7484.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$auto$fsm_map.cc:170:map_fsm$2236[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$7836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$8148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$8178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8365.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$8491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$8500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$8650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8793.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8901.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8929.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$8990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$9141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut$aiger72892$9246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$9253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$9289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$9509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$9528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$9533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$9610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut$aiger72892$9685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$auto$fsm_map.cc:170:map_fsm$2236[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$auto$fsm_map.cc:170:map_fsm$2236[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$auto$rtlil.cc:2582:Mux$2727[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$7756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$auto$rtlil.cc:2582:Mux$2727[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$auto$rtlil.cc:2582:Mux$2727[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$auto$rtlil.cc:2582:Mux$2727[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$auto$rtlil.cc:2582:Mux$2727[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut$auto$opt_dff.cc:219:make_patterns_logic$2425.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut$aiger72892$11096.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72987.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$72893$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73001.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$6179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$72893$lut$aiger72892$4774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Removed 0 unused cells and 6972 unused wires.

23.45. Executing AUTONAME pass.
Renamed 249328 objects in module top (310 iterations).
<suppressed ~11253 debug messages>

23.46. Executing HIERARCHY pass (managing design hierarchy).

23.46.1. Analyzing design hierarchy..
Top module:  \top

23.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

23.47. Printing statistics.

=== top ===

   Number of wires:               5183
   Number of wire bits:          13040
   Number of public wires:        5183
   Number of public wire bits:   13040
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               6608
     $_TBUF_                         6
     $scopeinfo                     30
     CCU2C                         326
     L6MUX21                       401
     LUT4                         3897
     PFUMX                         954
     TRELLIS_DPR16X4               292
     TRELLIS_FF                    702

23.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

23.49. Executing JSON backend.

Warnings: 213 unique messages, 214 total
End of script. Logfile hash: f7b41bed1a, CPU: user 7.18s system 0.10s, MEM: 203.04 MB peak
Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
Time spent: 40% 1x abc9_exe (4 sec), 11% 11x techmap (1 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:      6301/43848    14%
Info:         logic LUTs:   3897/43848     8%
Info:         carry LUTs:    652/43848     1%
Info:           RAM LUTs:   1168/ 5481    21%
Info:          RAMW LUTs:    584/10962     5%

Info:      Total DFFs:       702/43848     1%

Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     337 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xfcc848fa

Info: Device utilisation:
Info: 	          TRELLIS_IO:    18/  245     7%
Info: 	                DCCA:     1/   56     1%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:   702/43848     1%
Info: 	        TRELLIS_COMB:  6393/43848    14%
Info: 	        TRELLIS_RAMW:   292/ 5481     5%

Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 3228 cells, random placement wirelen = 294372.
Info:     at initial placer iter 0, wirelen = 2537
Info:     at initial placer iter 1, wirelen = 2695
Info:     at initial placer iter 2, wirelen = 3074
Info:     at initial placer iter 3, wirelen = 3058
Info: Running main analytical placer, max placement attempts per cell = 6856104.
Info:     at iteration #1, type ALL: wirelen solved = 3128, spread = 46238, legal = 46766; time = 0.16s
Info:     at iteration #2, type ALL: wirelen solved = 4363, spread = 40591, legal = 41247; time = 0.16s
Info:     at iteration #3, type ALL: wirelen solved = 5562, spread = 39643, legal = 40212; time = 0.16s
Info:     at iteration #4, type ALL: wirelen solved = 7274, spread = 36621, legal = 37365; time = 0.15s
Info:     at iteration #5, type ALL: wirelen solved = 8286, spread = 36326, legal = 36950; time = 0.15s
Info:     at iteration #6, type ALL: wirelen solved = 9803, spread = 32735, legal = 33487; time = 0.15s
Info:     at iteration #7, type ALL: wirelen solved = 10960, spread = 31875, legal = 32374; time = 0.15s
Info:     at iteration #8, type ALL: wirelen solved = 12388, spread = 30616, legal = 31571; time = 0.15s
Info:     at iteration #9, type ALL: wirelen solved = 12760, spread = 29478, legal = 30091; time = 0.14s
Info:     at iteration #10, type ALL: wirelen solved = 14057, spread = 29838, legal = 30388; time = 0.14s
Info:     at iteration #11, type ALL: wirelen solved = 15080, spread = 30421, legal = 31077; time = 0.14s
Info:     at iteration #12, type ALL: wirelen solved = 15616, spread = 30766, legal = 31213; time = 0.14s
Info:     at iteration #13, type ALL: wirelen solved = 16562, spread = 28285, legal = 29095; time = 0.14s
Info:     at iteration #14, type ALL: wirelen solved = 16205, spread = 29443, legal = 30201; time = 0.14s
Info:     at iteration #15, type ALL: wirelen solved = 17628, spread = 27696, legal = 28614; time = 0.14s
Info:     at iteration #16, type ALL: wirelen solved = 17065, spread = 27256, legal = 28294; time = 0.14s
Info:     at iteration #17, type ALL: wirelen solved = 17504, spread = 27398, legal = 28066; time = 0.14s
Info:     at iteration #18, type ALL: wirelen solved = 18075, spread = 27488, legal = 28172; time = 0.14s
Info:     at iteration #19, type ALL: wirelen solved = 18155, spread = 27155, legal = 28002; time = 0.14s
Info:     at iteration #20, type ALL: wirelen solved = 18519, spread = 29888, legal = 30390; time = 0.14s
Info:     at iteration #21, type ALL: wirelen solved = 20479, spread = 29359, legal = 29816; time = 0.14s
Info:     at iteration #22, type ALL: wirelen solved = 20677, spread = 29162, legal = 29822; time = 0.14s
Info:     at iteration #23, type ALL: wirelen solved = 20566, spread = 29301, legal = 29931; time = 0.14s
Info:     at iteration #24, type ALL: wirelen solved = 21003, spread = 29409, legal = 30025; time = 0.14s
Info: HeAP Placer Time: 5.48s
Info:   of which solving equations: 3.15s
Info:   of which spreading cells: 0.47s
Info:   of which strict legalisation: 0.15s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 4333, wirelen = 28002
Info:   at iteration #5: temp = 0.000000, timing cost = 4730, wirelen = 24594
Info:   at iteration #10: temp = 0.000000, timing cost = 4885, wirelen = 23720
Info:   at iteration #15: temp = 0.000000, timing cost = 4492, wirelen = 23389
Info:   at iteration #20: temp = 0.000000, timing cost = 4630, wirelen = 23295
Info:   at iteration #25: temp = 0.000000, timing cost = 4828, wirelen = 23259
Info:   at iteration #25: temp = 0.000000, timing cost = 4819, wirelen = 23259 
Info: SA placement time 18.18s

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 37.46 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.71 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 10.52 ns

Info: Slack histogram:
Info:  legend: * represents 47 endpoint(s)
Info:          + represents [1,47) endpoint(s)
Info: [ 13304,  14601) |+
Info: [ 14601,  15898) |*+
Info: [ 15898,  17195) |***+
Info: [ 17195,  18492) |******+
Info: [ 18492,  19789) |***+
Info: [ 19789,  21086) |*+
Info: [ 21086,  22383) |*********+
Info: [ 22383,  23680) |************+
Info: [ 23680,  24977) |*********************************************+
Info: [ 24977,  26274) |************************************************************ 
Info: [ 26274,  27571) |******+
Info: [ 27571,  28868) |*********+
Info: [ 28868,  30165) |***+
Info: [ 30165,  31462) | 
Info: [ 31462,  32759) |+
Info: [ 32759,  34056) |*+
Info: [ 34056,  35353) |*********+
Info: [ 35353,  36650) |******+
Info: [ 36650,  37947) |*+
Info: [ 37947,  39244) |***+
Info: Checksum: 0xd54d74bd
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 28531 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      217        782 |  217   782 |     27859|       0.59       0.59|
Info:       2000 |      360       1639 |  143   857 |     27191|       0.28       0.87|
Info:       3000 |      443       2556 |   83   917 |     26812|       0.31       1.19|
Info:       4000 |      596       3403 |  153   847 |     26043|       0.25       1.43|
Info:       5000 |      757       4242 |  161   839 |     25365|       0.30       1.73|
Info:       6000 |      875       5124 |  118   882 |     24968|       0.26       1.99|
Info:       7000 |     1000       5999 |  125   875 |     24492|       0.27       2.26|
Info:       8000 |     1116       6883 |  116   884 |     23696|       0.25       2.52|
Info:       9000 |     1311       7688 |  195   805 |     23009|       0.27       2.79|
Info:      10000 |     1439       8560 |  128   872 |     22784|       0.25       3.04|
Info:      11000 |     1615       9384 |  176   824 |     22099|       0.22       3.26|
Info:      12000 |     1835      10164 |  220   780 |     21483|       0.24       3.51|
Info:      13000 |     2058      10941 |  223   777 |     20871|       0.27       3.78|
Info:      14000 |     2257      11742 |  199   801 |     20269|       0.26       4.04|
Info:      15000 |     2489      12510 |  232   768 |     19594|       0.29       4.33|
Info:      16000 |     2712      13287 |  223   777 |     19091|       0.25       4.59|
Info:      17000 |     2989      14010 |  277   723 |     18459|       0.29       4.88|
Info:      18000 |     3262      14737 |  273   727 |     17917|       0.31       5.19|
Info:      19000 |     3533      15466 |  271   729 |     17333|       0.27       5.46|
Info:      20000 |     3806      16193 |  273   727 |     16838|       0.31       5.77|
Info:      21000 |     4126      16873 |  320   680 |     16265|       0.30       6.07|
Info:      22000 |     4450      17549 |  324   676 |     16006|       0.32       6.39|
Info:      23000 |     4613      18386 |  163   837 |     15765|       0.28       6.67|
Info:      24000 |     4913      19086 |  300   700 |     15245|       0.31       6.98|
Info:      25000 |     5260      19739 |  347   653 |     14741|       0.31       7.30|
Info:      26000 |     5600      20399 |  340   660 |     14345|       0.32       7.62|
Info:      27000 |     5906      21093 |  306   694 |     13826|       0.30       7.92|
Info:      28000 |     6316      21683 |  410   590 |     13425|       0.33       8.24|
Info:      29000 |     6652      22347 |  336   664 |     13162|       0.34       8.59|
Info:      30000 |     7015      22984 |  363   637 |     12673|       0.30       8.89|
Info:      31000 |     7381      23618 |  366   634 |     12334|       0.29       9.18|
Info:      32000 |     7728      24271 |  347   653 |     12128|       0.42       9.60|
Info:      33000 |     8165      24834 |  437   563 |     11840|       0.31       9.91|
Info:      34000 |     8604      25395 |  439   561 |     11542|       0.39      10.30|
Info:      35000 |     9008      25991 |  404   596 |     11185|       0.38      10.68|
Info:      36000 |     9445      26554 |  437   563 |     10774|       0.33      11.01|
Info:      37000 |     9795      27182 |  350   628 |     10311|       0.34      11.35|
Info:      38000 |    10028      27776 |  233   594 |      9612|       0.20      11.55|
Info:      39000 |    10299      28344 |  271   568 |      8938|       0.24      11.79|
Info:      40000 |    10601      28882 |  302   538 |      8377|       0.24      12.03|
Info:      41000 |    10954      29453 |  353   571 |      7884|       0.24      12.28|
Info:      42000 |    11396      29960 |  442   507 |      7432|       0.28      12.55|
Info:      43000 |    11813      30499 |  417   539 |      6932|       0.27      12.83|
Info:      44000 |    12212      31055 |  399   556 |      6427|       0.26      13.09|
Info:      45000 |    12521      31660 |  309   605 |      5775|       0.26      13.35|
Info:      46000 |    12598      32556 |   77   896 |      4866|       0.11      13.46|
Info:      47000 |    12623      33511 |   25   955 |      3902|       0.09      13.55|
Info:      48000 |    12667      34458 |   44   947 |      2961|       0.10      13.64|
Info:      49000 |    12837      35280 |  170   822 |      2159|       0.19      13.83|
Info:      50000 |    13023      35993 |  186   713 |      1432|       0.25      14.09|
Info:      51000 |    13110      36810 |   87   817 |       538|       0.17      14.26|
Info:      51539 |    13112      37105 |    2   295 |         0|       0.09      14.35|
Info: Routing complete.
Info: Router1 time 14.35s
Info: Checksum: 0x9e1ca2c5

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_2.Q
Info:  1.1  1.7    Net SOC.Core.Control_Unit.nextstate_PFUMX_Z_2_C0[2] (16,26) -> (16,24)
Info:                Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.C
Info:                Defined in:
Info:                  Risco-5/src/core/control_unit.v:51.11-51.16
Info:  0.2  1.9  Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info:  1.5  3.4    Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (16,24) -> (17,37)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  3.7  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.F
Info:  2.4  6.1    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (17,37) -> (24,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.B
Info:  0.4  6.5  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.5    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (24,20) -> (24,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.5  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.5    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (24,20) -> (24,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.6  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.6    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (24,20) -> (24,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.6  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.6    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (24,20) -> (24,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.7  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.7    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (24,20) -> (24,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.7  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.7    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (24,20) -> (25,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.7  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.7    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (25,20) -> (25,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.7  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.7    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (25,20) -> (25,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.8  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.8    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (25,20) -> (25,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.8  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.8    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (25,20) -> (25,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.9  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.9    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (25,20) -> (25,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.9  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.9    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (25,20) -> (25,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.9  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.9    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (25,20) -> (25,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.9  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.9    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (25,20) -> (26,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.0  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.0    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (26,20) -> (26,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.0  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.0    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (26,20) -> (26,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.1  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.1    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (26,20) -> (26,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.1  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.1    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (26,20) -> (26,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.1  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.1    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (26,20) -> (26,20)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.1  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.1    Net $nextpnr_CCU2C_31$CIN (26,20) -> (26,20)
Info:                Sink $nextpnr_CCU2C_31$CCU2_COMB0.FCI
Info:  0.4  7.6  Source $nextpnr_CCU2C_31$CCU2_COMB0.F
Info:  2.0  9.6    Net SOC.Bus.slave_1_write_LUT4_Z_C[3] (26,20) -> (13,9)
Info:                Sink SOC.Memory.address_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  9.8  Source SOC.Memory.address_LUT4_Z.F
Info:  1.8 11.6    Net SOC.slave_address[5] (13,9) -> (9,3)
Info:                Sink SOC.Memory.memory.0.33$DPRAM_COMB1.A
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:22.5-22.18
Info:  0.2 11.8  Source SOC.Memory.memory.0.33$DPRAM_COMB1.F
Info:  0.9 12.7    Net SOC.Memory.memory.0.33_DO_2[3] (9,3) -> (7,3)
Info:                Sink SOC.Memory.memory.0.33_DO_2_LUT4_C.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 12.9  Source SOC.Memory.memory.0.33_DO_2_LUT4_C.F
Info:  0.6 13.6    Net SOC.Memory.memory.0.41_DO_2_LUT4_C_Z[0] (7,3) -> (7,3)
Info:                Sink SOC.Memory.memory.0.97_DO_2_LUT4_C_Z_LUT4_Z.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 13.8  Source SOC.Memory.memory.0.97_DO_2_LUT4_C_Z_LUT4_Z.F
Info:  0.6 14.4    Net SOC.Memory.memory.0.97_DO_2_LUT4_C_Z[3] (7,3) -> (8,4)
Info:                Sink SOC.Memory.memory.0.233_DO_2_LUT4_C_Z_LUT4_Z_1.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 14.7  Source SOC.Memory.memory.0.233_DO_2_LUT4_C_Z_LUT4_Z_1.F
Info:  0.9 15.6    Net SOC.Memory.memory.0.233_DO_2_LUT4_C_Z[4] (8,4) -> (8,7)
Info:                Sink SOC.GPIOS.Gpios[5].direction_LUT4_B_D_LUT4_Z_B_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 15.9  Source SOC.GPIOS.Gpios[5].direction_LUT4_B_D_LUT4_Z_B_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  1.0 16.9    Net SOC.GPIOS.Gpios[5].direction_LUT4_B_D_LUT4_Z_B[3] (8,7) -> (5,8)
Info:                Sink SOC.GPIOS.Gpios[5].direction_LUT4_B_D_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 17.1  Source SOC.GPIOS.Gpios[5].direction_LUT4_B_D_LUT4_Z.F
Info:  1.5 18.6    Net SOC.GPIOS.Gpios[5].direction_LUT4_B_D[3] (5,8) -> (5,24)
Info:                Sink SOC.GPIOS.Gpios[5].direction_LUT4_B.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 18.8  Source SOC.GPIOS.Gpios[5].direction_LUT4_B.F
Info:  1.0 19.8    Net SOC.Core.read_data_LUT4_Z_21_C[3] (5,24) -> (11,26)
Info:                Sink SOC.Core.read_data_LUT4_Z_21.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 20.0  Source SOC.Core.read_data_LUT4_Z_21.F
Info:  0.4 20.5    Net SOC.read_data[5] (11,26) -> (11,26)
Info:                Sink SOC.Core.memory_register_TRELLIS_FF_Q_26.M
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:21.34-21.43
Info:  0.0 20.5  Setup SOC.Core.memory_register_TRELLIS_FF_Q_26.M
Info: 4.7 ns logic, 15.8 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source gpios[2]$tr_io.O
Info:  4.3  4.3    Net gpios[2]$TRELLIS_IO_IN (90,23) -> (14,24)
Info:                Sink SOC.GPIOS.Gpios[2].direction_LUT4_B.A
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:7.16-7.21
Info:  0.2  4.5  Source SOC.GPIOS.Gpios[2].direction_LUT4_B.F
Info:  0.5  5.0    Net SOC.Core.read_data_LUT4_Z_18_C[3] (14,24) -> (14,25)
Info:                Sink SOC.Core.read_data_LUT4_Z_18.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.2  Source SOC.Core.read_data_LUT4_Z_18.F
Info:  0.4  5.6    Net SOC.read_data[2] (14,25) -> (14,25)
Info:                Sink SOC.Core.memory_register_TRELLIS_FF_Q_29.M
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:21.34-21.43
Info:  0.0  5.6  Setup SOC.Core.memory_register_TRELLIS_FF_Q_29.M
Info: 0.5 ns logic, 5.1 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info:  3.6  4.1    Net SOC.GPIOS.gpio_direction[2] (6,24) -> (69,24)
Info:                Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info:                Defined in:
Info:                  Risco-5/src/peripheral/gpios.v:14.19-14.33
Info:  0.2  4.3  Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info:  1.3  5.6    Net gpios_$_TBUF__Y_3_E (69,24) -> (81,23)
Info:                Sink gpios[2]$tr_io$invert_T.A
Info:  0.2  5.8  Source gpios[2]$tr_io$invert_T.F
Info:  1.2  7.1    Net gpios[2]$tr_io$invert_T$conn$Z (81,23) -> (90,23)
Info:                Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 6.1 ns routing

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 48.89 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.62 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 7.06 ns

Info: Slack histogram:
Info:  legend: * represents 52 endpoint(s)
Info:          + represents [1,52) endpoint(s)
Info: [ 19547,  20523) |**+
Info: [ 20523,  21499) |*******+
Info: [ 21499,  22475) |***+
Info: [ 22475,  23451) |+
Info: [ 23451,  24427) |+
Info: [ 24427,  25403) |**+
Info: [ 25403,  26379) |************+
Info: [ 26379,  27355) |*********+
Info: [ 27355,  28331) |***********************************+
Info: [ 28331,  29307) |************************************************************ 
Info: [ 29307,  30283) |*+
Info: [ 30283,  31259) |**+
Info: [ 31259,  32235) |*********+
Info: [ 32235,  33211) |*+
Info: [ 33211,  34187) |*+
Info: [ 34187,  35163) |*+
Info: [ 35163,  36139) |****+
Info: [ 36139,  37115) |*******+
Info: [ 37115,  38091) |**+
Info: [ 38091,  39067) |**+

Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }

Loading: [======                                            ] 11.04%
Loading: [============                                      ] 22.08%
Loading: [=================                                 ] 33.12%
Loading: [=======================                           ] 44.15%
Loading: [============================                      ] 55.19%
Loading: [==================================                ] 66.23%
Loading: [=======================================           ] 77.27%
Loading: [=============================================     ] 88.31%
Loading: [==================================================] 99.35%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ echo testando na ecp5
testando na ecp5
[Pipeline] }
Lock released on resource [ecp5]
+ echo testando na tang nano
testando na tang nano
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS