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Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/lib/jenkins/workspace/Risco 5 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -Rf Risco-5/ build/ [Pipeline] sh + git clone https://github.com/JN513/Risco-5 Cloning into 'Risco-5'... [Pipeline] sh + cd Risco-5 [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (IVerilog) [Pipeline] sh + mkdir -p build [Pipeline] sh + cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v [Pipeline] sh + /eda/oss-cad-suite/bin/vvp build/soc_test.o ERROR: Risco-5/src/peripheral/memory.v:29: $readmemh: Unable to open software/memory/generic.hex for reading. VCD info: dumpfile build/soc.vcd opened for output. Risco-5/tests/soc_test.v:32: $finish called at 566 (1s) [Pipeline] sh + rm -f Risco-5/software/memory/generic.hex [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Síntese) [Pipeline] parallel [Pipeline] { (Branch: OSS-Cad-Suite) [Pipeline] { (Branch: Gowin) [Pipeline] stage [Pipeline] { (OSS-Cad-Suite) [Pipeline] stage [Pipeline] { (Gowin) [Pipeline] stage [Pipeline] { (Yosys) [Pipeline] sh [Pipeline] sh + rm -rf Risco-5/impl/pnr [Pipeline] sh + /eda/oss-cad-suite/bin/yosys -p read_verilog Risco-5/fpga/ecp5/main.v; read_verilog Risco-5/debug/clk_divider.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf <claire@yosyshq.com> | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) -- Running command ` read_verilog Risco-5/fpga/ecp5/main.v; read_verilog Risco-5/debug/clk_divider.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 ' -- 1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: Risco-5/debug/clk_divider.v Parsing Verilog input from `Risco-5/debug/clk_divider.v' to AST representation. Generating RTLIL representation for module `\ClkDivider'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: Risco-5/debug/reset.v Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation. Generating RTLIL representation for module `\Alu'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation. Generating RTLIL representation for module `\ALU_Control'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation. Generating RTLIL representation for module `\Control_Unit'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: Risco-5/src/core/core.v Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation. Generating RTLIL representation for module `\Core'. Risco-5/src/core/core.v:106: Warning: Identifier `\pc_source' is implicitly declared. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation. Generating RTLIL representation for module `\CSR_Unit'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation. Generating RTLIL representation for module `\Immediate_Generator'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation. Generating RTLIL representation for module `\MUX'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation. Generating RTLIL representation for module `\PC'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation. Generating RTLIL representation for module `\Registers'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation. Generating RTLIL representation for module `\BUS'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9) Generating RTLIL representation for module `\GPIO'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation. Generating RTLIL representation for module `\GPIOS'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation. Generating RTLIL representation for module `\LEDs'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation. Generating RTLIL representation for module `\Risco_5_SOC'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_rx'. Successfully finished Verilog frontend. 22. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_tx'. Successfully finished Verilog frontend. 23. Executing SYNTH_ECP5 pass. 23.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 23.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 23.3. Executing HIERARCHY pass (managing design hierarchy). 23.3.1. Finding top of design hierarchy.. root of 0 design levels: uart_tool_tx root of 0 design levels: uart_tool_rx root of 1 design levels: UART root of 2 design levels: Risco_5_SOC root of 0 design levels: Memory root of 0 design levels: LEDs root of 1 design levels: GPIOS root of 0 design levels: GPIO root of 0 design levels: FIFO root of 0 design levels: BUS root of 0 design levels: Registers root of 0 design levels: PC root of 0 design levels: MUX root of 0 design levels: Immediate_Generator root of 0 design levels: CSR_Unit root of 1 design levels: Core root of 0 design levels: Control_Unit root of 0 design levels: ALU_Control root of 0 design levels: Alu root of 0 design levels: ResetBootSystem root of 0 design levels: ClkDivider root of 3 design levels: top Automatically selected top as design top module. 23.3.2. Analyzing design hierarchy.. Top module: \top Used module: \Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: \ResetBootSystem Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \MEMORY_SIZE = 2048 Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 23.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \MEMORY_SIZE = 2048 Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 Generating RTLIL representation for module `$paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC'. Parameter \CYCLES = 20 23.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \WIDHT = 5 23.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 5 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 23.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 23.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \BOOT_ADDRESS = 0 23.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'. Parameter \BOOT_ADDRESS = 0 Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. Risco-5/src/core/core.v:106: Warning: Identifier `\pc_source' is implicitly declared. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 23.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 23.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 23.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 23.3.12. Analyzing design hierarchy.. Top module: \top Used module: $paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \WIDHT = 6 23.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 6 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Found cached RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'. Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000 Parameter \MEMORY_SIZE = 2048 23.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000 Parameter \MEMORY_SIZE = 2048 Generating RTLIL representation for module `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory'. Parameter \BOOT_ADDRESS = 0 Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. 23.3.15. Analyzing design hierarchy.. Top module: \top Used module: $paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 23.3.16. Analyzing design hierarchy.. Top module: \top Used module: $paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 23.3.17. Analyzing design hierarchy.. Top module: \top Used module: $paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Removing unused module `\uart_tool_tx'. Removing unused module `\uart_tool_rx'. Removing unused module `\UART'. Removing unused module `\Risco_5_SOC'. Removing unused module `\Memory'. Removing unused module `\GPIOS'. Removing unused module `\FIFO'. Removing unused module `\Core'. Removing unused module `\ResetBootSystem'. Removing unused module `\ClkDivider'. Removed 12 unused modules. 23.4. Executing PROC pass (convert processes to netlists). 23.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$516'. Found and cleaned up 1 empty switch in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:0$886'. Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:0$886'. Cleaned up 2 empty switches. 23.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$623 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$575 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$517 in module TRELLIS_DPR16X4. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:24$815 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$801 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$799 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$791 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$788 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$782 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$777 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$772 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$763 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$750 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$748 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$740 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$726 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$720 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$715 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:179$705 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:45$884 in module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:33$847 in module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$236 in module LEDs. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:76$652 in module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:41$638 in module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$839 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:22$94 in module Registers. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$84 in module PC. Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:10$83 in module MUX. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:10$83 in module MUX. Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$81 in module Immediate_Generator. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:181$79 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:172$75 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:158$73 in module CSR_Unit. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:113$66 in module CSR_Unit. Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$626 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Removed 1 dead cases from process $proc$Risco-5/src/core/control_unit.v:122$54 in module Control_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:122$54 in module Control_Unit. Removed 1 dead cases from process $proc$Risco-5/src/core/control_unit.v:80$52 in module Control_Unit. Marked 3 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:80$52 in module Control_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:72$51 in module Control_Unit. Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$47 in module ALU_Control. Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$47 in module ALU_Control. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:23$32 in module Alu. Removed a total of 4 dead cases. 23.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 11 redundant assignments. Promoted 146 assignments to connections. 23.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$624'. Set init value: \Q = 1'0 Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$803'. Set init value: \i = 0 Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$756'. Set init value: \i = 0 Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$708'. Set init value: \instruction_register = 0 Set init value: \memory_register = 0 Set init value: \alu_out_register = 0 Set init value: \register_data_1 = 0 Set init value: \register_data_2 = 0 Set init value: \pc_old = 0 Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$239'. Set init value: \data = 33'000000000000000000000000000000000 Found init rule in `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:0$655'. Set init value: \uart_tx_en = 1'0 Set init value: \tx_fifo_read = 1'0 Set init value: \tx_fifo_write = 1'0 Set init value: \rx_fifo_read = 1'0 Set init value: \rx_fifo_write = 1'0 Set init value: \buffer_full = 1'0 Set init value: \uart_tx_data = 8'00000000 Set init value: \tx_fifo_write_data = 8'00000000 Set init value: \rx_fifo_write_data = 8'00000000 Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$87'. Set init value: \Output = 0 Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$80'. Set init value: \csr_mcause = 0 Set init value: \csr_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000 Set init value: \csr_mepc = 0 Set init value: \csr_mie_mfie = 16'0000000000000000 Set init value: \csr_mie_meie = 1'0 Set init value: \csr_mie_msie = 1'0 Set init value: \csr_mie_mtie = 1'0 Set init value: \csr_mip_mfip = 16'0000000000000000 Set init value: \csr_mip_meip = 1'0 Set init value: \csr_mip_mtip = 1'0 Set init value: \csr_mip_msip = 1'0 Set init value: \csr_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000 Set init value: \csr_mscratch = 0 Set init value: \csr_mstatus_mie = 1'0 Set init value: \csr_mstatus_mpie = 1'0 Set init value: \csr_mtvec = 0 Set init value: \csr_mtval = 0 Set init value: \csr_write_data = 0 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$632'. Set init value: \reset_o = 1'0 Set init value: \state = 2'01 Set init value: \counter = 6'000000 Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$55'. Set init value: \state = 4'0000 Set init value: \is_immediate = 1'0 Set init value: \lorD = 1'0 Set init value: \pc_write = 1'0 Set init value: \ir_write = 1'0 Set init value: \pc_source = 1'0 Set init value: \reg_write = 1'0 Set init value: \memory_read = 1'0 Set init value: \memory_write = 1'0 Set init value: \pc_write_cond = 1'0 Set init value: \csr_write_enable = 1'0 Set init value: \aluop = 2'00 Set init value: \alu_src_a = 2'00 Set init value: \alu_src_b = 2'00 Set init value: \memory_to_reg = 2'00 Set init value: \nextstate = 4'0000 23.4.5. Executing PROC_ARST pass (detect async resets in processes). 23.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 1 switch. <suppressed ~88 debug messages> 23.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$624'. Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$623'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$575'. 1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$574_EN[3:0]$581 2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$574_DATA[3:0]$580 3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$574_ADDR[3:0]$579 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$517'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$515_EN[3:0]$523 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$515_DATA[3:0]$522 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$515_ADDR[3:0]$521 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$516'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'. 1/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$827 2/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_DATA[7:0]$826 3/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR[5:0]$825 4/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$822 5/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_DATA[7:0]$821 6/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR[5:0]$820 7/8: $0\write_ptr[5:0] 8/8: $0\read_ptr[5:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$803'. Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$801'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$799'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$791'. 1/1: $0\cycle_counter[12:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$788'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$782'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$777'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$772'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$763'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$756'. Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$750'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$748'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$740'. 1/1: $0\cycle_counter[12:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$726'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$720'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$715'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$708'. Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'. 1/6: $0\alu_out_register[31:0] 2/6: $0\register_data_2[31:0] 3/6: $0\register_data_1[31:0] 4/6: $0\memory_register[31:0] 5/6: $0\pc_old[31:0] 6/6: $0\instruction_register[31:0] Creating decoders for process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$884'. 1/1: $1\read_data[31:0] Creating decoders for process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$847'. 1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$880 2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_DATA[31:0]$879 3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_ADDR[31:0]$878 4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$883 5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_DATA[31:0]$882 6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_ADDR[31:0]$881 7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$870 8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_DATA[31:0]$869 9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_ADDR[31:0]$868 10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$876 11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_DATA[31:0]$875 12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_ADDR[31:0]$874 13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$873 14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_DATA[31:0]$872 15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_ADDR[31:0]$871 16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$866 17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_DATA[31:0]$865 18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_ADDR[31:0]$864 19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$863 20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_DATA[31:0]$862 21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_ADDR[31:0]$861 22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$860 23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_DATA[31:0]$859 24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_ADDR[31:0]$858 Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$239'. Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$236'. 1/1: $0\data[32:0] Creating decoders for process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:0$655'. Creating decoders for process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:76$652'. 1/1: $1\read_data[31:0] Creating decoders for process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:41$638'. 1/9: $0\rx_fifo_write[0:0] 2/9: $0\rx_fifo_read[0:0] 3/9: $0\tx_fifo_write[0:0] 4/9: $0\tx_fifo_read[0:0] 5/9: $0\uart_tx_en[0:0] 6/9: $0\rx_fifo_write_data[7:0] 7/9: $0\tx_fifo_write_data[7:0] 8/9: $0\uart_tx_data[7:0] 9/9: $0\buffer_full[0:0] Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$839'. 1/2: $0\gpio_value[5:0] 2/2: $0\gpio_direction[5:0] Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$112'. Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:22$94'. 1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$109 2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$90_DATA[31:0]$108 3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$90_ADDR[4:0]$107 4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$110 5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$101 6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$105 7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$104 8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$90_DATA[31:0]$103 9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$90_ADDR[4:0]$102 Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$87'. Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$84'. 1/1: $0\Output[31:0] Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:10$83'. 1/1: $1\S[31:0] Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$81'. 1/4: $4\immediate[31:0] 2/4: $3\immediate[31:0] 3/4: $2\immediate[31:0] 4/4: $1\immediate[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$80'. Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$79'. 1/1: $1\csr_data_out[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75'. 1/1: $1\csr_write_data[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'. 1/4: $0\csr_mip_msip[0:0] 2/4: $0\csr_mip_mtip[0:0] 3/4: $0\csr_mip_meip[0:0] 4/4: $0\csr_mip_mfip[15:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. 1/13: $0\csr_mtval[31:0] 2/13: $0\csr_mtvec[31:0] 3/13: $0\csr_mstatus_mpie[0:0] 4/13: $0\csr_mstatus_mie[0:0] 5/13: $0\csr_mscratch[31:0] 6/13: $0\csr_minstret[63:0] 7/13: $0\csr_mie_mtie[0:0] 8/13: $0\csr_mie_msie[0:0] 9/13: $0\csr_mie_meie[0:0] 10/13: $0\csr_mie_mfie[15:0] 11/13: $0\csr_mepc[31:0] 12/13: $0\csr_mcycle[63:0] 13/13: $0\csr_mcause[31:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$632'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$626'. 1/3: $0\counter[5:0] 2/3: $0\state[1:0] 3/3: $0\reset_o[0:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$55'. Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. 1/1: { $1\pc_write[0:0] $1\alu_src_b[1:0] $1\ir_write[0:0] $1\memory_read[0:0] $1\memory_to_reg[1:0] $1\alu_src_a[1:0] $1\aluop[1:0] $1\csr_write_enable[0:0] $1\pc_write_cond[0:0] $1\memory_write[0:0] $1\reg_write[0:0] $1\pc_source[0:0] $1\lorD[0:0] $1\is_immediate[0:0] } Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52'. 1/3: $3\nextstate[3:0] 2/3: $2\nextstate[3:0] 3/3: $1\nextstate[3:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$51'. 1/1: $0\state[3:0] Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$47'. 1/4: $4\aluop_out[3:0] 2/4: $3\aluop_out[3:0] 3/4: $2\aluop_out[3:0] 4/4: $1\aluop_out[3:0] Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:23$32'. 1/1: $1\ALU_out_S[31:0] 23.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$772'. No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$715'. No latch inferred for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.\read_data' from process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$884'. No latch inferred for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\read_data' from process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:76$652'. No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:16$88_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$112'. No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:10$83'. No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$81'. No latch inferred for signal `\CSR_Unit.\csr_mcause_code' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$80'. No latch inferred for signal `\CSR_Unit.\csr_mcause_interrupt_flag' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$80'. No latch inferred for signal `\CSR_Unit.\csr_utime' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$80'. No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$79'. No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75'. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [0]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [1]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [2]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [3]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [4]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [5]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [6]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [7]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [8]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [9]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [10]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [11]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [12]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [13]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [14]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [15]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [16]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [17]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [18]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [19]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [20]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [21]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [22]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [23]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [24]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [25]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [26]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [27]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [28]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [29]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [30]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [31]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75`. No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54`. No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52`. Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$47': $auto$proc_dlatch.cc:433:proc_dlatch$1937 No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:23$32'. 23.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$623'. created $dff cell `$procdff$1960' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$559_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$560_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$561_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$562_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$563_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$564_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$565_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$566_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$567_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$568_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$569_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$570_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$571_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$572_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$573_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$574_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$575'. created $dff cell `$procdff$1961' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$574_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$575'. created $dff cell `$procdff$1962' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$574_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$575'. created $dff cell `$procdff$1963' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$499_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$500_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$501_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$502_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$503_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$504_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$505_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$506_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$507_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$508_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$509_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$510_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$511_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$512_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$513_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$514_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$515_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$517'. created $dff cell `$procdff$1964' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$515_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$517'. created $dff cell `$procdff$1965' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$515_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$517'. created $dff cell `$procdff$1966' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$516'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'. created $dff cell `$procdff$1967' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'. created $dff cell `$procdff$1968' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'. created $dff cell `$procdff$1969' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'. created $dff cell `$procdff$1970' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'. created $dff cell `$procdff$1971' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$801'. created $dff cell `$procdff$1972' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg_0' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$801'. created $dff cell `$procdff$1973' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$799'. created $dff cell `$procdff$1974' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$791'. created $dff cell `$procdff$1975' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_sample' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$788'. created $dff cell `$procdff$1976' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$782'. created $dff cell `$procdff$1977' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$777'. created $dff cell `$procdff$1978' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\recieved_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$777'. created $dff cell `$procdff$1979' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\uart_rx_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$763'. created $dff cell `$procdff$1980' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\txd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$750'. created $dff cell `$procdff$1981' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$748'. created $dff cell `$procdff$1982' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$740'. created $dff cell `$procdff$1983' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$726'. created $dff cell `$procdff$1984' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$720'. created $dff cell `$procdff$1985' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\data_to_send' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$720'. created $dff cell `$procdff$1986' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'. created $dff cell `$procdff$1987' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'. created $dff cell `$procdff$1988' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'. created $dff cell `$procdff$1989' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'. created $dff cell `$procdff$1990' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'. created $dff cell `$procdff$1991' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'. created $dff cell `$procdff$1992' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$847'. created $dff cell `$procdff$1993' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$847'. created $dff cell `$procdff$1994' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$847'. created $dff cell `$procdff$1995' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$847'. created $dff cell `$procdff$1996' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$847'. created $dff cell `$procdff$1997' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$847'. created $dff cell `$procdff$1998' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$847'. created $dff cell `$procdff$1999' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$847'. created $dff cell `$procdff$2000' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$847'. created $dff cell `$procdff$2001' with positive edge clock. Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$236'. created $dff cell `$procdff$2002' with positive edge clock. Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\uart_tx_en' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:41$638'. created $dff cell `$procdff$2003' with positive edge clock. Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\tx_fifo_read' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:41$638'. created $dff cell `$procdff$2004' with positive edge clock. Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\tx_fifo_write' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:41$638'. created $dff cell `$procdff$2005' with positive edge clock. Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\rx_fifo_read' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:41$638'. created $dff cell `$procdff$2006' with positive edge clock. Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\rx_fifo_write' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:41$638'. created $dff cell `$procdff$2007' with positive edge clock. Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\buffer_full' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:41$638'. created $dff cell `$procdff$2008' with positive edge clock. Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\uart_tx_data' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:41$638'. created $dff cell `$procdff$2009' with positive edge clock. Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\tx_fifo_write_data' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:41$638'. created $dff cell `$procdff$2010' with positive edge clock. Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\rx_fifo_write_data' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:41$638'. created $dff cell `$procdff$2011' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$839'. created $dff cell `$procdff$2012' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$839'. created $dff cell `$procdff$2013' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$94'. created $dff cell `$procdff$2014' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$90_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$94'. created $dff cell `$procdff$2015' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$90_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$94'. created $dff cell `$procdff$2016' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$94'. created $dff cell `$procdff$2017' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$94'. created $dff cell `$procdff$2018' with positive edge clock. Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$84'. created $dff cell `$procdff$2019' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mip_mfip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'. created $dff cell `$procdff$2020' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mip_meip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'. created $dff cell `$procdff$2021' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mip_mtip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'. created $dff cell `$procdff$2022' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mip_msip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'. created $dff cell `$procdff$2023' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2024' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mcycle' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2025' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2026' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mie_mfie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2027' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mie_meie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2028' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mie_msie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2029' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mie_mtie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2030' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_minstret' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2031' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2032' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mstatus_mie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2033' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mstatus_mpie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2034' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2035' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. created $dff cell `$procdff$2036' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$626'. created $dff cell `$procdff$2037' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$626'. created $dff cell `$procdff$2038' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$626'. created $dff cell `$procdff$2039' with positive edge clock. Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$51'. created $dff cell `$procdff$2040' with positive edge clock. 23.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$624'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$623'. Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$623'. Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$598'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$575'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$541'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$517'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$516'. Found and cleaned up 3 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$815'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$803'. Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$801'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$801'. Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$799'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$799'. Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$791'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$791'. Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$788'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$788'. Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$782'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$782'. Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$777'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$777'. Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$772'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$772'. Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$763'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$763'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$756'. Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$750'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$750'. Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$748'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$748'. Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$740'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$740'. Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$726'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$726'. Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$720'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$720'. Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$715'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$715'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$708'. Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$705'. Found and cleaned up 1 empty switch in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$884'. Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$884'. Found and cleaned up 3 empty switches in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$847'. Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$847'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$239'. Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$236'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$236'. Removing empty process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:0$655'. Found and cleaned up 1 empty switch in `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:76$652'. Removing empty process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:76$652'. Found and cleaned up 5 empty switches in `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:41$638'. Removing empty process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:41$638'. Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$839'. Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$839'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$112'. Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:22$94'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:22$94'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$87'. Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$84'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$84'. Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:10$83'. Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:10$83'. Found and cleaned up 4 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$81'. Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$81'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$80'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$79'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$79'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$75'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$73'. Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$66'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$632'. Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$626'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$626'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$55'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$54'. Found and cleaned up 3 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$52'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$51'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$51'. Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$47'. Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$47'. Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:23$32'. Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:23$32'. Cleaned up 89 empty switches. 23.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. <suppressed ~4 debug messages> Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. <suppressed ~21 debug messages> Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. <suppressed ~19 debug messages> Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. <suppressed ~4 debug messages> Optimizing module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory. <suppressed ~5 debug messages> Optimizing module LEDs. <suppressed ~3 debug messages> Optimizing module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART. <suppressed ~9 debug messages> Optimizing module GPIO. <suppressed ~3 debug messages> Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. <suppressed ~4 debug messages> Optimizing module BUS. Optimizing module Registers. <suppressed ~2 debug messages> Optimizing module PC. <suppressed ~2 debug messages> Optimizing module MUX. <suppressed ~1 debug messages> Optimizing module Immediate_Generator. <suppressed ~1 debug messages> Optimizing module CSR_Unit. <suppressed ~2 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~7 debug messages> Optimizing module Control_Unit. <suppressed ~1 debug messages> Optimizing module ALU_Control. <suppressed ~15 debug messages> Optimizing module Alu. <suppressed ~1 debug messages> Optimizing module $paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC. Optimizing module top. 23.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Deleting now unused module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory. Deleting now unused module LEDs. Deleting now unused module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART. Deleting now unused module GPIO. Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Deleting now unused module BUS. Deleting now unused module Registers. Deleting now unused module PC. Deleting now unused module MUX. Deleting now unused module Immediate_Generator. Deleting now unused module CSR_Unit. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module Control_Unit. Deleting now unused module ALU_Control. Deleting now unused module Alu. Deleting now unused module $paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC. <suppressed ~30 debug messages> 23.6. Executing TRIBUF pass. 23.7. Executing DEMINOUT pass (demote inout ports to input or output). 23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~47 debug messages> 23.9. Executing OPT_CLEAN pass (remove unused cells and wires). + mkdir -p Risco-5/impl/pnr Finding unused cells or wires in module \top.. Removed 64 unused cells and 728 unused wires. <suppressed ~82 debug messages> 23.10. Executing CHECK pass (checking for obvious problems). Checking module top... Warning: Wire top.\SOC.Core.PCSourceMUX.C [31] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [30] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [29] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [28] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [27] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [26] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [25] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [24] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [23] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [22] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [21] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [20] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [19] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [18] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [17] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [16] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [15] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [14] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [13] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [12] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [11] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [10] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [9] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [8] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [7] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [6] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [5] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [4] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [3] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [2] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [1] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [0] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [15] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [14] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [13] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [12] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [11] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [10] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [9] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [8] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [7] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [6] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [5] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [4] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [3] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [2] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [1] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [0] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_external is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_timer is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_software is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [0] is used but has no driver. Found and reported 211 problems. 23.11. Executing OPT pass (performing simple optimizations). 23.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~6 debug messages> 23.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~351 debug messages> Removed a total of 117 cells. 23.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1831. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1859. dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1507. dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1509. dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1520. dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1535. dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1494. dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1494. dead port 1/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1494. dead port 2/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1494. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1454. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1460. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1466. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1472. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1251. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1253. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1260. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1262. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1269. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1271. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1278. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1280. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1287. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1289. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1296. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1298. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1304. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1310. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1316. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1322. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1328. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1334. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1340. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1346. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1352. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$918. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$924. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$930. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$918. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$924. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$930. Removed 41 multiplexer ports. <suppressed ~120 debug messages> 23.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1549: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1570_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1569_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1562_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1561_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1560_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1559_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1558_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1557_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1556_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1555_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1554_CMP $auto$opt_reduce.cc:134:opt_pmux$2097 $auto$opt_reduce.cc:134:opt_pmux$2095 $auto$opt_reduce.cc:134:opt_pmux$2093 $auto$opt_reduce.cc:134:opt_pmux$2091 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1848: { $auto$opt_reduce.cc:134:opt_pmux$2099 $flatten\SOC.\Core.\Control_Unit.$procmux$1856_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1855_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1854_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1853_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1852_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1851_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1850_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1849_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1861: { $flatten\SOC.\Core.\Control_Unit.$procmux$1877_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1860_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1832_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1874_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1866_CMP $auto$opt_reduce.cc:134:opt_pmux$2103 $auto$opt_reduce.cc:134:opt_pmux$2101 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1897: { $flatten\SOC.\Core.\ALU_Control.$procmux$1904_CMP $auto$opt_reduce.cc:134:opt_pmux$2105 $flatten\SOC.\Core.\ALU_Control.$procmux$1901_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1900_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1899_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1898_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1532: $auto$opt_reduce.cc:134:opt_pmux$2107 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1538: { $flatten\SOC.\Core.\Control_Unit.$procmux$1853_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1854_CMP $auto$opt_reduce.cc:134:opt_pmux$2111 $flatten\SOC.\Core.\Control_Unit.$procmux$1855_CMP $auto$opt_reduce.cc:134:opt_pmux$2109 $flatten\SOC.\Core.\Control_Unit.$procmux$1849_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1857_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1451: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1469: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1475: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$89_EN[31:0]$95 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1248: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1248_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1248_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1248_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] $flatten\SOC.\Memory.$procmux$1248_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1911: { $auto$opt_reduce.cc:134:opt_pmux$2115 $auto$opt_reduce.cc:134:opt_pmux$2113 $flatten\SOC.\Core.\ALU_Control.$procmux$1904_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1275: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1275_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1275_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1275_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] $flatten\SOC.\Memory.$procmux$1275_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1920: { $flatten\SOC.\Core.\ALU_Control.$procmux$1922_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1921_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1302: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1302_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1302_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1302_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] $flatten\SOC.\Memory.$procmux$1302_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$915: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$915_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$915_Y [0] New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$915_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$915_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$915_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$915_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$915_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$915_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$915_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$915_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$915: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$915_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$915_Y [0] New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$915_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$915_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$915_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$915_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$915_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$915_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$915_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$915_Y [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1478: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$110, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1469_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$91_EN[31:0]$99 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1481: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$109, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1451_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$90_EN[31:0]$98 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1320: Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$883, B=0, Y=$flatten\SOC.\Memory.$procmux$1320_Y New ports: A=$flatten\SOC.\Memory.$procmux$1275_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1320_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1320_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] $flatten\SOC.\Memory.$procmux$1320_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1338: Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$880, B=0, Y=$flatten\SOC.\Memory.$procmux$1338_Y New ports: A=$flatten\SOC.\Memory.$procmux$1248_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1338_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1338_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] $flatten\SOC.\Memory.$procmux$1338_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1373: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$870, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1302_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_EN[31:0]$850 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$933: Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$827, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$915_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$933: Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$827, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$915_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_EN[7:0]$818 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1355: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$876, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1320_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_EN[31:0]$856 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1364: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$873, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1338_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_EN[31:0]$853 [0] } Optimizing cells in module \top. Performed a total of 25 changes. 23.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 23.11.6. Executing OPT_DFF pass (perform DFF optimizations). 23.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 3 unused cells and 169 unused wires. <suppressed ~8 debug messages> 23.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 23.11.9. Rerunning OPT passes. (Maybe there is more to do..) 23.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~119 debug messages> 23.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 23.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 23.11.13. Executing OPT_DFF pass (perform DFF optimizations). 23.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 23.11.15. Executing OPT_EXPR pass (perform const folding). [Pipeline] } [Pipeline] // stage Optimizing module top. 23.11.16. Finished OPT passes. (There is nothing left to do.) 23.12. Executing FSM pass (extract and optimize FSM). 23.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. Not marking top.SOC.Core.CSR_Unit.csr_mip_mfip as FSM state register: Users of register don't seem to benefit from recoding. Register has an initialization value. Not marking top.SOC.Core.Control_Unit.state as FSM state register: Users of register don't seem to benefit from recoding. Register has an initialization value. Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state. Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. 23.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'. found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$1974 root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$765_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$780_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$793_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$779_Y found state code: 3'000 found ctrl input: \SOC.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \SOC.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$793_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$784_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$780_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$779_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$765_Y ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o } ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$765_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$779_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$780_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$784_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$793_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'0--0 -> 3'001 8'01010001 transition: 3'000 4'1--0 -> 3'000 8'01010000 transition: 3'000 4'---1 -> 3'000 8'01010000 transition: 3'010 4'--00 -> 3'010 8'00100010 transition: 3'010 4'--10 -> 3'011 8'00100011 transition: 3'010 4'---1 -> 3'000 8'00100000 transition: 3'001 4'-0-0 -> 3'001 8'00011001 transition: 3'001 4'-1-0 -> 3'010 8'00011010 transition: 3'001 4'---1 -> 3'000 8'00011000 transition: 3'011 4'-0-0 -> 3'011 8'10010011 transition: 3'011 4'-1-0 -> 3'000 8'10010000 transition: 3'011 4'---1 -> 3'000 8'10010000 23.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2116' from module `\top'. 23.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 7 unused cells and 7 unused wires. <suppressed ~8 debug messages> 23.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2116' from module `\top'. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. 23.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2116' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- 23.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2116' from module `top': ------------------------------------- Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$2116 (\SOC.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \ResetBootSystem.reset_o 1: \SOC.Uart.i_uart_rx.payload_done 2: \SOC.Uart.i_uart_rx.next_bit 3: \SOC.Uart.i_uart_rx.rxd_reg Output signals: 0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$793_Y 1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$784_Y 2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$780_Y 3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$779_Y 4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$765_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'1--0 -> 0 5'01010 1: 0 4'---1 -> 0 5'01010 2: 0 4'0--0 -> 2 5'01010 3: 1 4'---1 -> 0 5'00100 4: 1 4'--00 -> 1 5'00100 5: 1 4'--10 -> 3 5'00100 6: 2 4'---1 -> 0 5'00011 7: 2 4'-1-0 -> 1 5'00011 8: 2 4'-0-0 -> 2 5'00011 9: 3 4'-1-0 -> 0 5'10010 10: 3 4'---1 -> 0 5'10010 11: 3 4'-0-0 -> 3 5'10010 ------------------------------------- 23.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2116' from module `\top'. 23.13. Executing OPT pass (performing simple optimizations). 23.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 23.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 23.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~118 debug messages> 23.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 23.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 23.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$1986 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1199_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1193_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1184_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1175_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1166_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1157_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1139_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1148_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2166 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$2166 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1193_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1184_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1175_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1166_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1157_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1139_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1148_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$1984 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1115_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$2171 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1115_Y, Q = \SOC.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$1983 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1104_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 13'0000000000000). Adding EN signal on $auto$ff.cc:266:slice$2177 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$747_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$1982 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$1981 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1093_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$2182 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1093_Y, Q = \SOC.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1980 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1082_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2188 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1979 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1059_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1050_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1041_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1032_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1023_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1014_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$996_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1005_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2190 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1977 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$978_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$2194 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$787_Y, Q = \SOC.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1976 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$973_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$2198 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1975 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$965_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 13'0000000000000). Adding EN signal on $auto$ff.cc:266:slice$2200 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$798_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1973 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1972 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$1968 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$942_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2206 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$830_Y, Q = \SOC.Uart.TX_FIFO.write_ptr). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$1967 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$947_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2208 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$835_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$1968 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$942_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2210 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$830_Y, Q = \SOC.Uart.RX_FIFO.write_ptr). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$1967 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$947_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2212 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$835_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2011 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1416_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2214 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2010 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1421_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2216 ($sdff) from module top (D = \SOC.Uart.write_data [7:0], Q = \SOC.Uart.tx_fifo_write_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2009 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1426_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2218 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2007 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1391_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2006 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1396_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2005 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1401_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2003 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1406_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0). Adding SRST signal on $flatten\SOC.\Leds.$procdff$2002 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1381_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$2224 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2013 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1437_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2226 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2012 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1445_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2230 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction). Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2019 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1489_Y, Q = \SOC.Core.Pc.Output, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2236 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output). Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2040 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 4'0000). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2036 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1593_Y, Q = \SOC.Core.CSR_Unit.csr_mtval, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2239 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mtval). Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2035 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 1'0 \SOC.Core.CSR_Unit.csr_write_data [0] }, Q = \SOC.Core.CSR_Unit.csr_mtvec). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2034 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1619_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$2248 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2033 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1636_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mie, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$2252 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mstatus_mie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2032 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1652_Y, Q = \SOC.Core.CSR_Unit.csr_mscratch, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2256 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mscratch). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2031 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1665_Y, Q = \SOC.Core.CSR_Unit.csr_minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$2260 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1665_Y, Q = \SOC.Core.CSR_Unit.csr_minstret). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2030 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1683_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mtie, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$2264 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mie_mtie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2029 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1701_Y, Q = \SOC.Core.CSR_Unit.csr_mie_msie, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$2268 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mie_msie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2028 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1719_Y, Q = \SOC.Core.CSR_Unit.csr_mie_meie, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$2272 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [11], Q = \SOC.Core.CSR_Unit.csr_mie_meie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2027 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1737_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mfie, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:266:slice$2276 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [31:16], Q = \SOC.Core.CSR_Unit.csr_mie_mfie). Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2026 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.csr_mepc). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2025 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1760_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$2285 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1760_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2024 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1771_Y, Q = \SOC.Core.CSR_Unit.csr_mcause, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2289 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mcause). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2023 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_software, Q = \SOC.Core.CSR_Unit.csr_mip_msip, rval = 1'0). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2022 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_timer, Q = \SOC.Core.CSR_Unit.csr_mip_mtip, rval = 1'0). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2021 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_external, Q = \SOC.Core.CSR_Unit.csr_mip_meip, rval = 1'0). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2020 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_fast, Q = \SOC.Core.CSR_Unit.csr_mip_mfip, rval = 16'0000000000000000). Adding SRST signal on $flatten\SOC.\Core.$procdff$1992 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1231_Y, Q = \SOC.Core.pc_old, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2297 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old). Adding SRST signal on $flatten\SOC.\Core.$procdff$1991 ($dff) from module top (D = \SOC.Bus.write_data, Q = \SOC.Core.register_data_2, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$1990 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$1989 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$1988 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$1987 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1236_Y, Q = \SOC.Core.instruction_register, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2303 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register). Adding EN signal on $flatten\ResetBootSystem.$procdff$2039 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$2038 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Adding EN signal on $flatten\ResetBootSystem.$procdff$2037 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2280 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2280 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2243 ($dffe) from module top. Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$2225 ($sdffe) from module top. 23.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 130 unused cells and 126 unused wires. <suppressed ~131 debug messages> 23.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 23.13.9. Rerunning OPT passes. (Maybe there is more to do..) 23.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~76 debug messages> 23.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2196: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o } Optimizing cells in module \top. Performed a total of 1 changes. 23.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~15 debug messages> Removed a total of 5 cells. 23.13.13. Executing OPT_DFF pass (perform DFF optimizations). 23.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 6 unused wires. <suppressed ~2 debug messages> 23.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 23.13.16. Rerunning OPT passes. (Maybe there is more to do..) 23.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~76 debug messages> 23.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 23.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 23.13.20. Executing OPT_DFF pass (perform DFF optimizations). 23.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 23.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 23.13.23. Finished OPT passes. (There is nothing left to do.) 23.14. Executing WREDUCE pass (reducing word size of cells). Removed top 28 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\Control_Unit.$auto$mem.cc:328:emit$890 ($flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2045 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2047 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:16$111 (SOC.Core.RegisterBank.registers). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2042 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2043 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2044 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$885 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$845 (SOC.Memory.memory). Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2041 (SOC.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$814 (SOC.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2041 (SOC.Uart.TX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$814 (SOC.Uart.TX_FIFO.memory). Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1788_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$630 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$629 ($add). Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$629 ($add). Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$628 ($lt). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2311 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2316 ($ne). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$838 ($mux). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1388_CMP0 ($eq). Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$procmux$1387 ($pmux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$939 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$927 ($mux). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$835 ($mux). Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834 ($add). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$828 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$810 ($eq). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$939 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$927 ($mux). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$835 ($mux). Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834 ($add). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$828 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$810 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$776 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$775 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$774 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$773 ($mux). Removed top 2 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:111$768 ($eq). Removed top 1 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:109$766 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$742 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$734 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$732 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$729 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$728 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$724 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$719 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$718 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$717 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$716 ($mux). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$712 ($eq). Removed top 1 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$710 ($eq). Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$235 ($mux). Removed top 20 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$115 ($le). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$118 ($ge). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$119 ($le). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$122 ($ge). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$123 ($le). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$126 ($ge). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$127 ($le). Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:75$157 ($mux). Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:84$173 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$187 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Memory.$procmux$1244_CMP0 ($eq). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1361 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1370 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1379 ($mux). Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:100$53 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1497_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1497_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1497_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1874_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1873_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1872_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1871_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1870_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1860_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1857_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1856_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1855_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1852_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1851_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1832_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1829 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1922_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1904_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1903_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1902_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1890 ($mux). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$1935_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$1934_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$1933_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$1932_CMP0 ($eq). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$46 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$38 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1575_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1562_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1561_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1560_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1559_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1558_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1557_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1556_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1555_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1554_CMP0 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$72 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$70 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$69 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$114 ($ge). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1314 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1332 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1350 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1266 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1293 ($mux). Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$165 ($mux). Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$629_Y. Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$187_Y. Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0]. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$42_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$38_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$46_Y. Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[3:0]. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_ADDR[31:0]$848. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_ADDR[31:0]$851. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_ADDR[31:0]$854. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$841_ADDR[31:0]$868. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_ADDR[31:0]$871. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_ADDR[31:0]$874. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$842_ADDR[31:0]$878. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$843_ADDR[31:0]$881. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR[5:0]$816. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR[5:0]$825. Removed top 1 bits (of 8) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_DATA[7:0]$826. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834_Y. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$835_Y. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR[5:0]$816. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$804_ADDR[5:0]$825. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834_Y. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$835_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$773_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$774_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$775_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$776_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$716_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$717_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$718_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$719_Y. 23.15. Executing PEEPOPT pass (run peephole optimizers). [Pipeline] } 23.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 33 unused wires. <suppressed ~1 debug messages> 23.17. Executing SHARE pass (SAT-based resource sharing). Found 4 cells in module top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$814 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:57$124_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:55$120_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$116_Y $flatten\SOC.\Uart.$procmux$1390_CMP $flatten\SOC.\Uart.$procmux$1389_CMP $flatten\SOC.\Uart.$procmux$1388_CMP }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$845 ($memrd): Found 5 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1245_CMP $flatten\SOC.\Memory.$procmux$1244_CMP \SOC.Memory.option $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$116_Y \SOC.Bus.slave_0_write \SOC.Bus.slave_0_read }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:44$44 ($shr): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$1927_CMP. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:42$43 ($shl): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$1928_CMP. No candidates found. 23.18. Executing TECHMAP pass (map to technology primitives). 23.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 23.18.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~296 debug messages> 23.19. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 23.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 23.21. Executing TECHMAP pass (map to technology primitives). 23.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 23.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 23.21.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 23.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$629 ($add). creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$35 ($add). creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$36 ($sub). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:141$67 ($add). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:142$68 ($add). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$69 ($add). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$70 ($add). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:151$71 ($add). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$72 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$807 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$829 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$807 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$829 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$787 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$798 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$736 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$747 ($add). creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$747. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$736. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$798. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$787. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$829. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$807. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$829. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$807. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$72. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:151$71. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$70. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$69. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:142$68. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:141$67. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$36. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$35. creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$629. creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$628 ($lt): new $alu creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$114 ($ge): new $alu creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$118 ($ge): new $alu creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$122 ($ge): new $alu creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$126 ($ge): new $alu creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$115 ($le): new $alu creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$119 ($le): new $alu creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$123 ($le): new $alu creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$127 ($le): new $alu creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$45 ($ge): new $alu creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$37 ($lt): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$45. creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$630 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$628. creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$42 ($eq): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$45. creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$127: $auto$alumacc.cc:485:replace_alu$2374 creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$123: $auto$alumacc.cc:485:replace_alu$2387 creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$119: $auto$alumacc.cc:485:replace_alu$2400 creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$115: $auto$alumacc.cc:485:replace_alu$2413 creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$126: $auto$alumacc.cc:485:replace_alu$2426 creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$122: $auto$alumacc.cc:485:replace_alu$2435 creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$118: $auto$alumacc.cc:485:replace_alu$2444 creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$114: $auto$alumacc.cc:485:replace_alu$2453 creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$628, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$630: $auto$alumacc.cc:485:replace_alu$2462 creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$629: $auto$alumacc.cc:485:replace_alu$2473 creating $alu cell for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$45, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$37, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$42: $auto$alumacc.cc:485:replace_alu$2476 creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$35: $auto$alumacc.cc:485:replace_alu$2489 creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$36: $auto$alumacc.cc:485:replace_alu$2492 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:141$67: $auto$alumacc.cc:485:replace_alu$2495 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:142$68: $auto$alumacc.cc:485:replace_alu$2498 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$69: $auto$alumacc.cc:485:replace_alu$2501 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$70: $auto$alumacc.cc:485:replace_alu$2504 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:151$71: $auto$alumacc.cc:485:replace_alu$2507 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$72: $auto$alumacc.cc:485:replace_alu$2510 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$829: $auto$alumacc.cc:485:replace_alu$2513 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$807: $auto$alumacc.cc:485:replace_alu$2516 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834: $auto$alumacc.cc:485:replace_alu$2519 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$829: $auto$alumacc.cc:485:replace_alu$2522 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$807: $auto$alumacc.cc:485:replace_alu$2525 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$834: $auto$alumacc.cc:485:replace_alu$2528 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$787: $auto$alumacc.cc:485:replace_alu$2531 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$798: $auto$alumacc.cc:485:replace_alu$2534 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$736: $auto$alumacc.cc:485:replace_alu$2537 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$747: $auto$alumacc.cc:485:replace_alu$2540 created 29 $alu and 0 $macc cells. 23.23. Executing OPT pass (performing simple optimizations). 23.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~3 debug messages> 23.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~10 debug messages> Removed a total of 2 cells. 23.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~76 debug messages> 23.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 23.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 23.23.6. Executing OPT_DFF pass (perform DFF optimizations). 23.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 20 unused wires. <suppressed ~2 debug messages> 23.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 23.23.9. Rerunning OPT passes. (Maybe there is more to do..) 23.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~76 debug messages> 23.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 23.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 23.23.13. Executing OPT_DFF pass (perform DFF optimizations). 23.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 23.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 23.23.16. Finished OPT passes. (There is nothing left to do.) 23.24. Executing MEMORY pass. 23.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 23.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 23.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing top.SOC.Core.RegisterBank.registers write port 0. Analyzing top.SOC.Core.RegisterBank.registers write port 1. Analyzing top.SOC.Core.RegisterBank.registers write port 2. Analyzing top.SOC.Memory.memory write port 0. Analyzing top.SOC.Memory.memory write port 1. Analyzing top.SOC.Memory.memory write port 2. Analyzing top.SOC.Uart.RX_FIFO.memory write port 0. Analyzing top.SOC.Uart.TX_FIFO.memory write port 0. 23.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 23.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888'[0] in module `\top': no output FF found. Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found. Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': merging output FF to cell. Write port 0: don't care on collision. Write port 1: non-transparent. Write port 2: non-transparent. Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found. Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': no output FF found. Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell. Write port 0: non-transparent. Checking read port address `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888'[0] in module `\top': address FF has fully-defined init value, not supported. Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported. Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found. Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': merged address FF to cell. 23.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 44 unused wires. <suppressed ~7 debug messages> 23.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Merging ports 0, 2 (address 5'00000). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating write ports of memory top.SOC.Memory.memory by address: Merging ports 0, 1 (address \SOC.Memory.address [10:2]). Merging ports 0, 2 (address \SOC.Memory.address [10:2]). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing: Checking group clocked with posedge \clk, width 32: ports 0, 1. Common input cone for all EN signals: 6 cells. Size of unconstrained SAT problem: 40 variables, 98 clauses Merging port 1 into port 0. 23.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 23.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 8 unused cells and 8 unused wires. <suppressed ~9 debug messages> 23.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 23.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 23.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). using FF mapping for memory top.$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888 mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_ Extracted data FF from read port 1 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[1] mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_ mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted addr FF from read port 0 of top.SOC.Uart.RX_FIFO.memory: $\SOC.Uart.RX_FIFO.memory$rdreg[0] mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0] <suppressed ~1100 debug messages> 23.27. Executing TECHMAP pass (map to technology primitives). 23.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 23.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 23.27.3. Continuing TECHMAP pass. Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$1f7528d846def63a25ef79a14688e75507487b07\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$16483afc93766dfb5fb1eddfd226d96b3663d59c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$aaadea22aebcd84c93bb9858adaa720cf09b082d\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$4732e8e929fe8d0a57a6c959ddfc52773439ff42\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$5b36af983a34dea819263d47bd985c03f062c03b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$5f84a8dd211265fde0680d1329e0aeb011857798\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$65b5a9049f0a0f5b9de58368be8ce2821f51e438\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$5a90b288fb430e0f24af5f61ee43ef935b86341e\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$58ddad20e9ef77e6675ec0a973f6df52cac15605\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$569f3b21b6212e6a0e436dd55c34df99d3696e0b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$c21745a1d1b8202233eb4fd671436aaa3b71d7e7\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$eabd6f8a46e61d81805337b1dc746bfd80802602\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$98f4fff52781fee114365d416fa097fc5bdcc5a1\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$ef9fccd6f2ebbfd2f9ea51ad76fcd229dd950af9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$f05333f47f0fac035d1d00a83ba1f91fba94d570\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$e060b64551c3d3977f3359c6d9cbc2f183f778aa\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$5e6f6332f5b0abb114a71354918e4077127fc51f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$04114c6daf9b714920df2338bb84f1d824cfb28f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$df0229c2445eb19cad504fc663c8894a4b8ad2c2\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$82cf4a0fd82546fec0e453cb163e0b57b514e109\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$05123d0bc673513b0e5ab3de2414f4ca493424ef\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$3d62e89fd9fe82123196169686b7825d33b36c84\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$413228b6beffb528da7ce6c18481e68814727c46\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$74d116fba5fc319cbe4b4ef6fabb137b2ff9e708\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~635 debug messages> 23.28. Executing OPT pass (performing simple optimizations). 23.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~142 debug messages> 23.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~18 debug messages> Removed a total of 6 cells. 23.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $\SOC.Uart.RX_FIFO.memory$rdreg[0] ($dff) from module top (D = $auto$rtlil.cc:2582:Mux$2594, Q = $\SOC.Uart.RX_FIFO.memory$rdreg[0]$q, rval = 3'000). Adding SRST signal on $auto$ff.cc:266:slice$2305 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1785_Y, Q = \ResetBootSystem.counter, rval = 6'000000). Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2293 ($sdff) from module top. Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$2296 ($sdff) from module top. 23.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 20 unused cells and 2123 unused wires. <suppressed ~21 debug messages> 23.28.5. Rerunning OPT passes. (Removed registers in this run.) 23.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2 debug messages> 23.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 23.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$3407 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$2331 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). 23.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 3 unused cells and 3 unused wires. <suppressed ~4 debug messages> 23.28.10. Rerunning OPT passes. (Removed registers in this run.) 23.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 23.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 23.28.13. Executing OPT_DFF pass (perform DFF optimizations). 23.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 23.28.15. Finished fast OPT passes. 23.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory $flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888 in module \top: created 16 $dff cells and 0 static cells of width 18. read interface: 0 $dff and 15 $mux cells. write interface: 0 write mux blocks. 23.30. Executing OPT pass (performing simple optimizations). 23.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 23.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 23.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$2616: $auto$rtlil.cc:2489:ReduceOr$2610 -> 1'1 Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~59 debug messages> 23.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][3][6]$3452: Old ports: A=18'010000010000000000, B=18'010000011000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$a$3432 New ports: A=1'0, B=1'1, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$a$3432 [9] New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$a$3432 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$a$3432 [8:0] } = 17'01000001000000000 Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][3][5]$3449: Old ports: A=18'000000001010100100, B=18'101000010000000101, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [0] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [17:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [4:1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [0] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [5] 5'00010 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][3][4]$3446: Old ports: A=18'010000001100000001, B=18'101000010000000100, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 New ports: A=2'01, B=2'10, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [0] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [17:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [2] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [0] 6'000000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][3][3]$3443: Old ports: A=18'000000001100000000, B=18'000000000000001000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$b$3427 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$b$3427 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$b$3427 [3] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$b$3427 [17:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$b$3427 [7:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$b$3427 [2:0] } = { 8'00000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$b$3427 [8] 7'0000000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][3][2]$3440: Old ports: A=18'000000100000001000, B=18'000000000000010010, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$a$3426 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$a$3426 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$a$3426 [1] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$a$3426 [17:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$a$3426 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$a$3426 [0] } = { 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$a$3426 [3] 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$a$3426 [1] 2'00 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][3][1]$3437: Old ports: A=18'010000001000000000, B=18'000010000000000010, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424 [1] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424 [8:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424 [0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424 [9] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424 [1] 11'00000000000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][3][0]$3434: Old ports: A=18'101110000000000000, B=18'010000010000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [10] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [17:14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [9:0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [13] 12'000000000000 } Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$2601: Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Memory.write_data [15:0] }, B=\SOC.Memory.write_data, Y=$auto$rtlil.cc:2582:Mux$2602 New ports: A=\SOC.Memory.buffer [31:16], B=\SOC.Memory.write_data [31:16], Y=$auto$rtlil.cc:2582:Mux$2602 [31:16] New connections: $auto$rtlil.cc:2582:Mux$2602 [15:0] = \SOC.Memory.write_data [15:0] New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$1794: { $flatten\ResetBootSystem.$procmux$1789_CMP $flatten\ResetBootSystem.$procmux$1788_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1797: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$1797_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$1797_Y [1] New connections: $flatten\ResetBootSystem.$procmux$1797_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1890: Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$2333 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$2333 [2] New connections: $auto$wreduce.cc:461:run$2333 [1:0] = 2'10 Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1911: Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] } New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1 New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1549: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1570_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1569_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1562_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1561_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1560_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1559_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1558_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1557_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1556_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1555_CMP $auto$opt_reduce.cc:134:opt_pmux$2097 $auto$opt_reduce.cc:134:opt_pmux$2095 $auto$opt_reduce.cc:134:opt_pmux$2093 $auto$opt_reduce.cc:134:opt_pmux$2091 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][3][7]$3455: Old ports: A=18'010000001000000000, B=18'000001000001001000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433 [3] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433 [8:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433 [2:0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433 [9] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433 [3] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433 [3] 5'00000 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1829: Old ports: A=3'101, B=3'011, Y=$auto$wreduce.cc:461:run$2337 [2:0] New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$2337 [2:1] New connections: $auto$wreduce.cc:461:run$2337 [0] = 1'1 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1505: Old ports: A={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] }, B={ 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] New ports: A=\SOC.Core.instruction_register [24], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] New connections: { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [31:6] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] \SOC.Core.instruction_register [24:20] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1532: Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, B={ 19'0000000000000000000 \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] New ports: A=\SOC.Core.instruction_register [31], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:14] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 } Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1243: Old ports: A=\SOC.Memory.buffer, B={ 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data New ports: A=\SOC.Memory.buffer [31:8], B={ 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8] New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0] Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1077: Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$2355 [0] 1'0 $auto$wreduce.cc:461:run$2356 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$2358 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$2355 [0] $auto$wreduce.cc:461:run$2356 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$2358 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$776: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2358 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2358 [0] New connections: $auto$wreduce.cc:461:run$2358 [1] = $auto$wreduce.cc:461:run$2358 [0] Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1214: Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$2360 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$2362 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$2360 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$2362 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$719: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2362 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2362 [0] New connections: $auto$wreduce.cc:461:run$2362 [1] = $auto$wreduce.cc:461:run$2362 [0] Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$3431: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$a$3432, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 New ports: A={ 2'11 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$a$3432 [9] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433 [9] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][3]$b$3433 [3] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 [3] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 [15:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 [8:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 [2:0] } = { 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 [3] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 [3] 5'00000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$3428: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$a$3429 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [5] 1'1 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][2]$b$3430 [0] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [0] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [17:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [7:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [4:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [10] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [5] 4'0000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$3425: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$a$3426, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$b$3427, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$a$3426 [3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$a$3426 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$a$3426 [1] }, B={ 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$b$3427 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][1]$b$3427 [3] 1'0 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [1] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [17:12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [7:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [0] } = { 7'0000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [8] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [1] 2'00 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$3422: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$a$3423 [10] 2'00 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424 [9] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424 [1] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][2][0]$b$3424 [1] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [1] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [8:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [14] 10'0000000000 } Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$2605: Old ports: A=$auto$rtlil.cc:2582:Mux$2602, B={ \SOC.Memory.buffer [31:8] \SOC.Memory.write_data [7:0] }, Y=$auto$rtlil.cc:2582:Mux$2606 New ports: A={ $auto$rtlil.cc:2582:Mux$2602 [31:16] \SOC.Memory.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$2606 [31:8] New connections: $auto$rtlil.cc:2582:Mux$2606 [7:0] = \SOC.Memory.write_data [7:0] Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1803: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$1797_Y, Y=$flatten\ResetBootSystem.$procmux$1803_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$1797_Y [1], Y=$flatten\ResetBootSystem.$procmux$1803_Y [1] New connections: $flatten\ResetBootSystem.$procmux$1803_Y [0] = 1'0 Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1516: Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12:5] New connections: { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$3419: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$a$3420 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 [16] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 [10:9] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][1]$b$3421 [3] 2'00 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [16:15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [3:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [0] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [14:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [7:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [15] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [3] 2'00 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$3416: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [14:13] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [10:9] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$a$3417 [1] }, B={ 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [11] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [1] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][1][0]$b$3418 [1] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [11:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [4:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [1] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [7:5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [14] 6'000000 } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$3413: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415, Y={ \SOC.Core.pc_write \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.MemoryDataMUX.option \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond \SOC.Bus.write \SOC.Core.Control_Unit.reg_write \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.ALU_Control.is_immediate } New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [11:8] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [4:3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$a$3414 [1] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [16:15] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [3:2] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$888$rdmux[0][0][0]$b$3415 [0] }, Y={ \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.MemoryDataMUX.option [0] \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in [1] \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond \SOC.Bus.write \SOC.Core.Control_Unit.reg_write \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.ALU_Control.is_immediate } New connections: { \SOC.Core.pc_write \SOC.Core.MemoryDataMUX.option [1] \SOC.Core.ALU_Control.aluop_in [0] } = { \SOC.Core.AluInputBMUX.option [0] \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond } Optimizing cells in module \top. Performed a total of 34 changes. 23.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~15 debug messages> Removed a total of 5 cells. 23.30.6. Executing OPT_DFF pass (perform DFF optimizations). 23.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 22 unused wires. <suppressed ~2 debug messages> 23.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1 debug messages> 23.30.9. Rerunning OPT passes. (Maybe there is more to do..) 23.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~62 debug messages> 23.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 23.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 23.30.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2181 ($sdff) from module top. 23.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 23.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2 debug messages> 23.30.16. Rerunning OPT passes. (Maybe there is more to do..) 23.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~62 debug messages> 23.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 23.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 23.30.20. Executing OPT_DFF pass (perform DFF optimizations). 23.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 23.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 23.30.23. Finished OPT passes. (There is nothing left to do.) 23.31. Executing TECHMAP pass (map to technology primitives). 23.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 23.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 23.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $dffe. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $sdff. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $sdffe. Using template $paramod$3111a1a8e90c88cc8c163ba5aed0203d96ddc46d\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $bmux. Using extmapper simplemap for cells of type $tribuf. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using template $paramod$215440792383f7884e57d9c95f84e9552d0bf4ac\_80_ecp5_alu for cells of type $alu. Using template $paramod$41ef080258eed1ff8fcfbb7776f540ab469a3d7b\_80_ecp5_alu for cells of type $alu. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$c4ef20b21801b37ea2d65c32a05dfe56e84a870d\_80_ecp5_alu for cells of type $alu. Using template $paramod$ad3b00a3808c9aa98afd971fabdc5fb6557b30ff\_80_ecp5_alu for cells of type $alu. Using template $paramod$2407ada40cc3dda6c6015be2b49b748cddb5a800\_90_demux for cells of type $demux. Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux. Using template $paramod$f1fc4bc1d42e857fca43ce0fdd0da6ff25c612c4\_90_pmux for cells of type $pmux. Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux. Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux. Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux. Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $dlatch. Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $xor. Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu. Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~4293 debug messages> 23.32. Executing OPT pass (performing simple optimizations). 23.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~6139 debug messages> 23.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~4113 debug messages> Removed a total of 1371 cells. 23.32.3. Executing OPT_DFF pass (perform DFF optimizations). 23.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 769 unused cells and 4068 unused wires. <suppressed ~770 debug messages> 23.32.5. Finished fast OPT passes. 23.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 23.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 23.35. Executing TECHMAP pass (map to technology primitives). 23.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 23.35.2. Continuing TECHMAP pass. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_. No more expansions possible. <suppressed ~825 debug messages> 23.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~31 debug messages> 23.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 23.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top. 23.39. Executing ATTRMVCP pass (move or copy attributes). 23.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 4043 unused wires. <suppressed ~1 debug messages> 23.41. Executing TECHMAP pass (map to technology primitives). 23.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 23.41.2. Continuing TECHMAP pass. 23.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$22365 ($mux). Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$22364 ($logic_not). <suppressed ~4 debug messages> 23.41.4. Executing OPT pass (performing simple optimizations). 23.41.4.1. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. <suppressed ~1 debug messages> 23.41.4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 23.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \$_DLATCH_N_.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 23.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \$_DLATCH_N_. Performed a total of 0 changes. 23.41.4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 23.41.4.6. Executing OPT_DFF pass (perform DFF optimizations). 23.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \$_DLATCH_N_.. Removed 1 unused cells and 2 unused wires. <suppressed ~2 debug messages> 23.41.4.8. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. 23.41.4.9. Rerunning OPT passes. (Maybe there is more to do..) 23.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \$_DLATCH_N_.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 23.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \$_DLATCH_N_. Performed a total of 0 changes. 23.41.4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 23.41.4.13. Executing OPT_DFF pass (perform DFF optimizations). 23.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \$_DLATCH_N_.. 23.41.4.15. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. 23.41.4.16. Finished OPT passes. (There is nothing left to do.) Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_. No more expansions possible. <suppressed ~4 debug messages> 23.42. Executing ABC9 pass. 23.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 23.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 23.42.3. Executing PROC pass (convert processes to netlists). 23.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22469'. Cleaned up 1 empty switch. 23.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22470 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.3.4. Executing PROC_INIT pass (extract init attributes). 23.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22470'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22468_EN[3:0]$22474 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22468_DATA[3:0]$22475 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22468_ADDR[3:0]$22476 Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22469'. 23.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22465_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22461_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22466_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22460_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22456_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22463_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22453_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22454_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22458_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22459_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22455_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22464_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22467_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22462_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22457_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22452_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22468_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22470'. created $dff cell `$procdff$22520' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22468_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22470'. created $dff cell `$procdff$22521' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22468_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22470'. created $dff cell `$procdff$22522' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22469'. created direct connection (no actual register cell created). 23.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22494'. Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22470'. Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22469'. Cleaned up 1 empty switch. 23.42.3.12. Executing OPT_EXPR pass (perform const folding). 23.42.4. Executing PROC pass (convert processes to netlists). 23.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22540'. Cleaned up 1 empty switch. 23.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22541 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.4.4. Executing PROC_INIT pass (extract init attributes). 23.42.4.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22541'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22539_EN[3:0]$22545 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22539_DATA[3:0]$22547 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22539_ADDR[3:0]$22546 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22540'. 23.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22532_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22528_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22524_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22537_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22531_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22529_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22534_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22538_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22527_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22533_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22526_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22536_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22535_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22530_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22525_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22523_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22539_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22541'. created $dff cell `$procdff$22591' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22539_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22541'. created $dff cell `$procdff$22592' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22539_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22541'. created $dff cell `$procdff$22593' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22540'. created direct connection (no actual register cell created). 23.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22565'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22541'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22540'. Cleaned up 1 empty switch. 23.42.4.12. Executing OPT_EXPR pass (perform const folding). 23.42.5. Executing PROC pass (convert processes to netlists). 23.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22611'. Cleaned up 1 empty switch. 23.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22612 in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.5.4. Executing PROC_INIT pass (extract init attributes). 23.42.5.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22612'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22610_EN[3:0]$22618 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22610_DATA[3:0]$22617 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22610_ADDR[3:0]$22616 Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22611'. 23.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.\i' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22594_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22599_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22604_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22596_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22605_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22609_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22601_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22606_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22602_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22595_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22607_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22597_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22600_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22608_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22603_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22598_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22610_ADDR' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22612'. created $dff cell `$procdff$22662' with positive edge clock. Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22610_DATA' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22612'. created $dff cell `$procdff$22663' with positive edge clock. Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22610_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22612'. created $dff cell `$procdff$22664' with positive edge clock. Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.\muxwre' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22611'. created direct connection (no actual register cell created). 23.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22636'. Found and cleaned up 1 empty switch in `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22612'. Removing empty process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22611'. Cleaned up 1 empty switch. 23.42.5.12. Executing OPT_EXPR pass (perform const folding). 23.42.6. Executing PROC pass (convert processes to netlists). 23.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22682'. Cleaned up 1 empty switch. 23.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22683 in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.6.4. Executing PROC_INIT pass (extract init attributes). 23.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22683'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22681_EN[3:0]$22688 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22681_DATA[3:0]$22687 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22681_ADDR[3:0]$22689 Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22682'. 23.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.\i' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22665_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22670_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22666_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22676_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22672_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22678_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22668_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22674_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22680_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22673_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22667_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22679_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22677_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22671_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22675_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22669_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22681_DATA' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22683'. created $dff cell `$procdff$22733' with positive edge clock. Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22681_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22683'. created $dff cell `$procdff$22734' with positive edge clock. Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22681_ADDR' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22683'. created $dff cell `$procdff$22735' with positive edge clock. Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22682'. created direct connection (no actual register cell created). 23.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22707'. Found and cleaned up 1 empty switch in `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22683'. Removing empty process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22682'. Cleaned up 1 empty switch. 23.42.6.12. Executing OPT_EXPR pass (perform const folding). 23.42.7. Executing PROC pass (convert processes to netlists). 23.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22753'. Cleaned up 1 empty switch. 23.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22754 in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.7.4. Executing PROC_INIT pass (extract init attributes). 23.42.7.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.7.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22754'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22752_EN[3:0]$22760 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22752_DATA[3:0]$22758 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22752_ADDR[3:0]$22759 Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22753'. 23.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.\i' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22736_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22741_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22740_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22747_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22746_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22737_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22738_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22743_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22744_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22749_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22750_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22748_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22742_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22751_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22745_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22739_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22752_DATA' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22754'. created $dff cell `$procdff$22804' with positive edge clock. Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22752_ADDR' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22754'. created $dff cell `$procdff$22805' with positive edge clock. Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22752_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22754'. created $dff cell `$procdff$22806' with positive edge clock. Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22753'. created direct connection (no actual register cell created). 23.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22778'. Found and cleaned up 1 empty switch in `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22754'. Removing empty process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22753'. Cleaned up 1 empty switch. 23.42.7.12. Executing OPT_EXPR pass (perform const folding). 23.42.8. Executing PROC pass (convert processes to netlists). 23.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22824'. Cleaned up 1 empty switch. 23.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22825 in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.8.4. Executing PROC_INIT pass (extract init attributes). 23.42.8.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.8.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22825'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22823_EN[3:0]$22830 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22823_DATA[3:0]$22831 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22823_ADDR[3:0]$22829 Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22824'. 23.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.\i' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22810_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22811_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22816_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22817_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22822_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22808_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22814_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22820_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22819_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22813_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22812_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22818_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22821_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22815_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22809_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22807_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22823_ADDR' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22825'. created $dff cell `$procdff$22875' with positive edge clock. Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22823_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22825'. created $dff cell `$procdff$22876' with positive edge clock. Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22823_DATA' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22825'. created $dff cell `$procdff$22877' with positive edge clock. Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.\muxwre' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22824'. created direct connection (no actual register cell created). 23.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22849'. Found and cleaned up 1 empty switch in `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22825'. Removing empty process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22824'. Cleaned up 1 empty switch. 23.42.8.12. Executing OPT_EXPR pass (perform const folding). 23.42.9. Executing PROC pass (convert processes to netlists). 23.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22895'. Cleaned up 1 empty switch. 23.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22896 in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.9.4. Executing PROC_INIT pass (extract init attributes). 23.42.9.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.9.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22896'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22894_EN[3:0]$22902 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22894_DATA[3:0]$22901 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22894_ADDR[3:0]$22900 Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22895'. 23.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.\i' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22880_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22881_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22882_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22886_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22887_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22893_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22892_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22888_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22883_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22884_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22889_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22890_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22878_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22891_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22885_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22879_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22894_ADDR' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22896'. created $dff cell `$procdff$22946' with positive edge clock. Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22894_DATA' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22896'. created $dff cell `$procdff$22947' with positive edge clock. Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22894_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22896'. created $dff cell `$procdff$22948' with positive edge clock. Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.\muxwre' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22895'. created direct connection (no actual register cell created). 23.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22920'. Found and cleaned up 1 empty switch in `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22896'. Removing empty process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22895'. Cleaned up 1 empty switch. 23.42.9.12. Executing OPT_EXPR pass (perform const folding). 23.42.10. Executing PROC pass (convert processes to netlists). 23.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22966'. Cleaned up 1 empty switch. 23.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22967 in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.10.4. Executing PROC_INIT pass (extract init attributes). 23.42.10.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.10.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22967'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22965_EN[3:0]$22973 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22965_DATA[3:0]$22971 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22965_ADDR[3:0]$22972 Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22966'. 23.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.\i' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22949_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22950_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22951_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22952_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22956_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22957_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22958_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22962_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22963_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22953_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22964_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22954_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22959_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22960_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22961_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22955_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22965_DATA' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22967'. created $dff cell `$procdff$23017' with positive edge clock. Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22965_ADDR' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22967'. created $dff cell `$procdff$23018' with positive edge clock. Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22965_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22967'. created $dff cell `$procdff$23019' with positive edge clock. Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.\muxwre' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22966'. created direct connection (no actual register cell created). 23.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22991'. Found and cleaned up 1 empty switch in `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22967'. Removing empty process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22966'. Cleaned up 1 empty switch. 23.42.10.12. Executing OPT_EXPR pass (perform const folding). 23.42.11. Executing PROC pass (convert processes to netlists). 23.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23037'. Cleaned up 1 empty switch. 23.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23038 in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.11.4. Executing PROC_INIT pass (extract init attributes). 23.42.11.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.11.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23038'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23036_EN[3:0]$23043 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23036_DATA[3:0]$23044 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23036_ADDR[3:0]$23042 Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23037'. 23.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.\i' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23030_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23029_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23024_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23034_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23023_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23033_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23032_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23028_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23027_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23026_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23022_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23021_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23035_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23020_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23031_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23025_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23036_ADDR' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23038'. created $dff cell `$procdff$23088' with positive edge clock. Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23036_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23038'. created $dff cell `$procdff$23089' with positive edge clock. Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23036_DATA' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23038'. created $dff cell `$procdff$23090' with positive edge clock. Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23037'. created direct connection (no actual register cell created). 23.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23062'. Found and cleaned up 1 empty switch in `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23038'. Removing empty process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23037'. Cleaned up 1 empty switch. 23.42.11.12. Executing OPT_EXPR pass (perform const folding). 23.42.12. Executing PROC pass (convert processes to netlists). 23.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23108'. Cleaned up 1 empty switch. 23.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23109 in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.12.4. Executing PROC_INIT pass (extract init attributes). 23.42.12.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.12.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23109'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23107_EN[3:0]$23113 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23107_DATA[3:0]$23114 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23107_ADDR[3:0]$23115 Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23108'. 23.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23106_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23097_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23096_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.\i' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23105_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23100_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23099_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23094_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23104_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23103_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23102_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23091_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23098_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23093_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23092_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23101_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23095_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23107_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23109'. created $dff cell `$procdff$23159' with positive edge clock. Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23107_DATA' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23109'. created $dff cell `$procdff$23160' with positive edge clock. Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23107_ADDR' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23109'. created $dff cell `$procdff$23161' with positive edge clock. Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.\muxwre' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23108'. created direct connection (no actual register cell created). 23.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23133'. Found and cleaned up 1 empty switch in `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23109'. Removing empty process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23108'. Cleaned up 1 empty switch. 23.42.12.12. Executing OPT_EXPR pass (perform const folding). 23.42.13. Executing PROC pass (convert processes to netlists). 23.42.13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23179'. Cleaned up 1 empty switch. 23.42.13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23180 in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.13.4. Executing PROC_INIT pass (extract init attributes). 23.42.13.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.13.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.13.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23180'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23178_EN[3:0]$23184 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23178_DATA[3:0]$23185 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23178_ADDR[3:0]$23186 Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23179'. 23.42.13.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.13.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.\i' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23173_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23176_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23175_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23170_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23169_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23164_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23174_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23163_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23172_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23168_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23166_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23162_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23167_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23177_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23171_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23165_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23178_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23180'. created $dff cell `$procdff$23230' with positive edge clock. Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23178_DATA' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23180'. created $dff cell `$procdff$23231' with positive edge clock. Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23178_ADDR' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23180'. created $dff cell `$procdff$23232' with positive edge clock. Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.\muxwre' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23179'. created direct connection (no actual register cell created). 23.42.13.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23204'. Found and cleaned up 1 empty switch in `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23180'. Removing empty process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23179'. Cleaned up 1 empty switch. 23.42.13.12. Executing OPT_EXPR pass (perform const folding). 23.42.14. Executing PROC pass (convert processes to netlists). 23.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23250'. Cleaned up 1 empty switch. 23.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23251 in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.14.4. Executing PROC_INIT pass (extract init attributes). 23.42.14.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.14.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23251'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23249_EN[3:0]$23255 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23249_DATA[3:0]$23256 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23249_ADDR[3:0]$23257 Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23250'. 23.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23246_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23245_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23240_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.\i' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23239_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23234_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23248_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23244_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23243_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23237_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23236_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23238_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23242_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23247_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23241_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23235_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23233_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23249_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23251'. created $dff cell `$procdff$23301' with positive edge clock. Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23249_DATA' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23251'. created $dff cell `$procdff$23302' with positive edge clock. Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23249_ADDR' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23251'. created $dff cell `$procdff$23303' with positive edge clock. Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23250'. created direct connection (no actual register cell created). 23.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23275'. Found and cleaned up 1 empty switch in `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23251'. Removing empty process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23250'. Cleaned up 1 empty switch. 23.42.14.12. Executing OPT_EXPR pass (perform const folding). 23.42.15. Executing PROC pass (convert processes to netlists). 23.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23321'. Cleaned up 1 empty switch. 23.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23322 in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.15.4. Executing PROC_INIT pass (extract init attributes). 23.42.15.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.15.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23322'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23320_EN[3:0]$23326 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23320_DATA[3:0]$23327 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23320_ADDR[3:0]$23328 Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23321'. 23.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23316_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23315_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23310_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23309_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23319_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23318_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23314_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23313_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23312_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23308_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23307_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23306_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.\i' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23304_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23317_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23311_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23305_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23320_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23322'. created $dff cell `$procdff$23372' with positive edge clock. Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23320_DATA' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23322'. created $dff cell `$procdff$23373' with positive edge clock. Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23320_ADDR' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23322'. created $dff cell `$procdff$23374' with positive edge clock. Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23321'. created direct connection (no actual register cell created). 23.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23346'. Found and cleaned up 1 empty switch in `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23322'. Removing empty process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23321'. Cleaned up 1 empty switch. 23.42.15.12. Executing OPT_EXPR pass (perform const folding). 23.42.16. Executing PROC pass (convert processes to netlists). 23.42.16.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23392'. Cleaned up 1 empty switch. 23.42.16.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23393 in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.16.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.16.4. Executing PROC_INIT pass (extract init attributes). 23.42.16.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.16.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.16.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23393'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23391_EN[3:0]$23399 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23391_DATA[3:0]$23397 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23391_ADDR[3:0]$23398 Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23392'. 23.42.16.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.16.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.\i' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23386_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23385_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23380_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23390_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23379_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23389_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23388_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23384_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23383_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23382_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23378_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23377_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23376_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23375_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23387_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23381_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23391_DATA' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23393'. created $dff cell `$procdff$23443' with positive edge clock. Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23391_ADDR' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23393'. created $dff cell `$procdff$23444' with positive edge clock. Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23391_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23393'. created $dff cell `$procdff$23445' with positive edge clock. Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.\muxwre' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23392'. created direct connection (no actual register cell created). 23.42.16.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.16.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23417'. Found and cleaned up 1 empty switch in `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23393'. Removing empty process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23392'. Cleaned up 1 empty switch. 23.42.16.12. Executing OPT_EXPR pass (perform const folding). 23.42.17. Executing PROC pass (convert processes to netlists). 23.42.17.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23463'. Cleaned up 1 empty switch. 23.42.17.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23464 in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.17.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.17.4. Executing PROC_INIT pass (extract init attributes). 23.42.17.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.17.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.17.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23464'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23462_EN[3:0]$23469 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23462_DATA[3:0]$23470 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23462_ADDR[3:0]$23468 Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23463'. 23.42.17.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.17.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.\i' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23461_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23456_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23455_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23450_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23460_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23449_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23459_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23458_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23454_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23453_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23452_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23448_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23447_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23446_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23457_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23451_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23462_ADDR' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23464'. created $dff cell `$procdff$23514' with positive edge clock. Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23462_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23464'. created $dff cell `$procdff$23515' with positive edge clock. Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23462_DATA' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23464'. created $dff cell `$procdff$23516' with positive edge clock. Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.\muxwre' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23463'. created direct connection (no actual register cell created). 23.42.17.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.17.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23488'. Found and cleaned up 1 empty switch in `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23464'. Removing empty process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23463'. Cleaned up 1 empty switch. 23.42.17.12. Executing OPT_EXPR pass (perform const folding). 23.42.18. Executing PROC pass (convert processes to netlists). 23.42.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23534'. Cleaned up 1 empty switch. 23.42.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23535 in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.18.4. Executing PROC_INIT pass (extract init attributes). 23.42.18.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.18.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23535'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23533_EN[3:0]$23539 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23533_DATA[3:0]$23540 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23533_ADDR[3:0]$23541 Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23534'. 23.42.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.18.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23517_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.\i' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23526_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23525_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23520_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23530_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23519_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23529_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23532_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23531_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23528_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23524_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23523_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23522_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23518_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23527_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23521_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23533_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23535'. created $dff cell `$procdff$23585' with positive edge clock. Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23533_DATA' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23535'. created $dff cell `$procdff$23586' with positive edge clock. Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23533_ADDR' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23535'. created $dff cell `$procdff$23587' with positive edge clock. Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23534'. created direct connection (no actual register cell created). 23.42.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23559'. Found and cleaned up 1 empty switch in `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23535'. Removing empty process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23534'. Cleaned up 1 empty switch. 23.42.18.12. Executing OPT_EXPR pass (perform const folding). 23.42.19. Executing PROC pass (convert processes to netlists). 23.42.19.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23605'. Cleaned up 1 empty switch. 23.42.19.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23606 in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.19.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.19.4. Executing PROC_INIT pass (extract init attributes). 23.42.19.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.19.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.19.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23606'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23604_EN[3:0]$23610 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23604_DATA[3:0]$23611 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23604_ADDR[3:0]$23612 Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23605'. 23.42.19.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.19.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.\i' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23588_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23602_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23601_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23596_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23595_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23590_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23600_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23589_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23599_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23598_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23594_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23592_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23593_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23603_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23597_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23591_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23604_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23606'. created $dff cell `$procdff$23656' with positive edge clock. Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23604_DATA' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23606'. created $dff cell `$procdff$23657' with positive edge clock. Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23604_ADDR' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23606'. created $dff cell `$procdff$23658' with positive edge clock. Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.\muxwre' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23605'. created direct connection (no actual register cell created). 23.42.19.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.19.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23630'. Found and cleaned up 1 empty switch in `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23606'. Removing empty process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23605'. Cleaned up 1 empty switch. 23.42.19.12. Executing OPT_EXPR pass (perform const folding). 23.42.20. Executing PROC pass (convert processes to netlists). 23.42.20.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23676'. Cleaned up 1 empty switch. 23.42.20.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23677 in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.20.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.20.4. Executing PROC_INIT pass (extract init attributes). 23.42.20.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.20.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.20.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23677'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23675_EN[3:0]$23683 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23675_DATA[3:0]$23682 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23675_ADDR[3:0]$23681 Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23676'. 23.42.20.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.20.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.\i' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23664_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23668_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23669_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23670_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23674_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23660_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23665_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23666_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23671_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23672_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23663_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23662_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23673_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23667_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23661_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23659_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23675_ADDR' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23677'. created $dff cell `$procdff$23727' with positive edge clock. Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23675_DATA' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23677'. created $dff cell `$procdff$23728' with positive edge clock. Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23675_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23677'. created $dff cell `$procdff$23729' with positive edge clock. Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23676'. created direct connection (no actual register cell created). 23.42.20.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.20.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23701'. Found and cleaned up 1 empty switch in `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23677'. Removing empty process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23676'. Cleaned up 1 empty switch. 23.42.20.12. Executing OPT_EXPR pass (perform const folding). 23.42.21. Executing PROC pass (convert processes to netlists). 23.42.21.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23747'. Cleaned up 1 empty switch. 23.42.21.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23748 in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.21.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.21.4. Executing PROC_INIT pass (extract init attributes). 23.42.21.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.21.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.21.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23748'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23746_EN[3:0]$23753 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23746_DATA[3:0]$23754 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23746_ADDR[3:0]$23752 Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23747'. 23.42.21.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.21.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23740_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.\i' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23736_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23739_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23738_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23734_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23733_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23732_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23730_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23745_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23744_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23735_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23742_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23741_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23743_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23737_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23731_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23746_ADDR' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23748'. created $dff cell `$procdff$23798' with positive edge clock. Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23746_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23748'. created $dff cell `$procdff$23799' with positive edge clock. Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23746_DATA' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23748'. created $dff cell `$procdff$23800' with positive edge clock. Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.\muxwre' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23747'. created direct connection (no actual register cell created). 23.42.21.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.21.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23772'. Found and cleaned up 1 empty switch in `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23748'. Removing empty process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23747'. Cleaned up 1 empty switch. 23.42.21.12. Executing OPT_EXPR pass (perform const folding). 23.42.22. Executing PROC pass (convert processes to netlists). 23.42.22.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23818'. Cleaned up 1 empty switch. 23.42.22.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23819 in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.22.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.22.4. Executing PROC_INIT pass (extract init attributes). 23.42.22.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.22.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.22.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23819'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23817_EN[3:0]$23825 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23817_DATA[3:0]$23823 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23817_ADDR[3:0]$23824 Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23818'. 23.42.22.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.22.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.\i' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23812_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23811_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23806_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23816_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23805_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23815_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23814_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23810_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23809_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23808_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23804_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23803_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23802_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23801_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23813_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23807_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23817_DATA' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23819'. created $dff cell `$procdff$23869' with positive edge clock. Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23817_ADDR' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23819'. created $dff cell `$procdff$23870' with positive edge clock. Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23817_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23819'. created $dff cell `$procdff$23871' with positive edge clock. Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.\muxwre' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23818'. created direct connection (no actual register cell created). 23.42.22.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.22.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23843'. Found and cleaned up 1 empty switch in `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23819'. Removing empty process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23818'. Cleaned up 1 empty switch. 23.42.22.12. Executing OPT_EXPR pass (perform const folding). 23.42.23. Executing PROC pass (convert processes to netlists). 23.42.23.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23889'. Cleaned up 1 empty switch. 23.42.23.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23890 in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.23.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.23.4. Executing PROC_INIT pass (extract init attributes). 23.42.23.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.23.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.23.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23890'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23888_EN[3:0]$23895 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23888_DATA[3:0]$23896 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23888_ADDR[3:0]$23894 Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23889'. 23.42.23.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.23.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23881_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.\i' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23879_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23880_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23884_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23885_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23875_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23886_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23874_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23878_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23873_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23887_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23882_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23872_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23876_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23883_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23877_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23888_ADDR' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23890'. created $dff cell `$procdff$23940' with positive edge clock. Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23888_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23890'. created $dff cell `$procdff$23941' with positive edge clock. Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23888_DATA' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23890'. created $dff cell `$procdff$23942' with positive edge clock. Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.\muxwre' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23889'. created direct connection (no actual register cell created). 23.42.23.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.23.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23914'. Found and cleaned up 1 empty switch in `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23890'. Removing empty process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23889'. Cleaned up 1 empty switch. 23.42.23.12. Executing OPT_EXPR pass (perform const folding). 23.42.24. Executing PROC pass (convert processes to netlists). 23.42.24.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23960'. Cleaned up 1 empty switch. 23.42.24.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23961 in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.24.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.24.4. Executing PROC_INIT pass (extract init attributes). 23.42.24.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.24.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.24.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23961'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23959_EN[3:0]$23966 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23959_DATA[3:0]$23965 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23959_ADDR[3:0]$23967 Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23960'. 23.42.24.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.24.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.\i' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23951_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23949_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23956_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23945_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23958_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23957_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23952_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23946_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23943_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23944_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23948_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23950_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23954_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23955_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23953_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23947_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23959_DATA' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23961'. created $dff cell `$procdff$24011' with positive edge clock. Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23959_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23961'. created $dff cell `$procdff$24012' with positive edge clock. Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23959_ADDR' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23961'. created $dff cell `$procdff$24013' with positive edge clock. Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23960'. created direct connection (no actual register cell created). 23.42.24.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.24.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23985'. Found and cleaned up 1 empty switch in `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23961'. Removing empty process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23960'. Cleaned up 1 empty switch. 23.42.24.12. Executing OPT_EXPR pass (perform const folding). 23.42.25. Executing PROC pass (convert processes to netlists). 23.42.25.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24031'. Cleaned up 1 empty switch. 23.42.25.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24032 in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.25.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.25.4. Executing PROC_INIT pass (extract init attributes). 23.42.25.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.25.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.25.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24032'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24030_EN[3:0]$24036 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24030_DATA[3:0]$24037 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24030_ADDR[3:0]$24038 Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24031'. 23.42.25.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.25.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24019_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24020_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24018_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24014_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.\i' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24027_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24021_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24016_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24022_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24026_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24015_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24025_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24024_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24028_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24029_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24023_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24017_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24030_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24032'. created $dff cell `$procdff$24082' with positive edge clock. Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24030_DATA' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24032'. created $dff cell `$procdff$24083' with positive edge clock. Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24030_ADDR' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24032'. created $dff cell `$procdff$24084' with positive edge clock. Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24031'. created direct connection (no actual register cell created). 23.42.25.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.25.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24056'. Found and cleaned up 1 empty switch in `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24032'. Removing empty process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24031'. Cleaned up 1 empty switch. 23.42.25.12. Executing OPT_EXPR pass (perform const folding). 23.42.26. Executing PROC pass (convert processes to netlists). 23.42.26.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24102'. Cleaned up 1 empty switch. 23.42.26.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24103 in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.26.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.26.4. Executing PROC_INIT pass (extract init attributes). 23.42.26.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.26.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.26.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24103'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24101_EN[3:0]$24109 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24101_DATA[3:0]$24108 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24101_ADDR[3:0]$24107 Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24102'. 23.42.26.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.26.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.\i' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24100_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24096_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24090_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24085_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24086_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24087_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24091_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24092_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24093_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24089_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24094_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24097_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24095_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24098_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24088_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24099_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24101_ADDR' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24103'. created $dff cell `$procdff$24153' with positive edge clock. Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24101_DATA' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24103'. created $dff cell `$procdff$24154' with positive edge clock. Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24101_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24103'. created $dff cell `$procdff$24155' with positive edge clock. Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.\muxwre' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24102'. created direct connection (no actual register cell created). 23.42.26.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.26.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24127'. Found and cleaned up 1 empty switch in `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24103'. Removing empty process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24102'. Cleaned up 1 empty switch. 23.42.26.12. Executing OPT_EXPR pass (perform const folding). 23.42.27. Executing PROC pass (convert processes to netlists). 23.42.27.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24173'. Cleaned up 1 empty switch. 23.42.27.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24174 in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.27.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.27.4. Executing PROC_INIT pass (extract init attributes). 23.42.27.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.27.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.27.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24174'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24172_EN[3:0]$24178 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24172_DATA[3:0]$24180 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24172_ADDR[3:0]$24179 Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24173'. 23.42.27.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.27.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.\i' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24168_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24162_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24157_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24156_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24158_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24159_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24163_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24164_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24165_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24169_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24170_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24160_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24171_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24167_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24161_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24166_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24172_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24174'. created $dff cell `$procdff$24224' with positive edge clock. Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24172_ADDR' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24174'. created $dff cell `$procdff$24225' with positive edge clock. Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24172_DATA' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24174'. created $dff cell `$procdff$24226' with positive edge clock. Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.\muxwre' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24173'. created direct connection (no actual register cell created). 23.42.27.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.27.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24198'. Found and cleaned up 1 empty switch in `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24174'. Removing empty process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24173'. Cleaned up 1 empty switch. 23.42.27.12. Executing OPT_EXPR pass (perform const folding). 23.42.28. Executing PROC pass (convert processes to netlists). 23.42.28.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24244'. Cleaned up 1 empty switch. 23.42.28.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24245 in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 23.42.28.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 23.42.28.4. Executing PROC_INIT pass (extract init attributes). 23.42.28.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.28.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 23.42.28.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24245'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24243_EN[3:0]$24251 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24243_DATA[3:0]$24250 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24243_ADDR[3:0]$24249 Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24244'. 23.42.28.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.28.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.\i' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24242_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24236_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24230_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24227_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24233_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24232_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24231_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24237_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24238_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24228_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24239_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24229_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24234_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24235_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24240_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24241_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24243_ADDR' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24245'. created $dff cell `$procdff$24295' with positive edge clock. Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24243_DATA' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24245'. created $dff cell `$procdff$24296' with positive edge clock. Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24243_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24245'. created $dff cell `$procdff$24297' with positive edge clock. Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24244'. created direct connection (no actual register cell created). 23.42.28.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.28.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24269'. Found and cleaned up 1 empty switch in `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24245'. Removing empty process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24244'. Cleaned up 1 empty switch. 23.42.28.12. Executing OPT_EXPR pass (perform const folding). 23.42.29. Executing SCC pass (detecting logic loops). Found an SCC: $techmap$auto$ff.cc:266:slice$8069.$auto$simplemap.cc:267:simplemap_mux$22367 Found an SCC: $techmap$auto$ff.cc:266:slice$8068.$auto$simplemap.cc:267:simplemap_mux$22367 Found an SCC: $techmap$auto$ff.cc:266:slice$8067.$auto$simplemap.cc:267:simplemap_mux$22367 Found an SCC: $techmap$auto$ff.cc:266:slice$8066.$auto$simplemap.cc:267:simplemap_mux$22367 Found an SCC: $auto$ff.cc:266:slice$5880 $auto$simplemap.cc:126:simplemap_reduce$5991 $auto$simplemap.cc:38:simplemap_not$11752 $auto$simplemap.cc:126:simplemap_reduce$6026 $auto$ff.cc:266:slice$5881 $auto$simplemap.cc:38:simplemap_not$11753 $auto$ff.cc:266:slice$5882 $auto$simplemap.cc:126:simplemap_reduce$5998 $auto$simplemap.cc:126:simplemap_reduce$5992 $auto$simplemap.cc:126:simplemap_reduce$6033 $auto$simplemap.cc:126:simplemap_reduce$6027 $auto$simplemap.cc:38:simplemap_not$11754 $auto$ff.cc:266:slice$5883 $auto$simplemap.cc:38:simplemap_not$11755 $auto$ff.cc:266:slice$5884 $auto$simplemap.cc:126:simplemap_reduce$5993 $auto$ff.cc:266:slice$5885 $auto$ff.cc:266:slice$5886 $auto$simplemap.cc:38:simplemap_not$11759 $auto$ff.cc:266:slice$5888 $auto$simplemap.cc:126:simplemap_reduce$6002 $auto$simplemap.cc:126:simplemap_reduce$5999 $auto$simplemap.cc:126:simplemap_reduce$6029 $auto$ff.cc:266:slice$5887 $auto$simplemap.cc:126:simplemap_reduce$5995 $auto$simplemap.cc:126:simplemap_reduce$6030 $auto$simplemap.cc:38:simplemap_not$11760 $auto$ff.cc:266:slice$5889 $auto$simplemap.cc:38:simplemap_not$11761 $auto$ff.cc:266:slice$5890 $auto$simplemap.cc:126:simplemap_reduce$6000 $auto$simplemap.cc:126:simplemap_reduce$5996 $auto$simplemap.cc:126:simplemap_reduce$6035 $auto$simplemap.cc:126:simplemap_reduce$6031 $auto$simplemap.cc:38:simplemap_not$11762 $auto$ff.cc:266:slice$5891 $auto$simplemap.cc:126:simplemap_reduce$6038 $auto$simplemap.cc:225:simplemap_logbin$5972 $auto$simplemap.cc:196:simplemap_lognot$6007 $auto$simplemap.cc:126:simplemap_reduce$6005 $auto$simplemap.cc:126:simplemap_reduce$6003 $auto$ff.cc:266:slice$5892 $auto$simplemap.cc:167:logic_reduce$4106 $auto$simplemap.cc:225:simplemap_logbin$5971 $auto$simplemap.cc:196:simplemap_lognot$6042 $auto$simplemap.cc:126:simplemap_reduce$6040 $auto$simplemap.cc:126:simplemap_reduce$6037 $auto$simplemap.cc:126:simplemap_reduce$6034 $auto$simplemap.cc:126:simplemap_reduce$6028 $auto$simplemap.cc:38:simplemap_not$11756 Found an SCC: $auto$simplemap.cc:38:simplemap_not$13101 $auto$ff.cc:266:slice$6048 $auto$simplemap.cc:126:simplemap_reduce$6174 $auto$simplemap.cc:126:simplemap_reduce$6159 $auto$ff.cc:266:slice$6049 $auto$ff.cc:266:slice$6050 $auto$simplemap.cc:75:simplemap_bitop$13085 $auto$simplemap.cc:196:simplemap_lognot$6179 $auto$simplemap.cc:126:simplemap_reduce$6177 $auto$simplemap.cc:126:simplemap_reduce$6175 $auto$opt_expr.cc:613:replace_const_cells$21282 $auto$opt_expr.cc:613:replace_const_cells$21474 $auto$simplemap.cc:267:simplemap_mux$13081 $auto$simplemap.cc:126:simplemap_reduce$13095 $auto$simplemap.cc:126:simplemap_reduce$13092 $auto$simplemap.cc:126:simplemap_reduce$13097 $auto$simplemap.cc:75:simplemap_bitop$13083 $auto$simplemap.cc:267:simplemap_mux$6140 $auto$simplemap.cc:225:simplemap_logbin$6149 $auto$simplemap.cc:196:simplemap_lognot$6164 $auto$simplemap.cc:126:simplemap_reduce$6162 $auto$simplemap.cc:126:simplemap_reduce$6160 $auto$ff.cc:266:slice$6051 $auto$simplemap.cc:126:simplemap_reduce$4127 $auto$simplemap.cc:126:simplemap_reduce$4125 $auto$simplemap.cc:225:simplemap_logbin$6099 $auto$simplemap.cc:196:simplemap_lognot$6109 $auto$simplemap.cc:126:simplemap_reduce$6107 $auto$opt_expr.cc:613:replace_const_cells$21472 $auto$simplemap.cc:267:simplemap_mux$13082 $auto$simplemap.cc:126:simplemap_reduce$13100 Found an SCC: $auto$ff.cc:266:slice$6052 $auto$simplemap.cc:126:simplemap_reduce$6198 $auto$ff.cc:266:slice$6053 $auto$simplemap.cc:38:simplemap_not$11827 $auto$ff.cc:266:slice$6054 $auto$simplemap.cc:38:simplemap_not$11828 $auto$ff.cc:266:slice$6055 $auto$ff.cc:266:slice$6056 $auto$simplemap.cc:126:simplemap_reduce$6200 $auto$simplemap.cc:38:simplemap_not$11830 $auto$ff.cc:266:slice$6057 $auto$ff.cc:266:slice$6058 $auto$simplemap.cc:126:simplemap_reduce$6206 $auto$simplemap.cc:126:simplemap_reduce$6201 $auto$ff.cc:266:slice$6059 $auto$ff.cc:266:slice$6060 $auto$simplemap.cc:126:simplemap_reduce$6202 $auto$simplemap.cc:38:simplemap_not$11834 $auto$ff.cc:266:slice$6061 $auto$ff.cc:266:slice$6062 $auto$simplemap.cc:126:simplemap_reduce$6207 $auto$simplemap.cc:126:simplemap_reduce$6203 $auto$simplemap.cc:38:simplemap_not$11836 $auto$ff.cc:266:slice$6063 $auto$simplemap.cc:126:simplemap_reduce$6210 $auto$ff.cc:266:slice$6064 $auto$simplemap.cc:126:simplemap_reduce$4154 $auto$simplemap.cc:196:simplemap_lognot$6214 $auto$simplemap.cc:126:simplemap_reduce$6212 $auto$simplemap.cc:126:simplemap_reduce$6209 $auto$simplemap.cc:126:simplemap_reduce$6205 $auto$simplemap.cc:126:simplemap_reduce$6199 Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$4339 $auto$simplemap.cc:38:simplemap_not$4042 $auto$simplemap.cc:38:simplemap_not$14866 $auto$ff.cc:266:slice$3567 $auto$ff.cc:479:convert_ce_over_srst$21644 $auto$ff.cc:266:slice$3568 $auto$ff.cc:479:convert_ce_over_srst$21646 $auto$simplemap.cc:126:simplemap_reduce$4046 $auto$ff.cc:266:slice$3566 $auto$ff.cc:479:convert_ce_over_srst$21642 $auto$simplemap.cc:38:simplemap_not$14864 $auto$ff.cc:266:slice$3565 $auto$ff.cc:479:convert_ce_over_srst$21640 $auto$simplemap.cc:38:simplemap_not$3959 $auto$alumacc.cc:485:replace_alu$2462.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$2462.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2462.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$4049 $auto$simplemap.cc:126:simplemap_reduce$4045 $auto$simplemap.cc:38:simplemap_not$20166 $auto$ff.cc:266:slice$3564 $auto$ff.cc:479:convert_ce_over_srst$21638 $auto$simplemap.cc:126:simplemap_reduce$4278 $auto$simplemap.cc:75:simplemap_bitop$4043 $auto$simplemap.cc:126:simplemap_reduce$4252 $auto$simplemap.cc:126:simplemap_reduce$4341 $auto$simplemap.cc:126:simplemap_reduce$4338 $auto$simplemap.cc:126:simplemap_reduce$4051 $auto$simplemap.cc:126:simplemap_reduce$4047 $auto$simplemap.cc:38:simplemap_not$20171 $auto$ff.cc:266:slice$3569 $auto$ff.cc:479:convert_ce_over_srst$21648 $auto$simplemap.cc:126:simplemap_reduce$4254 Found 8 SCCs in module top. Found 8 SCCs. 23.42.30. Executing ABC9_OPS pass (helper functions for ABC9). 23.42.31. Executing PROC pass (convert processes to netlists). 23.42.31.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 23.42.31.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 23.42.31.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 23.42.31.4. Executing PROC_INIT pass (extract init attributes). 23.42.31.5. Executing PROC_ARST pass (detect async resets in processes). 23.42.31.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 23.42.31.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 23.42.31.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.42.31.9. Executing PROC_DFF pass (convert process syncs to FFs). 23.42.31.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.42.31.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 23.42.31.12. Executing OPT_EXPR pass (perform const folding). 23.42.32. Executing TECHMAP pass (map to technology primitives). 23.42.32.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 23.42.32.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~212 debug messages> 23.42.33. Executing OPT pass (performing simple optimizations). 23.42.33.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4. Optimizing module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4. Optimizing module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4. Optimizing module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4. Optimizing module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4. Optimizing module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4. Optimizing module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4. Optimizing module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4. Optimizing module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4. Optimizing module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4. Optimizing module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4. Optimizing module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4. Optimizing module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4. Optimizing module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4. Optimizing module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4. Optimizing module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4. Optimizing module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4. Optimizing module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4. Optimizing module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4. Optimizing module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4. Optimizing module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4. Optimizing module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4. Optimizing module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4. Optimizing module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4. 23.42.33.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4'. Removed a total of 0 cells. 23.42.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 23.42.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4. Optimizing cells in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4. Optimizing cells in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4. Optimizing cells in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4. Optimizing cells in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4. Optimizing cells in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4. Optimizing cells in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4. Optimizing cells in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4. Optimizing cells in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4. Optimizing cells in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4. Optimizing cells in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4. Optimizing cells in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4. Optimizing cells in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4. Optimizing cells in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4. Optimizing cells in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4. Optimizing cells in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4. Optimizing cells in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4. Optimizing cells in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4. Optimizing cells in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4. Optimizing cells in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4. Optimizing cells in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4. Optimizing cells in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4. Optimizing cells in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4. Optimizing cells in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4. Performed a total of 0 changes. 23.42.33.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4'. Removed a total of 0 cells. 23.42.33.6. Executing OPT_DFF pass (perform DFF optimizations). 23.42.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.. 23.42.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4. Optimizing module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4. Optimizing module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4. Optimizing module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4. Optimizing module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4. Optimizing module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4. Optimizing module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4. Optimizing module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4. Optimizing module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4. Optimizing module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4. Optimizing module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4. Optimizing module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4. Optimizing module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4. Optimizing module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4. Optimizing module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4. Optimizing module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4. Optimizing module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4. Optimizing module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4. Optimizing module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4. Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4. Optimizing module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4. Optimizing module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4. Optimizing module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4. 23.42.33.9. Finished OPT passes. (There is nothing left to do.) 23.42.34. Executing TECHMAP pass (map to technology primitives). 23.42.34.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 23.42.34.2. Continuing TECHMAP pass. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4 for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4. Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4 for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4. Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4 for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4. Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4 for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4. Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4 for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4. Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4 for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4. Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4 for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4. Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4 for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4. Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4 for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4. Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4 for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4. Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4 for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4. Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4 for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4. Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4 for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4. Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4 for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4. Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4 for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4. Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4 for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4. Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4 for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4. Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4 for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4. Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4 for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4. Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4 for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4. Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4 for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4. Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4 for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4. Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4 for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4. Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4 for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~320 debug messages> 23.42.35. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 23.42.36. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 23.42.37. Executing ABC9_OPS pass (helper functions for ABC9). 23.42.38. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 23.42.39. Executing TECHMAP pass (map to technology primitives). 23.42.39.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 23.42.39.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $xor. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~251 debug messages> 23.42.40. Executing OPT pass (performing simple optimizations). 23.42.40.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~18 debug messages> 23.42.40.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 23.42.40.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 23.42.40.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 23.42.40.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 23.42.40.6. Executing OPT_DFF pass (perform DFF optimizations). 23.42.40.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 23.42.40.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 23.42.40.9. Rerunning OPT passes. (Maybe there is more to do..) 23.42.40.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 23.42.40.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 23.42.40.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 23.42.40.13. Executing OPT_DFF pass (perform DFF optimizations). 23.42.40.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 23.42.40.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 23.42.40.16. Finished OPT passes. (There is nothing left to do.) 23.42.41. Executing AIGMAP pass (map logic to AIG). Module top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 23.42.42. Executing AIGMAP pass (map logic to AIG). Module top: replaced 3998 cells with 23957 new cells, skipped 3342 cells. replaced 3 cell types: 1343 $_OR_ 94 $_XOR_ 2561 $_MUX_ not replaced 59 cell types: 30 $scopeinfo 362 $_NOT_ 1257 $_AND_ 6 $_TBUF_ 1 $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4 1 $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4 1 $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4 710 TRELLIS_FF 1 $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4 1 $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4 1 $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4 1 $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4 1 $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4 1 $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4 1 $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4 1 $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4 1 $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4 1 $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4 1 $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4 1 $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4 252 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 1 $__ABC9_SCC_BREAKER 1 $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4 1 $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp 16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4 16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 1 $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4 1 $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4 1 $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4 1 $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4 1 $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4 1 $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4 1 $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4 1 $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp 252 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp 392 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 23.42.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 23.42.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 23.42.42.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 10565 AND gates and 30473 wires from module `top' to a netlist network with 1895 inputs and 741 outputs. 23.42.42.4. Executing ABC9_EXE pass (technology mapping using ABC9). 23.42.42.5. Executing ABC9. Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 1895/ 741 and = 9156 lev = 46 (5.14) mem = 0.27 MB box = 684 bb = 292 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 1895/ 741 and = 12173 lev = 62 (3.12) mem = 0.30 MB ch = 1330 box = 637 bb = 292 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 60. Obj = 140. Set = 636. CutMin = no ABC: Node = 12173. Ch = 1193. Total mem = 3.34 MB. Peak cut mem = 0.28 MB. ABC: P: Del = 6973.00. Ar = 11366.0. Edge = 14041. Cut = 172537. T = 0.04 sec ABC: P: Del = 6855.00. Ar = 11639.0. Edge = 14120. Cut = 170777. T = 0.04 sec ABC: P: Del = 6855.00. Ar = 6813.0. Edge = 12881. Cut = 362829. T = 0.08 sec ABC: F: Del = 6855.00. Ar = 4616.0. Edge = 11399. Cut = 333682. T = 0.08 sec ABC: A: Del = 6855.00. Ar = 4132.0. Edge = 10153. Cut = 294417. T = 0.11 sec ABC: A: Del = 6855.00. Ar = 4089.0. Edge = 10089. Cut = 308287. T = 0.12 sec ABC: Total time = 0.48 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 1895/ 741 and = 8617 lev = 39 (3.34) mem = 0.26 MB box = 637 bb = 292 ABC: Mapping (K=7) : lut = 2553 edge = 9987 lev = 14 (1.41) levB = 41 mem = 0.13 MB ABC: LUT = 2553 : 2=240 9.4 % 3=638 25.0 % 4=1120 43.9 % 5=344 13.5 % 6=84 3.3 % 7=127 5.0 % Ave = 3.91 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 5.77 seconds, total: 5.77 seconds 23.42.42.6. Executing AIGER frontend. <suppressed ~5331 debug messages> Removed 11873 unused cells and 23611 unused wires. 23.42.42.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 2578 ABC RESULTS: $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells: 16 ABC RESULTS: $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 252 ABC RESULTS: $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 345 ABC RESULTS: input signals: 337 ABC RESULTS: output signals: 131 Removing temp directory. 23.42.43. Executing TECHMAP pass (map to technology primitives). 23.42.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 23.42.43.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4 for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4. Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4 for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4. Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4 for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4. Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4 for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4. Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4 for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4. Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4 for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4. Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4 for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4. Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4 for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4. Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4 for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4. Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4 for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4. Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4 for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4. Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4 for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4. Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4 for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4. Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4 for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4. Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4 for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4. Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4 for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4. Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4 for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4. Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4 for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4. Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4 for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4. Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4 for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4. Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4 for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4. Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4 for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4. Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4 for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4. Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4 for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4. Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001000 for cells of type $__ABC9_SCC_BREAKER. No more expansions possible. <suppressed ~999 debug messages> Removed 326 unused cells and 36918 unused wires. 23.43. Executing TECHMAP pass (map to technology primitives). 23.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 23.43.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut. Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod$ce44877a8aba311086973ef3ef648b154684306e\$lut for cells of type $lut. Using template $paramod$f28a4401e00366386f5c9da01093cb438d2ef37a\$lut for cells of type $lut. Using template $paramod$173257c402a3003de28bff8c2a49d358e5f4004c\$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut. Using template $paramod$2c1875de701f39453798b76f5b327fe456cc0991\$lut for cells of type $lut. Using template $paramod$f28c2e49975958241d4d835ef97e799ed72256e5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$23ba03b3f106a8b0f20f18bfebd862b419996ddc\$lut for cells of type $lut. Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut. Using template $paramod$394086530b97e2ede4325cfef07483589916f736\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod$9c6e6a10ea00e5b0682f6243b802d7839a398197\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod$b18a3edb490ff3a49fefc94182a05f36efbdbba2\$lut for cells of type $lut. Using template $paramod$db8547c0ce3f404162c765a55df5db805b4e10bc\$lut for cells of type $lut. Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6\$lut for cells of type $lut. Using template $paramod$2e6f7636c4430e71acfafacf89034290c19a68d2\$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut. Using template $paramod$73168779d124d0e86f3f4da4f351086f6646bb40\$lut for cells of type $lut. Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut. Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut. Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut. Using template $paramod$38400b76de2b00d7d5f8f09de118b82fd1b8be0a\$lut for cells of type $lut. Using template $paramod$48f2db66c872c1f64faeb797c1719c912a15a86f\$lut for cells of type $lut. Using template $paramod$08466811901d5e03ed77c75ae1ee4f324a7c22b7\$lut for cells of type $lut. Using template $paramod$35e780f9333f3666b86f6bdeb5e6c5f65477f87e\$lut for cells of type $lut. Using template $paramod$c19ac226b2328a9dc00b76bc0a6d1e025c6f4fca\$lut for cells of type $lut. Using template $paramod$1df6d41de86e48fa0e114cfe35ac61195abc3952\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$4e45a60feb8bbe3cabd280417c9ffbefad6f6ef3\$lut for cells of type $lut. Using template $paramod$bed770a996b91d26bd8ec11fab40ed5b998c6937\$lut for cells of type $lut. Using template $paramod$b2b8f14c1dc45737f0261c4484079d734f30d41f\$lut for cells of type $lut. Using template $paramod$05402c79be82cc63a2eaed19f98c2af9df54d241\$lut for cells of type $lut. Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut. Using template $paramod$d7a87ca2ecbda1d431eb014d7af4b3bc1067b28d\$lut for cells of type $lut. Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut. Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut. Using template $paramod$b97ff285770a798ba31d840db2ce52fdc36910ae\$lut for cells of type $lut. Using template $paramod$a8f200f2806e23893fd75a1574871ecd897f762e\$lut for cells of type $lut. Using template $paramod$b2b362fa866354d5936edc937d825ffc48772447\$lut for cells of type $lut. Using template $paramod$3cc80e2a63856e1f46075e358d1c072c35cc4ca8\$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. Using template $paramod$bd860769e6801c50637ab5dc92ce390296b4c30f\$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$e5274c96f8b44566b2d73eeb1cf5954f7e7f6ecd\$lut for cells of type $lut. Using template $paramod$5c3294d2efb88caf0474e72690e5c12ab871a3e8\$lut for cells of type $lut. Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut. Using template $paramod$d54d0e440c49fc9214ad93b5a7a39944cc09a889\$lut for cells of type $lut. Using template $paramod$454e704f56eefdc3d304504657b4b36f6ea90b49\$lut for cells of type $lut. Using template $paramod$130ffa84d8c0712333eceff6854084179663a049\$lut for cells of type $lut. Using template $paramod$ee3ba3939f6ccdb74bf420a252d58cdb86511937\$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut. Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. Using template $paramod$be95f3a2132281eadd1adcfe6229e43dbc3353c9\$lut for cells of type $lut. Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut. Using template $paramod$26d876869d6ab003366d0470e095daef2ccfcbd7\$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. Using template $paramod$b8113752b08bd47f69a1c8c2bca1cfb157e800c9\$lut for cells of type $lut. Using template $paramod$8a53c8ed770d5cdf15616910b18b79f747ce75f2\$lut for cells of type $lut. Using template $paramod$f62bf7b9bf368c5a044dd284e6192cdfb023ea0f\$lut for cells of type $lut. Using template $paramod$37bac9dbfeca7057c37e5fd5c0af3364f646bd96\$lut for cells of type $lut. Using template $paramod$f672f1e5ea7eaf40630014635549af40fc023a51\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. Using template $paramod$6fc23ce09f2013cb9de2228dbcdda21841008f92\$lut for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut. Using template $paramod$fbd55d1b12935a22902cde46a0a7b6e309d6aa42\$lut for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$a29dc9226a883358910d3758606f48686bda2689\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$f1dc124cf9ada1441102b500edee2ce97246bab5\$lut for cells of type $lut. Using template $paramod$47a326ee296feaca60c97add5a2f7670de259bd9\$lut for cells of type $lut. Using template $paramod$e0a16b39d62021fbd2d1c105eda1b9c3b86f8b30\$lut for cells of type $lut. Using template $paramod$8833253c105c1f3ff9a03a20302d6d0a2f4d9c5b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$4b7a2575a604aa21eec6378b6833292a7c6978f8\$lut for cells of type $lut. Using template $paramod$3416dacc8eaab1f89b3d6b7398df3da766d29ef2\$lut for cells of type $lut. Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut. Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut. Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$aaaf4d53e5623317f7cfb17b8590e4ed662ebe75\$lut for cells of type $lut. Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$3ee26675fdb86c62f9449255b242f36533c51cab\$lut for cells of type $lut. Using template $paramod$4a4e8242f8f2e0e44388e42a12a5ef5e2b8bb93f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. Using template $paramod$70a934594406e8042bf2854c778fef542ef3ea5f\$lut for cells of type $lut. Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod$0331e023d83b8009e60defb446ce9fa640b122c7\$lut for cells of type $lut. Using template $paramod$682dcf7a44e09cdf417bc55247ac658426f4c8e6\$lut for cells of type $lut. Using template $paramod$f20ce4917fd5b3c1bb5c623666c4e99ee36747d1\$lut for cells of type $lut. Using template $paramod$a81cf453a316218febe7a33c0cf3157f69dfa7dc\$lut for cells of type $lut. Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut. Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut. Using template $paramod$4c5119bb88a973ab4f4242c30fcba8815107791b\$lut for cells of type $lut. Using template $paramod$052ca015f1400ebf950f85d5f181f7a5865c336c\$lut for cells of type $lut. Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod$ea9f0804ffa1047d479d3e00429394419ff5856b\$lut for cells of type $lut. Using template $paramod$4db3f0d067a6794efd5979ea33ffc0ce06e2e75c\$lut for cells of type $lut. Using template $paramod$a05170b3f2d3fcb0bf88d37e810984e864962880\$lut for cells of type $lut. Using template $paramod$de07eb062963514b9c819aacc3e74a1253bffd53\$lut for cells of type $lut. Using template $paramod$60b99ddfae8ffcebbb1fe7f9e676a60f7472edd5\$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut. Using template $paramod$42196ec919ef6d750f498dc9bf84b2fe077d555c\$lut for cells of type $lut. Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut. Using template $paramod$bc79ab600eab28cc7a77ef316f89478e951888a7\$lut for cells of type $lut. Using template $paramod$99bea6b1a6bfc821c80186f7c0bda101c86a5f38\$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut. Using template $paramod$791ae37bef671b724edae9f13d094dc39cd7c8cb\$lut for cells of type $lut. Using template $paramod$4b544f91022bca4281a618411346553c7c590f28\$lut for cells of type $lut. Using template $paramod$ef1cc14162296fd4d0d07385991da6aec0946444\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. Using template $paramod$e234b33fd72932ba3f0d727e277c697708f63208\$lut for cells of type $lut. Using template $paramod$77b67ef20c955093353b18505577135db4a47988\$lut for cells of type $lut. Using template $paramod$f35f11a6ceaf16b1d14847945e42ee9bd315e95e\$lut for cells of type $lut. Using template $paramod$d08ae3e2fee668f1a68bd32fd012d46d229cb782\$lut for cells of type $lut. Using template $paramod$df3b65132f7020afafd5e2001ca04b29f12adcb4\$lut for cells of type $lut. Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut. Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut. Using template $paramod$81f38dbe34c0131668a5f4192c3c2c07e8338073\$lut for cells of type $lut. Using template $paramod$31f64b4b2cb5d8113d9a1455af902b3edbe63394\$lut for cells of type $lut. Using template $paramod$52acd744af558b1acd7f06b0e1d721506b042b9b\$lut for cells of type $lut. Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut. Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. Using template $paramod$633ae299df262467973f925d88826d85d4a12fb4\$lut for cells of type $lut. Using template $paramod$723be7177967d6866729df0ff463a602326a012e\$lut for cells of type $lut. Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut. Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut. Using template $paramod$af01034afe1bdbc87587d263805971d96e724ed7\$lut for cells of type $lut. Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut. Using template $paramod$2013022fd02779c591c90c3a35efff5a182a577a\$lut for cells of type $lut. Using template $paramod$9b444505f3a8d856cee3b7ca9d0a263c9da4fb6e\$lut for cells of type $lut. Using template $paramod$2e0fd651ab536ddf2afd30af26b1a2532281e83a\$lut for cells of type $lut. Using template $paramod$1e997caf89fb4d457c9ce250ca544f3e1d060a89\$lut for cells of type $lut. Using template $paramod$ec77ef2f39e0c5347eaada9711f26fca6a276050\$lut for cells of type $lut. Using template $paramod$a1461d2dce432aab43aa5e3a52594fb039138a21\$lut for cells of type $lut. Using template $paramod$51e48538280474c9f69a3d6951615d32243ae75c\$lut for cells of type $lut. Using template $paramod$55405c184723e0c981beae197deafc4b247b3004\$lut for cells of type $lut. Using template $paramod$fe0ec6cf52a74b8e9115c7ff11adb77b1122b4e4\$lut for cells of type $lut. Using template $paramod$12428c4217e00e6257ac0074a74f30fd71809836\$lut for cells of type $lut. Using template $paramod$7fc325150916e09e21db63cc9672b99a89ef9301\$lut for cells of type $lut. Using template $paramod$050221686252202c3dcb014324b7b753c760a3f5\$lut for cells of type $lut. Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut. Using template $paramod$15efa44280f2a77bf023b68f95d9df5681d9dd99\$lut for cells of type $lut. Using template $paramod$f405ee362848dd1a47c58160f854302f6ecf95ff\$lut for cells of type $lut. Using template $paramod$44c0fe996e6f3f4ba8bae2e194245aa82c30fa47\$lut for cells of type $lut. Using template $paramod$c07d61aaf1d93e15249de987e8fd0ca391dbd52a\$lut for cells of type $lut. Using template $paramod$f6205ea4d16154fcc0de4d21dff0bd55a57f1ba0\$lut for cells of type $lut. Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut. Using template $paramod$1ae2b86b41d612949835304cb76e044b333c87cd\$lut for cells of type $lut. Using template $paramod$924b39a5781143b3d97abceead32dfebbce1809b\$lut for cells of type $lut. Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut. Using template $paramod$e42911d5b4783f893e9fda29cce43782c36909b8\$lut for cells of type $lut. Using template $paramod$3e14605ffdc6e1eed6147205c511e169125adea2\$lut for cells of type $lut. Using template $paramod$89ca3723ebb4dfdb3c4024f3f04b784a3e88f188\$lut for cells of type $lut. Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut. Using template $paramod$eaea85d27cc0950ed001348e061727a194f5cf9c\$lut for cells of type $lut. Using template $paramod$3f9a3800e34bd795630a4eaf44b2e1d4a7f48a74\$lut for cells of type $lut. Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut. Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut. Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut. Using template $paramod$d9922e15eb5da1acc26e937540cc16b16c2ad42c\$lut for cells of type $lut. Using template $paramod$9ad365b45077187469ed80134c40f64c286b5b07\$lut for cells of type $lut. Using template $paramod$0ae4e6ad7e07e634c7166b50dfaeb6b360dcb05d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut. Using template $paramod$492eaf0a536adc9996cc1bdb46e9f2144885c0ab\$lut for cells of type $lut. Using template $paramod$18368a3da11a7221c7fb674ec80ee0d0bd64b883\$lut for cells of type $lut. Using template $paramod$82a00bf0f959a345aaec45c197de61b70ee9c703\$lut for cells of type $lut. Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut. Using template $paramod$653ed1fca2cbea6092fc92115114dddd9158d22d\$lut for cells of type $lut. Using template $paramod$21a1ca6f9f5c15b304c8c46ce6cda8b91e063cf1\$lut for cells of type $lut. Using template $paramod$de7ed7b302880cc6d7708c8eac1634f4008cc075\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut. Using template $paramod$77c2a0573790d304ab2299da6d598e8d2e184867\$lut for cells of type $lut. Using template $paramod$f52ac008435695f9b4157529669c6afa0327a863\$lut for cells of type $lut. Using template $paramod$7a9692718574a8ca8397cd6df9507b9a647f0b4e\$lut for cells of type $lut. Using template $paramod$1ec3fb8fd1fa98216cb96b4422de32c4ba5f6c9c\$lut for cells of type $lut. Using template $paramod$becf4ae4f5301462ee316851950c81d66baf3e53\$lut for cells of type $lut. Using template $paramod$5f05aeca11247703def93cf31ef2edb8c4adec56\$lut for cells of type $lut. Using template $paramod$a6ef2a845efd4ff0d96bc4fd2f06cc3516fa63ff\$lut for cells of type $lut. Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut. Using template $paramod$0f891ee84fac320f890afcf9c994c53a24cd31f9\$lut for cells of type $lut. Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut. Using template $paramod$6e3a03c79073e44642e8ed2dab4ee82dfd40dfba\$lut for cells of type $lut. Using template $paramod$7f53f4c6ab3129f897ce065d15ceca6db3bb9c00\$lut for cells of type $lut. Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut. Using template $paramod$8504d86f1088c038cefc453338e6ce07c755faf4\$lut for cells of type $lut. Using template $paramod$c4a57735f68dea791563158e71e652a9ee523b9b\$lut for cells of type $lut. Using template $paramod$985f4a39445dc8a19b2aa35fe53dc5ac282e20d6\$lut for cells of type $lut. Using template $paramod$d76cdb06be4cd57b04868d1769cbce929fcbb61a\$lut for cells of type $lut. Using template $paramod$81674e5ce0a740bd3df4bc9aa2a0d98f67dc9361\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$d5b95ef1c89d834e3e72966caf0c9ff97c5cfa95\$lut for cells of type $lut. Using template $paramod$ad72f449a3fc25ae204b59a66f1bc742c88a461d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110101 for cells of type $lut. Using template $paramod$2b5c74206b2232d69cebc74aeb36a11007fc1a0c\$lut for cells of type $lut. Using template $paramod$77100cb13ff33cd8aef867af4059c7b810c791c9\$lut for cells of type $lut. Using template $paramod$07b1b12ce0305f55108770e958fd02caedfebdf8\$lut for cells of type $lut. Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut. Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut. Using template $paramod$e8ba44e4a3ee29c32776f6151b0293be3e5fa416\$lut for cells of type $lut. Using template $paramod$13a79e008061312bbb4dd073f52bfcaecdaec07e\$lut for cells of type $lut. Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut. Using template $paramod$10d3f5c358068baea94eb7a863ad4a61dadd7a9a\$lut for cells of type $lut. Using template $paramod$feac1814a13647ff95d85e23385825c648d6c2ee\$lut for cells of type $lut. Using template $paramod$3751cff910103888107374559f35d9f1f2f94946\$lut for cells of type $lut. Using template $paramod$b8893f9056e7dfd09e5aac0f9c12c307b0fa7a63\$lut for cells of type $lut. Using template $paramod$f042de7342b2b10a6806821f7b41d4a327cbae6b\$lut for cells of type $lut. Using template $paramod$f25cfeb07793f4c9b87758158af8df76472138cf\$lut for cells of type $lut. Using template $paramod$3c5d67806b5dfffe98cf256e15d237955fb1756b\$lut for cells of type $lut. Using template $paramod$6de442abe246ff8c0692702d40d84ce1c07479d9\$lut for cells of type $lut. Using template $paramod$dcf80d2c2ec10d6ba1e23d820880a8149a8ee2d7\$lut for cells of type $lut. Using template $paramod$793fc28cf61120083daef76d0ad6adfe307204e0\$lut for cells of type $lut. Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut. Using template $paramod$cd993efb9e63a4c10845b014d76174a67faa06cd\$lut for cells of type $lut. Using template $paramod$e4028dbef8bf09e426c35a5ead7da0bbf24c7433\$lut for cells of type $lut. Using template $paramod$18b66a2dc66be2a0d172c3d50ba03932f5924e22\$lut for cells of type $lut. Using template $paramod$b8f75cf9c6c06c079da053f4aa60c4d5363c32b3\$lut for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut. Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod$40f50322426372d948aaadc2f14dc77fbf5a9200\$lut for cells of type $lut. Using template $paramod$bf5be42a5629888c2c70a1c940021ec3b18b1512\$lut for cells of type $lut. Using template $paramod$758d9e8729b283bb3651b0fa835584bea2e26299\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568\$lut for cells of type $lut. Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut. Using template $paramod$5c36a508e8885449eeca65fa0c02b7154f6a3130\$lut for cells of type $lut. Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut. Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut. Using template $paramod$f2d22947d144afc97fbfe77dd7b67614b454e6ce\$lut for cells of type $lut. Using template $paramod$7f0d2c58f8a8571de97c933bf19741574ee6472d\$lut for cells of type $lut. Using template $paramod$9616fecedc1a6ce839b990a3156875e06908d6fa\$lut for cells of type $lut. Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. Using template $paramod$973394a6f8c13a435c2fa950b3fc699e041032a1\$lut for cells of type $lut. Using template $paramod$1608964cd44e926c22f8f8ce1065b9f3472e6f6d\$lut for cells of type $lut. Using template $paramod$a5e8c1e7cd3da97a7753a6d3982fd60e35cd98df\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut. Using template $paramod$bf00427ade60df6ecbee879d4a17f97643fe237b\$lut for cells of type $lut. Using template $paramod$68fccd364235f9e63176db909dbae027db36e86a\$lut for cells of type $lut. Using template $paramod$7e5d3318550e2db43c19acc270faf504f594803b\$lut for cells of type $lut. Using template $paramod$895777c5ed324b274bcbda58a212301bfcfc729d\$lut for cells of type $lut. Using template $paramod$2e275b44ade5fad054ab9e2853e9673aaf704694\$lut for cells of type $lut. Using template $paramod$60a7cf2b851adabf56be742ab40fdf6b156a8f30\$lut for cells of type $lut. Using template $paramod$c4af7f2c88559dab5f19c52110f1d82cb05f465f\$lut for cells of type $lut. Using template $paramod$f26a55a3b5e6a14b750ec4c5c51364fd22cd4d5e\$lut for cells of type $lut. Using template $paramod$287f1241f3338cac99fcc60a61582c4947886932\$lut for cells of type $lut. Using template $paramod$aff1aa3071658a0de88f8bbb51c45874f2d1e44a\$lut for cells of type $lut. Using template $paramod$88a106be73851c7a5d1740739afdb4dbd65330dc\$lut for cells of type $lut. Using template $paramod$ae94d50df378ea92eca5d18fa8d45dda42518ea2\$lut for cells of type $lut. Using template $paramod$b5d2ddcf66f5237fb7b81882f14baf21a2e8ebb7\$lut for cells of type $lut. Using template $paramod$0d23d73cbd5ac178376b6145e5d570298e605fc0\$lut for cells of type $lut. Using template $paramod$196d71d697f29238f64d04f3867f611ca5c291b5\$lut for cells of type $lut. Using template $paramod$4ccd54f46aa2a362171cc25f5c2a03bc73bbd95e\$lut for cells of type $lut. Using template $paramod$41b777a122fa6162fe05e453fac63a5bd726825e\$lut for cells of type $lut. Using template $paramod$4d1533dad4814c51bde53f9a378e78c03dd47a9f\$lut for cells of type $lut. Using template $paramod$4570d1492902d4fceaa4514a05982f400175bf65\$lut for cells of type $lut. Using template $paramod$a2a239e169b719e301098d0e44b37605e4e45297\$lut for cells of type $lut. Using template $paramod$486d1e1cdd0727e7000b2a5997534189586e24cf\$lut for cells of type $lut. Using template $paramod$ea718eeb98c809ba5abcd0d342cca6190319badd\$lut for cells of type $lut. Using template $paramod$1f2c31d6f9d5076de53559ae8a054e1c27e3a8e2\$lut for cells of type $lut. Using template $paramod$f109125ffdede8321ac65719b1066c75ff1eaef0\$lut for cells of type $lut. Using template $paramod$1ea99bfd7dc3a15adef0012a32509f257a7e366a\$lut for cells of type $lut. Using template $paramod$22d2c572074146d40a2bf5a9d2fbc5175093bd0d\$lut for cells of type $lut. Using template $paramod$e2d4399e1e149b2bd3c04b32fc0d847bb8cdd6d6\$lut for cells of type $lut. Using template $paramod$c7446aefbe8323b51fdaeabb1b55f9c218552255\$lut for cells of type $lut. Using template $paramod$9e0d5e3cbbbadb2b139aaae0b912cff38011856c\$lut for cells of type $lut. Using template $paramod$f2ffc9085000a0a9f052860f5ccb192550bf9aac\$lut for cells of type $lut. Using template $paramod$bb59da4933702bb82ef3226e214fb972ba5089dd\$lut for cells of type $lut. Using template $paramod$b337e3cce6217ac730d7f74b0fc4a364dd64484c\$lut for cells of type $lut. Using template $paramod$c362ad8dedc7d166ed978091aca319ab1e81a2d4\$lut for cells of type $lut. Using template $paramod$3189f5673222f9145c406d1a41a5d157cb8381d2\$lut for cells of type $lut. Using template $paramod$38a09d61b4208a328f326f67c48fcb92f664b999\$lut for cells of type $lut. Using template $paramod$fbace1c5af8b8efd1c625bd9d47d8b080aa709a4\$lut for cells of type $lut. Using template $paramod$88e41ea94449dd2f974e4d7486dbbcdee83e0a6d\$lut for cells of type $lut. Using template $paramod$b061f1d14659387aa4588cdc98a0dd8a3d7e2815\$lut for cells of type $lut. Using template $paramod$455e7f3b92b02317f156a783bf4d59a070171fd2\$lut for cells of type $lut. Using template $paramod$0b411b7d1762b79400c7b7e65303823d9a001f59\$lut for cells of type $lut. Using template $paramod$cc173bb48f638125313eee2d9b59be0a55452992\$lut for cells of type $lut. Using template $paramod$f52d31369a575902b7f4718aa6ea19045c36b670\$lut for cells of type $lut. Using template $paramod$7f88ae8b0ca78f7b736f446522956805c49fb79f\$lut for cells of type $lut. Using template $paramod$ccd0ca33cca88a5f9dd0380c0483d68a8f2a8165\$lut for cells of type $lut. Using template $paramod$83dc89e4276b6a382277886e110ab9c65ad63765\$lut for cells of type $lut. Using template $paramod$8c11a155773d2e4aba9b1022fc059160b55313e8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod$b52a83b20478a9d248bb9977fedae09592bb3a53\$lut for cells of type $lut. Using template $paramod$5f62258baf8e9e81bbe6ab71cd1b06a1c2737273\$lut for cells of type $lut. Using template $paramod$5e9f4601ba49c93822a1807d80c28fa0610b6873\$lut for cells of type $lut. Using template $paramod$5beb8e7bee421403ff620b1057283d148224a974\$lut for cells of type $lut. Using template $paramod$72148f3545efac6f48701d6c21ae5eeb7a5f865b\$lut for cells of type $lut. Using template $paramod$b2b0ef0fd68f407fde72a1ece09e1ea9a689265f\$lut for cells of type $lut. Using template $paramod$059968be1ef12c596bb5d360a749040b6777bf4a\$lut for cells of type $lut. Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut. Using template $paramod$a5dd9ee10fc2202a29791f7d68d4afcce241aee5\$lut for cells of type $lut. Using template $paramod$cecd657bbcbef802318d4d20bbf444609afc9bf4\$lut for cells of type $lut. Using template $paramod$4832df48ba2043723334bbfa7a32d426d800dbae\$lut for cells of type $lut. Using template $paramod$fdb7d2f78b1b1d86177579c82e917e4e8af6f77d\$lut for cells of type $lut. Using template $paramod$d80c9b99dacb354fa564a6fcc23ca30753bf6623\$lut for cells of type $lut. Using template $paramod$9e1755e3954600257bb9b9ab192e2c0243b0f35a\$lut for cells of type $lut. Using template $paramod$d06a69a5fbd7b853c2dd102d7aeb64b2bdc9fabe\$lut for cells of type $lut. Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut. Using template $paramod$023d9d13c9ddd8e6cbda8fa49753038bbbacbfa4\$lut for cells of type $lut. Using template $paramod$ec6bb3db7c80c492ce6110718f99328a4ab7f019\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut. Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut. Using template $paramod$72999a7ffa547571d7240ef55378d6675343dc1c\$lut for cells of type $lut. Using template $paramod$a5c444d04c5a634d51f946f50a00eb23a3758ff5\$lut for cells of type $lut. Using template $paramod$d6e6d411b16e057eae3ca70523bb1b2722704525\$lut for cells of type $lut. Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. Using template $paramod$72acf8dc31a7f123b60145f2655fe8a137aa68d6\$lut for cells of type $lut. Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut. Using template $paramod$474e736e3c2be1c5c72ef98199ca0c7937f8ee13\$lut for cells of type $lut. Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut. Using template $paramod$ef40c88c17fd9dafc15b58ac013920ba3ecb927b\$lut for cells of type $lut. Using template $paramod$7ce7683c590e6b9a2ebd543a8f468551f1af24cf\$lut for cells of type $lut. Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut. Using template $paramod$240e171f8bae87a2fe4bee672a3055fa35afe320\$lut for cells of type $lut. Using template $paramod$00da6ee835349555028231ae835c9b401a5c1dee\$lut for cells of type $lut. Using template $paramod$8075729953f49b6cb1b4d863b2fb20da9818d304\$lut for cells of type $lut. Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut. Using template $paramod$ba4b1c9b57f942a38af35848615a2f06189d3bfe\$lut for cells of type $lut. Using template $paramod$aaf2ef5cf75121bbc717334d538c8a2de3e26e03\$lut for cells of type $lut. Using template $paramod$3e7360796ac608ec9e808c79d6b1f4bc43c69d15\$lut for cells of type $lut. Using template $paramod$4f6ef5838c139220e91b3d9534b74e9d61193cac\$lut for cells of type $lut. Using template $paramod$d657361b360a152b4018b0283df55e5626273e96\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$899a7d400185b4f778bea81a50f62c95a0b19d77\$lut for cells of type $lut. Using template $paramod$263b613d26e59958a0d1e36903a2016b82f2f359\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut. Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut. Using template $paramod$95e069858cb2e42f0b23620675213cfe73b02fff\$lut for cells of type $lut. Using template $paramod$ac977fdb827743bc5fe009760f4eb846eab5907d\$lut for cells of type $lut. Using template $paramod$8b24fb07373c4ee224b517e500c9710a464b35dc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$717dae7a4b4d98fb824634d546043d165e3cf20a\$lut for cells of type $lut. Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$ead66ba22839f96e739c8f1b5a09bc1717b3be02\$lut for cells of type $lut. Using template $paramod$95f9b81027e0efcb4250de73f2fadc287f9fe7c2\$lut for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod$c6126b0dd2c3f19c664e9ac13e1673e0f31255f5\$lut for cells of type $lut. Using template $paramod$0e6f7067c2a44b2e3cbef1e1c87513a6042c22b4\$lut for cells of type $lut. Using template $paramod$0f19b1c588a47c675d00132b243b5e3308ffab5d\$lut for cells of type $lut. Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut. Using template $paramod$5637f6366c0fa622e75f886ee59706323e5fe6fc\$lut for cells of type $lut. Using template $paramod$4d673f44384ebded9d542bceabb0e9271e6f9336\$lut for cells of type $lut. Using template $paramod$71b6d833a4170eede1dcc8409c3fc7460c2df8d9\$lut for cells of type $lut. Using template $paramod$8bbd860b6b6da9423e63d54e024a82fba4a4590c\$lut for cells of type $lut. Using template $paramod$505ca6f83efadae0442899a08af73f5288142a52\$lut for cells of type $lut. No more expansions possible. <suppressed ~8189 debug messages> 23.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73141.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$9142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$8843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$8567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$8567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$8231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$8181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$8181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$8175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$8175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$auto$rtlil.cc:2582:Mux$2614[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7859.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7033.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$5671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$5671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$5671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$5473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$5188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$5063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$4578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$5934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$5908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6801.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$5713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$5800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$4911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$4911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$4126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$4185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$4185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$4146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$4217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$10125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$10135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$10208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$10486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$10655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10831.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10871.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$10934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$10998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$11140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$11170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$11308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$11514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$11902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$11998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$12009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$12016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$12031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$12062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$12079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$12099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$12106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$12117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$12142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$12190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$12206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$12239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$12294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$12301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$4126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73353.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$4190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4585.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$4713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4792.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$4956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$4986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$5958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$5091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5124.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5459.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$5479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$5671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$5693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$5851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$5859.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$5887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$5941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$5984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6253.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$5901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6437.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6544.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6705.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$6969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$6985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$6989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7041.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$5998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7585.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut$aiger73043$7660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$7868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$7973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7977.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$7984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$8192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8239.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$8253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$8567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$8576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$8680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$8713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$73044$lut$aiger73043$8838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$8843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$8850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$8907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$9100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$9134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$9142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$9199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$9624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$aiger73043$9641.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$9933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$auto$fsm_map.cc:170:map_fsm$2123[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut$auto$rtlil.cc:2582:Mux$2614[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$auto$rtlil.cc:2582:Mux$2614[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$73044$lut\SOC.Core.CSR_Unit.csr_write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73133.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$73044$lut$auto$fsm_map.cc:170:map_fsm$2123[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73072.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73089.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$73044$lut$aiger73043$4217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Removed 0 unused cells and 7080 unused wires. 23.45. Executing AUTONAME pass. Renamed 337998 objects in module top (357 iterations). <suppressed ~11889 debug messages> 23.46. Executing HIERARCHY pass (managing design hierarchy). 23.46.1. Analyzing design hierarchy.. Top module: \top 23.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 23.47. Printing statistics. === top === Number of wires: 5495 Number of wire bits: 13414 Number of public wires: 5495 Number of public wire bits: 13414 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 6932 $_TBUF_ 6 $scopeinfo 30 CCU2C 345 L6MUX21 465 LUT4 4064 PFUMX 1020 TRELLIS_DPR16X4 292 TRELLIS_FF 710 23.48. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 23.49. Executing JSON backend. Warnings: 213 unique messages, 214 total End of script. Logfile hash: aecd3ee715, CPU: user 7.38s system 0.08s, MEM: 219.06 MB peak Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) Time spent: 43% 1x abc9_exe (5 sec), 11% 11x techmap (1 sec), ... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (NextPNR) [Pipeline] sh + /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained Info: constraining clock net 'clk' to 25.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 6506/43848 14% Info: logic LUTs: 4064/43848 9% Info: carry LUTs: 690/43848 1% Info: RAM LUTs: 1168/ 5481 21% Info: RAMW LUTs: 584/10962 5% Info: Total DFFs: 710/43848 1% Info: Packing IOs.. Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'. Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'. Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'. Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'. Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'. Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'. Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'. Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'. Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'. Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'. Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 353 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0x1ccf940d Info: Device utilisation: Info: TRELLIS_IO: 18/ 245 7% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 710/43848 1% Info: TRELLIS_COMB: 6602/43848 15% Info: TRELLIS_RAMW: 292/ 5481 5% Info: Placed 18 cells based on constraints. Info: Creating initial analytic placement for 3258 cells, random placement wirelen = 302004. Info: at initial placer iter 0, wirelen = 2826 Info: at initial placer iter 1, wirelen = 2772 Info: at initial placer iter 2, wirelen = 2947 Info: at initial placer iter 3, wirelen = 3051 Info: Running main analytical placer, max placement attempts per cell = 7263766. Info: at iteration #1, type ALL: wirelen solved = 2910, spread = 46464, legal = 46926; time = 0.16s Info: at iteration #2, type ALL: wirelen solved = 5147, spread = 37569, legal = 38181; time = 0.16s Info: at iteration #3, type ALL: wirelen solved = 6636, spread = 37961, legal = 38580; time = 0.16s Info: at iteration #4, type ALL: wirelen solved = 8142, spread = 36985, legal = 37646; time = 0.16s Info: at iteration #5, type ALL: wirelen solved = 9862, spread = 36271, legal = 36980; time = 0.15s Info: at iteration #6, type ALL: wirelen solved = 11402, spread = 32936, legal = 34362; time = 0.15s Info: at iteration #7, type ALL: wirelen solved = 11471, spread = 34759, legal = 35718; time = 0.15s Info: at iteration #8, type ALL: wirelen solved = 12594, spread = 33311, legal = 34239; time = 0.15s Info: at iteration #9, type ALL: wirelen solved = 13327, spread = 30539, legal = 31665; time = 0.15s Info: at iteration #10, type ALL: wirelen solved = 13942, spread = 30390, legal = 31316; time = 0.15s Info: at iteration #11, type ALL: wirelen solved = 15411, spread = 29413, legal = 30190; time = 0.15s Info: at iteration #12, type ALL: wirelen solved = 15362, spread = 28812, legal = 29998; time = 0.15s Info: at iteration #13, type ALL: wirelen solved = 16337, spread = 27486, legal = 28793; time = 0.15s Info: at iteration #14, type ALL: wirelen solved = 16120, spread = 27485, legal = 28602; time = 0.15s Info: at iteration #15, type ALL: wirelen solved = 16177, spread = 27454, legal = 28584; time = 0.15s Info: at iteration #16, type ALL: wirelen solved = 16668, spread = 26789, legal = 28305; time = 0.15s Info: at iteration #17, type ALL: wirelen solved = 16897, spread = 26018, legal = 27422; time = 0.15s Info: at iteration #18, type ALL: wirelen solved = 17089, spread = 24971, legal = 26639; time = 0.15s Info: at iteration #19, type ALL: wirelen solved = 17321, spread = 26169, legal = 27184; time = 0.15s Info: at iteration #20, type ALL: wirelen solved = 18005, spread = 25047, legal = 26132; time = 0.15s Info: at iteration #21, type ALL: wirelen solved = 17281, spread = 25774, legal = 26916; time = 0.15s Info: at iteration #22, type ALL: wirelen solved = 17921, spread = 25576, legal = 26359; time = 0.14s Info: at iteration #23, type ALL: wirelen solved = 18103, spread = 25609, legal = 26749; time = 0.14s Info: at iteration #24, type ALL: wirelen solved = 18146, spread = 25632, legal = 26493; time = 0.14s Info: at iteration #25, type ALL: wirelen solved = 18626, spread = 25664, legal = 26546; time = 0.14s Info: HeAP Placer Time: 5.89s Info: of which solving equations: 3.37s Info: of which spreading cells: 0.49s Info: of which strict legalisation: 0.18s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 5230, wirelen = 26132 Info: at iteration #5: temp = 0.000000, timing cost = 3200, wirelen = 23240 Info: at iteration #10: temp = 0.000000, timing cost = 2904, wirelen = 22548 Info: at iteration #15: temp = 0.000000, timing cost = 3095, wirelen = 22262 Info: at iteration #20: temp = 0.000000, timing cost = 3276, wirelen = 22165 Info: at iteration #23: temp = 0.000000, timing cost = 3182, wirelen = 22146 Info: SA placement time 15.81s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 37.57 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.27 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 9.72 ns Info: Slack histogram: Info: legend: * represents 40 endpoint(s) Info: + represents [1,40) endpoint(s) Info: [ 13385, 14678) |+ Info: [ 14678, 15971) |+ Info: [ 15971, 17264) |+ Info: [ 17264, 18557) |**+ Info: [ 18557, 19850) |********+ Info: [ 19850, 21143) |******+ Info: [ 21143, 22436) |*+ Info: [ 22436, 23729) |***********+ Info: [ 23729, 25022) |*************+ Info: [ 25022, 26315) |********+ Info: [ 26315, 27608) |************************************************************ Info: [ 27608, 28901) |******************************************************+ Info: [ 28901, 30194) |**********+ Info: [ 30194, 31487) |********+ Info: [ 31487, 32780) |****+ Info: [ 32780, 34073) |+ Info: [ 34073, 35366) |*******+ Info: [ 35366, 36659) |**********+ Info: [ 36659, 37952) |****+ Info: [ 37952, 39245) |***+ Info: Checksum: 0x49995df8 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 29421 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 139 860 | 139 860 | 28719| 0.68 0.68| Info: 2000 | 237 1762 | 98 902 | 28015| 0.26 0.94| Info: 3000 | 347 2652 | 110 890 | 27397| 0.26 1.20| Info: 4000 | 513 3486 | 166 834 | 26647| 0.25 1.46| Info: 5000 | 620 4379 | 107 893 | 26108| 0.31 1.77| Info: 6000 | 761 5238 | 141 859 | 25457| 0.26 2.03| Info: 7000 | 955 6044 | 194 806 | 24886| 0.24 2.27| Info: 8000 | 1175 6824 | 220 780 | 24206| 0.25 2.52| Info: 9000 | 1391 7608 | 216 784 | 23676| 0.23 2.75| Info: 10000 | 1577 8422 | 186 814 | 23289| 0.26 3.01| Info: 11000 | 1770 9229 | 193 807 | 22637| 0.25 3.26| Info: 12000 | 1968 10031 | 198 802 | 21921| 0.24 3.50| Info: 13000 | 2186 10813 | 218 782 | 21219| 0.24 3.74| Info: 14000 | 2359 11640 | 173 827 | 20580| 0.26 4.00| Info: 15000 | 2605 12394 | 246 754 | 19925| 0.29 4.29| Info: 16000 | 2873 13126 | 268 732 | 19267| 0.28 4.57| Info: 17000 | 2965 14034 | 92 908 | 19099| 0.23 4.80| Info: 18000 | 3260 14739 | 295 705 | 18543| 0.25 5.05| Info: 19000 | 3562 15437 | 302 698 | 17941| 0.30 5.35| Info: 20000 | 3871 16128 | 309 691 | 17317| 0.30 5.65| Info: 21000 | 4097 16902 | 226 774 | 16712| 0.28 5.93| Info: 22000 | 4435 17564 | 338 662 | 16206| 0.33 6.26| Info: 23000 | 4745 18254 | 310 690 | 15609| 0.29 6.55| Info: 24000 | 5016 18983 | 271 729 | 14967| 0.29 6.84| Info: 25000 | 5351 19648 | 335 665 | 14553| 0.30 7.14| Info: 26000 | 5777 20222 | 426 574 | 14138| 0.32 7.47| Info: 27000 | 6160 20839 | 383 617 | 13635| 0.31 7.78| Info: 28000 | 6556 21443 | 396 604 | 13150| 0.30 8.08| Info: 29000 | 6870 22129 | 314 686 | 12820| 0.30 8.38| Info: 30000 | 7235 22764 | 365 635 | 12371| 0.32 8.70| Info: 31000 | 7645 23341 | 410 577 | 11915| 0.35 9.04| Info: 32000 | 7997 23946 | 352 605 | 11376| 0.26 9.30| Info: 33000 | 8297 24555 | 300 609 | 10764| 0.24 9.54| Info: 34000 | 8577 25148 | 280 593 | 10118| 0.24 9.78| Info: 35000 | 8868 25705 | 291 557 | 9433| 0.21 9.99| Info: 36000 | 9145 26260 | 277 555 | 8815| 0.24 10.22| Info: 37000 | 9371 26957 | 226 697 | 8165| 0.24 10.46| Info: 38000 | 9633 27636 | 262 679 | 7632| 0.23 10.69| Info: 39000 | 9990 28220 | 357 584 | 7063| 0.27 10.96| Info: 40000 | 10380 28750 | 390 530 | 6498| 0.30 11.26| Info: 41000 | 10669 29404 | 289 654 | 5879| 0.28 11.54| Info: 42000 | 10777 30269 | 108 865 | 5004| 0.16 11.70| Info: 43000 | 10824 31218 | 47 949 | 4080| 0.10 11.80| Info: 44000 | 10838 32195 | 14 977 | 3094| 0.08 11.88| Info: 45000 | 10954 33076 | 116 881 | 2231| 0.16 12.04| Info: 46000 | 11107 33818 | 153 742 | 1396| 0.22 12.26| Info: 47000 | 11182 34623 | 75 805 | 483| 0.19 12.45| Info: 47482 | 11182 34891 | 0 268 | 0| 0.08 12.53| Info: Routing complete. Info: Router1 time 12.53s Info: Checksum: 0x50f00b20 Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q.Q Info: 1.2 1.8 Net SOC.Core.Control_Unit.nextstate_PFUMX_Z_2_C0[0] (23,18) -> (19,18) Info: Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.A Info: Defined in: Info: Risco-5/src/core/control_unit.v:51.11-51.16 Info: 0.2 2.0 Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F Info: 1.5 3.5 Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (19,18) -> (7,18) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 3.7 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.F Info: 1.7 5.4 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1 (7,18) -> (17,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_CCU2C_B1$CCU2_COMB1.B Info: 0.4 5.8 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_CCU2C_B1$CCU2_COMB1.FCO Info: 0.0 5.8 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_CCU2C_B1_COUT (17,19) -> (17,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 5.9 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 5.9 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (17,19) -> (17,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 5.9 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 5.9 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (17,19) -> (17,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.0 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.0 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (17,19) -> (17,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.0 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.0 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (17,19) -> (18,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.1 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.1 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (18,19) -> (18,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.1 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.1 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (18,19) -> (18,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.1 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.1 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (18,19) -> (18,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.1 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.1 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (18,19) -> (18,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.2 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.2 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (18,19) -> (18,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.2 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.2 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (18,19) -> (18,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.3 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.3 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (18,19) -> (18,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.3 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.3 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (18,19) -> (19,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.3 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.3 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (19,19) -> (19,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.3 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.3 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (19,19) -> (19,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.4 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.4 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (19,19) -> (19,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.4 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.4 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (19,19) -> (19,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B1_CCU2C_B1$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.5 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B1_CCU2C_B1$CCU2_COMB0.FCO Info: 0.0 6.5 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B1_CCU2C_B1$CCU2_FCI_INT (19,19) -> (19,19) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B1_CCU2C_B1$CCU2_COMB1.FCI Info: 0.0 6.5 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B1_CCU2C_B1$CCU2_COMB1.FCO Info: 0.0 6.5 Net $nextpnr_CCU2C_35$CIN (19,19) -> (19,19) Info: Sink $nextpnr_CCU2C_35$CCU2_COMB0.FCI Info: 0.4 6.9 Source $nextpnr_CCU2C_35$CCU2_COMB0.F Info: 1.4 8.3 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B1_CCU2C_B1_COUT (19,19) -> (19,30) Info: Sink SOC.Memory.address_LUT4_Z_2.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 8.5 Source SOC.Memory.address_LUT4_Z_2.F Info: 2.6 11.2 Net SOC.slave_address[3] (19,30) -> (32,19) Info: Sink SOC.Memory.memory.0.61$DPRAM_COMB1.B Info: Defined in: Info: Risco-5/src/peripheral/soc.v:22.5-22.18 Info: 0.2 11.4 Source SOC.Memory.memory.0.61$DPRAM_COMB1.F Info: 0.9 12.3 Net SOC.Memory.memory.0.45_DO_2[2] (32,19) -> (31,19) Info: Sink SOC.Memory.memory.0.45_DO_2_LUT4_C.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 12.5 Source SOC.Memory.memory.0.45_DO_2_LUT4_C.F Info: 0.8 13.3 Net SOC.Memory.memory.0.45_DO_2_LUT4_C_Z[3] (31,19) -> (31,19) Info: Sink SOC.Memory.memory.0.109_DO_2_LUT4_C_Z_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 13.6 Source SOC.Memory.memory.0.109_DO_2_LUT4_C_Z_LUT4_Z.F Info: 1.5 15.1 Net SOC.Memory.memory.0.109_DO_2_LUT4_C_Z[3] (31,19) -> (31,25) Info: Sink SOC.Memory.memory.0.165_DO_2_LUT4_C_Z_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.4 15.5 Source SOC.Memory.memory.0.165_DO_2_LUT4_C_Z_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 1.1 16.6 Net SOC.Memory.memory.0.165_DO_2_LUT4_C_Z_LUT4_C_Z[2] (31,25) -> (28,24) Info: Sink SOC.Core.read_data_LUT4_Z_6_D_LUT4_Z.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 16.9 Source SOC.Core.read_data_LUT4_Z_6_D_LUT4_Z.F Info: 0.4 17.3 Net SOC.Core.read_data_LUT4_Z_6_D[3] (28,24) -> (28,24) Info: Sink SOC.Core.read_data_LUT4_Z_6_D_LUT4_D.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 17.5 Source SOC.Core.read_data_LUT4_Z_6_D_LUT4_D.F Info: 2.0 19.6 Net SOC.Core.read_data_LUT4_Z_9_D_LUT4_D_Z[21] (28,24) -> (33,19) Info: Sink SOC.Memory.memory.0.13$RAMW_SLICE.A1 Info: 0.0 19.6 Source SOC.Memory.memory.0.13$RAMW_SLICE.WDO1 Info: 0.1 19.6 Net SOC.Memory.memory.0.13$RAMW_SLICE$conn$WDO1 (33,19) -> (33,19) Info: Sink SOC.Memory.memory.0.13$DPRAM_COMB1.WD Info: 0.0 19.6 Setup SOC.Memory.memory.0.13$DPRAM_COMB1.WD Info: 4.3 ns logic, 15.3 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source gpios[2]$tr_io.O Info: 4.0 4.0 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (16,25) Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_1_LUT4_Z.B Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:7.16-7.21 Info: 0.2 4.2 Source SOC.Uart.RX_FIFO.memory.0.0_DO_1_LUT4_Z.F Info: 0.2 4.4 Net SOC.Uart.RX_FIFO.memory.0.0_DO_1[1] (16,25) -> (16,25) Info: Sink SOC.Core.read_data_LUT4_Z_19.B Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 4.6 Source SOC.Core.read_data_LUT4_Z_19.F Info: 1.2 5.9 Net SOC.read_data[2] (16,25) -> (24,24) Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M Info: Defined in: Info: Risco-5/src/peripheral/soc.v:21.34-21.43 Info: 0.0 5.9 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M Info: 0.5 ns logic, 5.4 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>': Info: curr total Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_29.Q Info: 3.8 4.3 Net SOC.Leds.data[2] (32,18) -> (71,43) Info: Sink led_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 4.6 Source led_LUT4_Z.F Info: 1.7 6.2 Net led[2]$TRELLIS_IO_OUT (71,43) -> (90,44) Info: Sink led[2]$tr_io.I Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:6.22-6.25 Info: 0.8 ns logic, 5.5 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 50.93 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.89 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.22 ns Info: Slack histogram: Info: legend: * represents 38 endpoint(s) Info: + represents [1,38) endpoint(s) Info: [ 20365, 21300) |****+ Info: [ 21300, 22235) |******+ Info: [ 22235, 23170) |*****+ Info: [ 23170, 24105) |**+ Info: [ 24105, 25040) |*+ Info: [ 25040, 25975) |*+ Info: [ 25975, 26910) |************+ Info: [ 26910, 27845) |**************+ Info: [ 27845, 28780) |***********+ Info: [ 28780, 29715) |***********************************************************+ Info: [ 29715, 30650) |************************************************************ Info: [ 30650, 31585) |**+ Info: [ 31585, 32520) |+ Info: [ 32520, 33455) |******+ Info: [ 33455, 34390) |*********+ Info: [ 34390, 35325) |**+ Info: [ 35325, 36260) |****+ Info: [ 36260, 37195) |************+ Info: [ 37195, 38130) |****+ Info: [ 38130, 39065) |***+ Info: Program finished normally. [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (ECPPACK) [Pipeline] sh + /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Flash) [Pipeline] parallel [Pipeline] { (Branch: openFPGAloader ECP5) [Pipeline] { (Branch: openFPGAloader Tangnano 20k) [Pipeline] stage [Pipeline] { (openFPGAloader ECP5) [Pipeline] stage [Pipeline] { (openFPGAloader Tangnano 20k) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] lock Trying to acquire lock on [ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [ecp5] [Pipeline] { [Pipeline] lock Trying to acquire lock on [tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [tangnano20k] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada [Pipeline] sh + /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 DAPLink CMSIS-DAP Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE + echo gravando na tang nano gravando na tang nano [Pipeline] } Lock released on resource [tangnano20k] [Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } [Pipeline] // stage [Pipeline] } Loading: [====== ] 11.00% Loading: [=========== ] 22.00% Loading: [================= ] 33.00% Loading: [====================== ] 44.00% Loading: [============================ ] 55.00% Loading: [================================= ] 65.99% Loading: [======================================= ] 76.99% Loading: [============================================ ] 87.99% Loading: [==================================================] 98.99% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } Lock released on resource [ecp5] [Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Testes) [Pipeline] parallel [Pipeline] { (Branch: ECP5 - Testes) [Pipeline] { (Branch: TangNano - Testes) [Pipeline] stage [Pipeline] { (ECP5 - Testes) [Pipeline] stage [Pipeline] { (TangNano - Testes) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] echo Rodando teste na ECP5 [Pipeline] lock Trying to acquire lock on [ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [ecp5] [Pipeline] { [Pipeline] echo Rodando teste na tang nano [Pipeline] lock Trying to acquire lock on [tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [tangnano20k] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada [Pipeline] sh + echo testando na ecp5 testando na ecp5 [Pipeline] } Lock released on resource [ecp5] + echo testando na tang nano testando na tang nano [Pipeline] // lock [Pipeline] echo ECP5 liberada [Pipeline] } [Pipeline] } Lock released on resource [tangnano20k] [Pipeline] // script [Pipeline] // lock [Pipeline] } [Pipeline] echo TangNano liberada [Pipeline] } [Pipeline] // stage [Pipeline] // script [Pipeline] } [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline Finished: SUCCESS