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Start of Pipeline - (3 min 51 sec in block)
node - (3 min 50 sec in block)
node block - (3 min 50 sec in block)
stage - (2.1 sec in block)Git Clone
stage block (Git Clone) - (1.8 sec in block)
sh - (0.39 sec in self)rm -Rf Risco-5/ build/
sh - (0.9 sec in self)git clone https://github.com/JN513/Risco-5
sh - (0.35 sec in self)cd Risco-5
stage - (2.4 sec in block)IVerilog
stage block (IVerilog) - (2.1 sec in block)
sh - (0.41 sec in self)mkdir -p build
sh - (0.39 sec in self)cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
sh - (0.42 sec in self) /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/*.v Risco-5/src/peripheral/*.v Risco-5/tests/soc_test.v
sh - (0.39 sec in self)/eda/oss-cad-suite/bin/vvp build/soc_test.o
sh - (0.35 sec in self)rm -f Risco-5/software/memory/generic.hex
stage - (3 min 39 sec in block)Síntese
stage block (Síntese) - (3 min 39 sec in block)
parallel - (3 min 38 sec in block)
parallel block (Branch: OSS-Cad-Suite) - (34 ms in block)
stage - (58 sec in block)OSS-Cad-Suite
stage block (OSS-Cad-Suite) - (58 sec in block)
stage - (14 sec in block)Yosys
stage block (Yosys) - (14 sec in block)
sh - (13 sec in self) /eda/oss-cad-suite/bin/yosys -p " read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 "
stage - (42 sec in block)NextPNR
stage block (NextPNR) - (41 sec in block)
sh - (41 sec in self) /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
stage - (1.2 sec in block)ECPPACK
stage block (ECPPACK) - (1 sec in block)
sh - (0.87 sec in self)/eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
parallel block (Branch: Gowin) - (34 ms in block)
stage - (1.6 sec in block)Gowin
stage block (Gowin) - (1.5 sec in block)
sh - (0.66 sec in self)rm -rf Risco-5/impl/pnr
sh - (0.38 sec in self)mkdir -p Risco-5/impl/pnr
parallel block (Branch: Vivado) - (3 min 38 sec in block)
stage - (3 min 37 sec in block)Vivado
stage block (Vivado) - (3 min 37 sec in block)
sh - (3 min 37 sec in self)cd Risco-5/fpga/nexys4_ddr && /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl
stage - (2.8 sec in block)FPGA Flash
stage block (FPGA Flash) - (2.4 sec in block)
parallel - (2.2 sec in block)
parallel block (Branch: openFPGAloader ECP5) - (22 ms in block)
stage - (0.93 sec in block)openFPGAloader ECP5
stage block (openFPGAloader ECP5) - (0.44 sec in block)
parallel block (Branch: openFPGAloader Tangnano 20k) - (23 ms in block)
stage - (0.94 sec in block)openFPGAloader Tangnano 20k
stage block (openFPGAloader Tangnano 20k) - (0.44 sec in block)
parallel block (Branch: openFPGAloader Nexys 4 DDR) - (1.6 sec in block)
stage - (0.92 sec in block)openFPGAloader Nexys 4 DDR
stage block (openFPGAloader Nexys 4 DDR) - (0.44 sec in block)
stage - (2.8 sec in block)Testes
stage block (Testes) - (2.5 sec in block)
parallel - (2.2 sec in block)
parallel block (Branch: ECP5 - Testes) - (34 ms in block)
stage - (0.97 sec in block)ECP5 - Testes
stage block (ECP5 - Testes) - (0.49 sec in block)
parallel block (Branch: TangNano - Testes) - (34 ms in block)
stage - (0.97 sec in block)TangNano - Testes
stage block (TangNano - Testes) - (0.49 sec in block)
parallel block (Branch: Nexys 4 - Testes) - (1.6 sec in block)
stage - (0.97 sec in block)Nexys 4 - Testes
stage block (Nexys 4 - Testes) - (0.49 sec in block)