Console Output

Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco 5@2
[Pipeline] {
[Pipeline] stage
[Pipeline] { (git_clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ /eda/oss-cad-suite/bin/yosys -p                          read_verilog Risco-5/fpga/ecp5/*.v;                         read_verilog Risco-5/debug/clk_divider.v;                         read_verilog Risco-5/src/core/*.v;                         read_verilog Risco-5/src/peripheral/*.v;                         synth_ecp5 -json ./build/out.json -abc9                     

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)


-- Running command `                         read_verilog Risco-5/fpga/ecp5/*.v;                         read_verilog Risco-5/debug/clk_divider.v;                         read_verilog Risco-5/src/core/*.v;                         read_verilog Risco-5/src/peripheral/*.v;                         synth_ecp5 -json ./build/out.json -abc9                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/reset.v
Parsing Verilog input from `Risco-5/fpga/ecp5/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/debug/clk_divider.v
Parsing Verilog input from `Risco-5/debug/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\ALU'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:76: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

19. Executing SYNTH_ECP5 pass.

19.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

19.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

19.3. Executing HIERARCHY pass (managing design hierarchy).

19.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: ALU                 
root of   0 design levels: ClkDivider          
root of   0 design levels: ResetBootSystem     
root of   3 design levels: top                 
Automatically selected top as design top module.

19.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Used module:     \ClkDivider
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \MEMORY_SIZE = 4096
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000

19.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \MEMORY_SIZE = 4096
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Generating RTLIL representation for module `$paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC'.
Parameter \CYCLES = 20

19.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \COUNTER_BITS = 32

19.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Generating RTLIL representation for module `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600

19.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

19.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

19.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:76: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

19.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

19.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.

19.3.11. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Found cached RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 4096

19.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

19.3.13. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.

19.3.14. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000

19.3.15. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\Core'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removed 9 unused modules.

19.4. Executing PROC pass (convert processes to netlists).

19.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$364'.
Found and cleaned up 1 empty switch in `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:0$627'.
Removing empty process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:0$627'.
Cleaned up 2 empty switches.

19.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$471 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$423 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$365 in module TRELLIS_DPR16X4.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$611 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$609 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$601 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$598 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$592 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$587 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$582 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$573 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$560 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$558 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$550 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$536 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$530 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$525 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:135$515 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:31$618 in module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$132 in module LEDs.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:155$69 in module Registers.
Removed 2 dead cases from process $proc$Risco-5/src/core/registers.v:81$68 in module Registers.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:81$68 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:19$64 in module PC.
Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:10$63 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:10$63 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:7$60 in module Immediate_Generator.
Marked 3 switch rules as full_case in process $proc$Risco-5/debug/clk_divider.v:25$485 in module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:69$51 in module Control_Unit.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:52$48 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:44$47 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:8$45 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:8$45 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:11$30 in module ALU.
Marked 5 switch rules as full_case in process $proc$Risco-5/fpga/ecp5/reset.v:24$474 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Removed a total of 4 dead cases.

19.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 8 redundant assignments.
Promoted 131 assignments to connections.

19.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$472'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$613'.
  Set init value: \i = 0
Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$566'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$518'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$135'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `\Registers.$proc$Risco-5/src/core/registers.v:0$72'.
  Set init value: \register0 = 0
  Set init value: \register1 = 0
  Set init value: \register2 = 0
  Set init value: \register3 = 0
  Set init value: \register4 = 0
  Set init value: \register5 = 0
  Set init value: \register6 = 0
  Set init value: \register7 = 0
  Set init value: \register8 = 0
  Set init value: \register9 = 0
  Set init value: \register10 = 0
  Set init value: \register11 = 0
  Set init value: \register12 = 0
  Set init value: \register13 = 0
  Set init value: \register14 = 0
  Set init value: \register15 = 0
  Set init value: \register16 = 0
  Set init value: \register17 = 0
  Set init value: \register18 = 0
  Set init value: \register19 = 0
  Set init value: \register20 = 0
  Set init value: \register21 = 0
  Set init value: \register22 = 0
  Set init value: \register23 = 0
  Set init value: \register24 = 0
  Set init value: \register25 = 0
  Set init value: \register26 = 0
  Set init value: \register27 = 0
  Set init value: \register28 = 0
  Set init value: \register29 = 0
  Set init value: \register30 = 0
  Set init value: \register31 = 0
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$67'.
  Set init value: \PC_Register = 0
Found init rule in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$497'.
  Set init value: \clk_o_pulse = 1'0
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$53'.
  Set init value: \state = 3'000
  Set init value: \pc_write_cond = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \lorD = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \memory_to_reg = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 2'00
  Set init value: \alu_src_b = 2'00
  Set init value: \reg_write = 1'0
  Set init value: \nextstate = 3'000
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:0$480'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000

19.4.5. Executing PROC_ARST pass (detect async resets in processes).

19.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~75 debug messages>

19.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$472'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$471'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$423'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$422_EN[3:0]$429
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$422_DATA[3:0]$428
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$422_ADDR[3:0]$427
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$365'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$363_EN[3:0]$371
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$363_DATA[3:0]$370
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$363_ADDR[3:0]$369
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$364'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$613'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$611'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$609'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$601'.
     1/1: $0\cycle_counter[12:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$598'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$592'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$587'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$582'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$573'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$566'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$560'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$558'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$550'.
     1/1: $0\cycle_counter[12:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$536'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$530'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$525'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$518'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$515'.
     1/5: $0\alu_out_register[31:0]
     2/5: $0\register_data_2[31:0]
     3/5: $0\register_data_1[31:0]
     4/5: $0\memory_register[31:0]
     5/5: $0\instruction_register[31:0]
Creating decoders for process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$618'.
     1/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$625
     2/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_DATA[31:0]$624
     3/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_ADDR[31:0]$623
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$135'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$132'.
     1/1: $0\data[32:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$72'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
     1/32: $0\register31[31:0]
     2/32: $0\register30[31:0]
     3/32: $0\register29[31:0]
     4/32: $0\register28[31:0]
     5/32: $0\register27[31:0]
     6/32: $0\register26[31:0]
     7/32: $0\register25[31:0]
     8/32: $0\register24[31:0]
     9/32: $0\register23[31:0]
    10/32: $0\register22[31:0]
    11/32: $0\register21[31:0]
    12/32: $0\register20[31:0]
    13/32: $0\register19[31:0]
    14/32: $0\register18[31:0]
    15/32: $0\register17[31:0]
    16/32: $0\register16[31:0]
    17/32: $0\register15[31:0]
    18/32: $0\register14[31:0]
    19/32: $0\register13[31:0]
    20/32: $0\register12[31:0]
    21/32: $0\register11[31:0]
    22/32: $0\register10[31:0]
    23/32: $0\register9[31:0]
    24/32: $0\register8[31:0]
    25/32: $0\register7[31:0]
    26/32: $0\register6[31:0]
    27/32: $0\register5[31:0]
    28/32: $0\register4[31:0]
    29/32: $0\register3[31:0]
    30/32: $0\register2[31:0]
    31/32: $0\register1[31:0]
    32/32: $0\register0[31:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
     1/2: $1\readData2[31:0]
     2/2: $1\readData1[31:0]
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$67'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:19$64'.
     1/1: $1\PC_Register[31:0]
Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:10$63'.
     1/1: $1\S[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
     1/1: $1\immediate[31:0]
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$497'.
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$495'.
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$485'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$53'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
     1/23: $2\reg_write[0:0]
     2/23: $2\memory_write[0:0]
     3/23: $2\memory_read[0:0]
     4/23: $2\lorD[0:0]
     5/23: $2\aluop[1:0]
     6/23: $3\alu_src_a[1:0]
     7/23: $2\alu_src_b[1:0]
     8/23: $2\pc_source[0:0]
     9/23: $2\pc_write[0:0]
    10/23: $2\pc_write_cond[0:0]
    11/23: $2\alu_src_a[1:0]
    12/23: $1\pc_write[0:0]
    13/23: $1\alu_src_b[1:0]
    14/23: $1\ir_write[0:0]
    15/23: $1\memory_read[0:0]
    16/23: $1\reg_write[0:0]
    17/23: $1\alu_src_a[1:0]
    18/23: $1\aluop[1:0]
    19/23: $1\pc_source[0:0]
    20/23: $1\memory_to_reg[0:0]
    21/23: $1\memory_write[0:0]
    22/23: $1\lorD[0:0]
    23/23: $1\pc_write_cond[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48'.
     1/3: $3\nextstate[2:0]
     2/3: $2\nextstate[2:0]
     3/3: $1\nextstate[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:44$47'.
     1/1: $0\state[2:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45'.
     1/4: $4\aluop_out[3:0]
     2/4: $3\aluop_out[3:0]
     3/4: $2\aluop_out[3:0]
     4/4: $1\aluop_out[3:0]
Creating decoders for process `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.
     1/1: $1\ALU_out_S[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:0$480'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$474'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]

19.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$582'.
No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$525'.
No latch inferred for signal `\Registers.\readData1' from process `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
No latch inferred for signal `\Registers.\readData2' from process `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:10$63'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48`.
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45': $auto$proc_dlatch.cc:427:proc_dlatch$2097
No latch inferred for signal `\ALU.\ALU_out_S' from process `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.

19.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$471'.
  created $dff cell `$procdff$2120' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$407_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$408_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$409_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$410_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$411_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$412_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$413_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$414_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$415_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$416_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$417_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$418_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$419_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$420_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$421_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$422_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$423'.
  created $dff cell `$procdff$2121' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$422_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$423'.
  created $dff cell `$procdff$2122' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$422_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$423'.
  created $dff cell `$procdff$2123' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$347_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$348_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$349_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$350_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$351_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$352_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$353_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$354_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$355_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$356_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$357_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$358_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$359_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$360_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$361_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$362_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$363_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$365'.
  created $dff cell `$procdff$2124' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$363_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$365'.
  created $dff cell `$procdff$2125' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$363_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$365'.
  created $dff cell `$procdff$2126' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$611'.
  created $dff cell `$procdff$2127' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg_0' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$611'.
  created $dff cell `$procdff$2128' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$609'.
  created $dff cell `$procdff$2129' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$601'.
  created $dff cell `$procdff$2130' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_sample' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$598'.
  created $dff cell `$procdff$2131' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$592'.
  created $dff cell `$procdff$2132' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$587'.
  created $dff cell `$procdff$2133' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\recieved_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$587'.
  created $dff cell `$procdff$2134' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\uart_rx_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$573'.
  created $dff cell `$procdff$2135' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\txd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$560'.
  created $dff cell `$procdff$2136' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$558'.
  created $dff cell `$procdff$2137' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$550'.
  created $dff cell `$procdff$2138' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$536'.
  created $dff cell `$procdff$2139' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$530'.
  created $dff cell `$procdff$2140' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\data_to_send' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$530'.
  created $dff cell `$procdff$2141' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$515'.
  created $dff cell `$procdff$2142' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$515'.
  created $dff cell `$procdff$2143' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$515'.
  created $dff cell `$procdff$2144' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$515'.
  created $dff cell `$procdff$2145' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$515'.
  created $dff cell `$procdff$2146' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_ADDR' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$618'.
  created $dff cell `$procdff$2147' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_DATA' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$618'.
  created $dff cell `$procdff$2148' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$618'.
  created $dff cell `$procdff$2149' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$132'.
  created $dff cell `$procdff$2150' with positive edge clock.
Creating register for signal `\Registers.\register0' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2151' with positive edge clock.
Creating register for signal `\Registers.\register1' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2152' with positive edge clock.
Creating register for signal `\Registers.\register2' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2153' with positive edge clock.
Creating register for signal `\Registers.\register3' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2154' with positive edge clock.
Creating register for signal `\Registers.\register4' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2155' with positive edge clock.
Creating register for signal `\Registers.\register5' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2156' with positive edge clock.
Creating register for signal `\Registers.\register6' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2157' with positive edge clock.
Creating register for signal `\Registers.\register7' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2158' with positive edge clock.
Creating register for signal `\Registers.\register8' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2159' with positive edge clock.
Creating register for signal `\Registers.\register9' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2160' with positive edge clock.
Creating register for signal `\Registers.\register10' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2161' with positive edge clock.
Creating register for signal `\Registers.\register11' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2162' with positive edge clock.
Creating register for signal `\Registers.\register12' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2163' with positive edge clock.
Creating register for signal `\Registers.\register13' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2164' with positive edge clock.
Creating register for signal `\Registers.\register14' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2165' with positive edge clock.
Creating register for signal `\Registers.\register15' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2166' with positive edge clock.
Creating register for signal `\Registers.\register16' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2167' with positive edge clock.
Creating register for signal `\Registers.\register17' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2168' with positive edge clock.
Creating register for signal `\Registers.\register18' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2169' with positive edge clock.
Creating register for signal `\Registers.\register19' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2170' with positive edge clock.
Creating register for signal `\Registers.\register20' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2171' with positive edge clock.
Creating register for signal `\Registers.\register21' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2172' with positive edge clock.
Creating register for signal `\Registers.\register22' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2173' with positive edge clock.
Creating register for signal `\Registers.\register23' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2174' with positive edge clock.
Creating register for signal `\Registers.\register24' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2175' with positive edge clock.
Creating register for signal `\Registers.\register25' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2176' with positive edge clock.
Creating register for signal `\Registers.\register26' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2177' with positive edge clock.
Creating register for signal `\Registers.\register27' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2178' with positive edge clock.
Creating register for signal `\Registers.\register28' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2179' with positive edge clock.
Creating register for signal `\Registers.\register29' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2180' with positive edge clock.
Creating register for signal `\Registers.\register30' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2181' with positive edge clock.
Creating register for signal `\Registers.\register31' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2182' with positive edge clock.
Creating register for signal `\PC.\PC_Register' using process `\PC.$proc$Risco-5/src/core/pc.v:19$64'.
  created $dff cell `$procdff$2183' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_o_pulse' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$495'.
  created $dff cell `$procdff$2184' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_o_auto' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$485'.
  created $dff cell `$procdff$2185' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_counter' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$485'.
  created $dff cell `$procdff$2186' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:44$47'.
  created $dff cell `$procdff$2187' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$474'.
  created $dff cell `$procdff$2188' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$474'.
  created $dff cell `$procdff$2189' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$474'.
  created $dff cell `$procdff$2190' with positive edge clock.

19.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

19.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$472'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$471'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$471'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$446'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$423'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$389'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$365'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$364'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$613'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$611'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$611'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$609'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$609'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$601'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$601'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$598'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$598'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$592'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$592'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$587'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$587'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$582'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$582'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$573'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$573'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$566'.
Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$560'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$560'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$558'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$558'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$550'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$550'.
Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$536'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$536'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$530'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$530'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$525'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$525'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$518'.
Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$515'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$515'.
Found and cleaned up 1 empty switch in `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$618'.
Removing empty process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$618'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$135'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$132'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$132'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$72'.
Found and cleaned up 3 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:155$69'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:81$68'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$67'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:19$64'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:19$64'.
Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:10$63'.
Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:10$63'.
Found and cleaned up 1 empty switch in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$497'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$495'.
Found and cleaned up 4 empty switches in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$485'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$485'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$53'.
Found and cleaned up 4 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Found and cleaned up 3 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:44$47'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:44$47'.
Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45'.
Found and cleaned up 1 empty switch in `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.
Removing empty process `ALU.$proc$Risco-5/src/core/alu.v:11$30'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:0$480'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$474'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$474'.
Cleaned up 75 empty switches.

19.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~2 debug messages>
Optimizing module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
<suppressed ~2 debug messages>
Optimizing module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module BUS.
Optimizing module Registers.
<suppressed ~4 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
Optimizing module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
<suppressed ~5 debug messages>
Optimizing module Control_Unit.
<suppressed ~5 debug messages>
Optimizing module ALU_Control.
<suppressed ~13 debug messages>
Optimizing module ALU.
<suppressed ~1 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module $paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC.
Optimizing module top.

19.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
Deleting now unused module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
Deleting now unused module LEDs.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module ALU.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module $paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC.
<suppressed ~21 debug messages>

19.6. Executing TRIBUF pass.

19.7. Executing DEMINOUT pass (demote inout ports to input or output).

19.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~52 debug messages>

19.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 122 unused cells and 623 unused wires.
<suppressed ~158 debug messages>

19.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\SOC.Core.PCSourceMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [31] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [30] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [29] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [28] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [27] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [26] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [25] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [24] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [23] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [22] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [21] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [20] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [19] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [18] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [17] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [16] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [15] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [14] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [13] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [12] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [11] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [10] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [9] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [8] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [7] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [6] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [5] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [4] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [3] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [2] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [1] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [0] is used but has no driver.
Found and reported 256 problems.

19.11. Executing OPT pass (performing simple optimizations).

19.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~9 debug messages>

19.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~438 debug messages>
Removed a total of 146 cells.

19.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1818.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1825.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1833.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1841.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1851.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1863.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1877.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1887.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1898.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1906.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1915.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1983.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1991.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1771.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1771.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$1771.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$1771.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1771.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1771.
Removed 19 multiplexer ports.
<suppressed ~88 debug messages>

19.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1838: $auto$opt_reduce.cc:134:opt_pmux$2193
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1847: { $auto$opt_reduce.cc:134:opt_pmux$2195 $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:57$49_Y }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1857: { $flatten\SOC.\Core.\Control_Unit.$procmux$1814_CMP $auto$opt_reduce.cc:134:opt_pmux$2197 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1870: { $auto$opt_reduce.cc:134:opt_pmux$2201 $auto$opt_reduce.cc:134:opt_pmux$2199 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1883: $auto$opt_reduce.cc:134:opt_pmux$2203
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1895: $auto$opt_reduce.cc:134:opt_pmux$2205
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1812: $auto$opt_reduce.cc:134:opt_pmux$2207
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1777: { $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:57$49_Y $flatten\SOC.\Core.\Control_Unit.$procmux$1813_CMP $auto$opt_reduce.cc:134:opt_pmux$2211 $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:61$50_Y $auto$opt_reduce.cc:134:opt_pmux$2209 $flatten\SOC.\Core.\Control_Unit.$procmux$1824_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2019: { $flatten\SOC.\Core.\ALU_Control.$procmux$2026_CMP $auto$opt_reduce.cc:134:opt_pmux$2213 $flatten\SOC.\Core.\ALU_Control.$procmux$2023_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2022_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2021_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2020_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1663: $auto$opt_reduce.cc:134:opt_pmux$2215
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2033: { $auto$opt_reduce.cc:134:opt_pmux$2219 $auto$opt_reduce.cc:134:opt_pmux$2217 $flatten\SOC.\Core.\ALU_Control.$procmux$2026_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2042: { $flatten\SOC.\Core.\ALU_Control.$procmux$2044_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2043_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$936:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_EN[31:0]$621 [0] }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$2196: { $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:57$49_Y $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:61$50_Y $flatten\SOC.\Core.\Control_Unit.$procmux$1816_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1817_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1824_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$2198: { $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:61$50_Y $flatten\SOC.\Core.\Control_Unit.$procmux$1814_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1815_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1816_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1824_CMP }
  Optimizing cells in module \top.
Performed a total of 17 changes.

19.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

19.11.6. Executing OPT_DFF pass (perform DFF optimizations).

19.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 177 unused wires.
<suppressed ~8 debug messages>

19.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.11.9. Rerunning OPT passes. (Maybe there is more to do..)

19.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~88 debug messages>

19.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

19.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.11.13. Executing OPT_DFF pass (perform DFF optimizations).

19.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

19.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.11.16. Finished OPT passes. (There is nothing left to do.)

19.12. Executing FSM pass (extract and optimize FSM).

19.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Register has an initialization value.
Not marking top.SOC.Core.RegisterBank.register0 as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_tx.fsm_state.

19.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_tx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_tx.$procdff$2137
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$544_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$534_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$552_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$532_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_tx.stop_done
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_tx.payload_done
  found state code: 3'010
  found ctrl input: \SOC.Uart.i_uart_tx.next_bit
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_tx.uart_tx_en
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$552_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$544_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$539_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$538_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$534_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$532_Y
  ctrl inputs: { \SOC.Uart.i_uart_tx.uart_tx_en \SOC.Uart.i_uart_tx.next_bit \SOC.Uart.i_uart_tx.payload_done \SOC.Uart.i_uart_tx.stop_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$532_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$534_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$538_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$539_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$544_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$552_Y $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] }
  transition:      3'000 5'0---0 ->      3'000 9'101100000
  transition:      3'000 5'1---0 ->      3'001 9'101100001
  transition:      3'000 5'----1 ->      3'000 9'101100000
  transition:      3'010 5'--0-0 ->      3'010 9'010100010
  transition:      3'010 5'--1-0 ->      3'011 9'010100011
  transition:      3'010 5'----1 ->      3'000 9'010100000
  transition:      3'001 5'-0--0 ->      3'001 9'001101001
  transition:      3'001 5'-1--0 ->      3'010 9'001101010
  transition:      3'001 5'----1 ->      3'000 9'001101000
  transition:      3'011 5'---00 ->      3'011 9'001010011
  transition:      3'011 5'---10 ->      3'000 9'001010000
  transition:      3'011 5'----1 ->      3'000 9'001010000

19.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2220' from module `\top'.

19.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>

19.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2220' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [2].

19.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2220' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

19.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2220' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_tx.fsm_state$2220 (\SOC.Uart.i_uart_tx.fsm_state):

  Number of input signals:    5
  Number of output signals:   6
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_tx.stop_done
    2: \SOC.Uart.i_uart_tx.payload_done
    3: \SOC.Uart.i_uart_tx.next_bit
    4: \SOC.Uart.i_uart_tx.uart_tx_en

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$552_Y
    1: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$544_Y
    2: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$539_Y
    3: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$538_Y
    4: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$534_Y
    5: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$532_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 5'0---0   ->     0 6'101100
      1:     0 5'----1   ->     0 6'101100
      2:     0 5'1---0   ->     2 6'101100
      3:     1 5'----1   ->     0 6'010100
      4:     1 5'--0-0   ->     1 6'010100
      5:     1 5'--1-0   ->     3 6'010100
      6:     2 5'----1   ->     0 6'001101
      7:     2 5'-1--0   ->     1 6'001101
      8:     2 5'-0--0   ->     2 6'001101
      9:     3 5'---10   ->     0 6'001010
     10:     3 5'----1   ->     0 6'001010
     11:     3 5'---00   ->     3 6'001010

-------------------------------------

19.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2220' from module `\top'.

19.13. Executing OPT pass (performing simple optimizations).

19.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

19.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~87 debug messages>

19.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

19.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2141 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$898_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$892_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$883_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$874_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$865_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$856_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$838_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$847_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2272 ($sdff) from module top (D = \SOC.Bus.slave_2_write_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$2272 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$892_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$883_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$874_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$865_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$856_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$838_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$847_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2139 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$814_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2277 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$814_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2138 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$803_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2283 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$557_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2136 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$792_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2287 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$792_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$2150 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$944_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2293 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2182 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register31).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2181 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register30).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2180 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register29).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2179 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register28).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2178 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register27).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2177 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register26).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2176 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register25).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2175 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register24).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2174 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register23).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2173 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register22).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2172 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register21).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2171 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register20).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2170 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register19).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2169 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register18).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2168 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register17).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2167 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register16).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2166 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register15).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2165 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register14).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2164 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register13).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2163 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register12).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2162 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register11).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2161 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register10).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2160 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register9).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2159 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register8).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2158 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register7).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2157 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register6).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2156 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register5).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2155 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register4).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2154 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register3).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2153 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register2).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2152 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register1).
Adding SRST signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2151 ($dff) from module top (D = $flatten\SOC.\Core.\RegisterBank.$procmux$1695_Y, Q = \SOC.Core.RegisterBank.register0, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2450 ($sdff) from module top (D = 0, Q = \SOC.Core.RegisterBank.register0).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2183 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1766_Y, Q = \SOC.Core.Pc.PC_Register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2456 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.PC_Register).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2187 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 3'000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2146 ($dff) from module top (D = \SOC.Bus.write_data, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2145 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2144 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2143 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2142 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$930_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2463 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2190 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2189 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2188 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\ClkDivider.$procdff$2186 ($dff) from module top (D = $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$488_Y, Q = \ClkDivider.clk_counter, rval = 0).
Adding SRST signal on $flatten\ClkDivider.$procdff$2185 ($dff) from module top (D = $flatten\ClkDivider.$procmux$1802_Y, Q = \ClkDivider.clk_o_auto, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2491 ($sdff) from module top (D = $flatten\ClkDivider.$procmux$1802_Y, Q = \ClkDivider.clk_o_auto).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$2451 ($sdffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$2294 ($sdffe) from module top.

19.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 130 unused cells and 131 unused wires.
<suppressed ~131 debug messages>

19.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

19.13.9. Rerunning OPT passes. (Maybe there is more to do..)

19.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~48 debug messages>

19.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

19.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~93 debug messages>
Removed a total of 31 cells.

19.13.13. Executing OPT_DFF pass (perform DFF optimizations).

19.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 31 unused wires.
<suppressed ~1 debug messages>

19.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.13.16. Rerunning OPT passes. (Maybe there is more to do..)

19.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~48 debug messages>

19.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

19.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.13.20. Executing OPT_DFF pass (perform DFF optimizations).

19.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

19.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.13.23. Finished OPT passes. (There is nothing left to do.)

19.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2191 (SOC.Memory.memory).
Removed top 22 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$626 (SOC.Memory.memory).
Removed top 22 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$616 (SOC.Memory.memory).
Removed top 7 bits (of 32) from port B of cell top.$flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$494 ($ge).
Removed top 8 bits (of 32) from port B of cell top.$flatten\ClkDivider.$eq$Risco-5/debug/clk_divider.v:33$490 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$488 ($add).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$2071_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/fpga/ecp5/reset.v:38$478 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$477 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$477 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$476 ($lt).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2471 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$542 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$529 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$528 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$527 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$526 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$522 ($eq).
Removed top 1 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$520 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$131 ($mux).
Removed top 2 bits (of 8) from port Y of cell top.$flatten\SOC.\Leds.$not$Risco-5/src/peripheral/leds.v:31$134 ($not).
Removed top 2 bits (of 8) from port A of cell top.$flatten\SOC.\Leds.$not$Risco-5/src/peripheral/leds.v:31$134 ($not).
Removed top 20 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:44$74 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:45$77 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:46$78 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:54$93 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:55$94 ($le).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:61$108 ($mux).
Removed top 22 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$942 ($mux).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$eq$Risco-5/src/core/alu_control.v:34$46 ($eq).
Removed top 29 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61 ($sub).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1774_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1774_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1764_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1763_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1762_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1761_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1760_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1759_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1758_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1757_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1756_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1755_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1754_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1753_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1752_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1751_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1750_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1731_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1730_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1729_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1728_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1727_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1726_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1725_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1724_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1723_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1722_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1721_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1720_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1719_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1718_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1717_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1656_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1618_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1581_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1545_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1510_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1476_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1443_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1411_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1380_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1350_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1321_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1293_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1266_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1240_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1215_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2476 ($ne).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1989 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1916_CMP0 ($eq).
Removed top 1 bits (of 2) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1913 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1852_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1824_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1819_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1817_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1816_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1815_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1814_CMP0 ($eq).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:61$50 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2044_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2026_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2025_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2024_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2012 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2057_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2056_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2055_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2054_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$44 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:22$36 ($mux).
Removed top 29 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62 ($sub).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:43$73 ($ge).
Removed top 20 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:64$112 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$477_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:22$36_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$44_Y.
Removed top 1 bits (of 2) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\alu_src_a[1:0].
Removed top 1 bits (of 3) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\nextstate[2:0].
Removed top 22 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$614_ADDR[31:0]$619.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$526_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$527_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$528_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$529_Y.
Removed top 2 bits (of 8) from wire top.leds.

19.15. Executing PEEPOPT pass (run peephole optimizers).

19.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 14 unused wires.
<suppressed ~1 debug messages>

19.17. Executing SHARE pass (SAT-based resource sharing).
Found 3 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$616 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:43$75_Y \SOC.Bus.slave_0_read }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:28$40 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2051_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:26$39 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2052_CMP.
    No candidates found.

19.18. Executing TECHMAP pass (map to technology primitives).

19.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

19.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~270 debug messages>

19.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

19.21. Executing TECHMAP pass (map to technology primitives).

19.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

19.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

19.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

19.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$488 ($add).
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$477 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62 ($sub).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$546 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$557 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$557.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$546.
  creating $alu model for $macc $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62.
  creating $alu model for $macc $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$477.
  creating $alu model for $macc $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$488.
  creating $alu model for $flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$494 ($ge): new $alu
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$476 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:43$73 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:45$77 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:54$93 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:44$74 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:46$78 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:55$94 ($le): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$43 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:22$35 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/fpga/ecp5/reset.v:38$478 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$476.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:55$94: $auto$alumacc.cc:485:replace_alu$2518
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:46$78: $auto$alumacc.cc:485:replace_alu$2531
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:44$74: $auto$alumacc.cc:485:replace_alu$2544
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:54$93: $auto$alumacc.cc:485:replace_alu$2557
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:45$77: $auto$alumacc.cc:485:replace_alu$2566
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:43$73: $auto$alumacc.cc:485:replace_alu$2575
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$476, $flatten\ResetBootSystem.$eq$Risco-5/fpga/ecp5/reset.v:38$478: $auto$alumacc.cc:485:replace_alu$2584
  creating $alu cell for $flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$494: $auto$alumacc.cc:485:replace_alu$2595
  creating $alu cell for $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$488: $auto$alumacc.cc:485:replace_alu$2604
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$477: $auto$alumacc.cc:485:replace_alu$2607
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33: $auto$alumacc.cc:485:replace_alu$2610
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$43, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:22$35, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42: $auto$alumacc.cc:485:replace_alu$2613
  creating $alu cell for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61: $auto$alumacc.cc:485:replace_alu$2626
  creating $alu cell for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62: $auto$alumacc.cc:485:replace_alu$2629
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$546: $auto$alumacc.cc:485:replace_alu$2632
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$557: $auto$alumacc.cc:485:replace_alu$2635
  created 16 $alu and 0 $macc cells.

19.23. Executing OPT pass (performing simple optimizations).

19.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

19.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~48 debug messages>

19.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2490: { $auto$rtlil.cc:2461:Not$2599 $auto$rtlil.cc:2464:ReduceAnd$2601 \reset }
  Optimizing cells in module \top.
Performed a total of 1 changes.

19.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.23.6. Executing OPT_DFF pass (perform DFF optimizations).

19.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 13 unused wires.
<suppressed ~2 debug messages>

19.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.23.9. Rerunning OPT passes. (Maybe there is more to do..)

19.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~48 debug messages>

19.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

19.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.23.13. Executing OPT_DFF pass (perform DFF optimizations).

19.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

19.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.23.16. Finished OPT passes. (There is nothing left to do.)

19.24. Executing MEMORY pass.

19.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

19.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

19.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Memory.memory write port 0.

19.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

19.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.

19.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

19.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

19.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

19.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

19.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

19.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

19.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
<suppressed ~68 debug messages>

19.27. Executing TECHMAP pass (map to technology primitives).

19.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

19.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

19.27.3. Continuing TECHMAP pass.
Using template $paramod$fb6ed8f936d3525780a052d218072c625795bc14\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$0eb199c7b2cea9c358f23ffe94c4548bdd802747\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b089c18cc881634130ec6d4716ef25d78c9d48c9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$731f2d82778baee6f78f5f3e0670a3ade61ac0d6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$48358c22c7a8e5b48ddefb8e14a8bb1f81de841f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5276274b86ff102139fbc8ae2dfc335d77b58a6a\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c75b2ca41d3ff8a2b5ad26d6a6ec321bb6e56448\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$315d0c5245324146665fc1ab307bed98cfcb6adf\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~634 debug messages>

19.28. Executing OPT pass (performing simple optimizations).

19.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~106 debug messages>

19.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

19.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$2465 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$2068_Y, Q = \ResetBootSystem.counter, rval = 6'000000).

19.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 28 unused cells and 3648 unused wires.
<suppressed ~29 debug messages>

19.28.5. Rerunning OPT passes. (Removed registers in this run.)

19.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

19.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$3909 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$2496 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

19.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 4 unused wires.
<suppressed ~3 debug messages>

19.28.10. Rerunning OPT passes. (Removed registers in this run.)

19.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.28.13. Executing OPT_DFF pass (perform DFF optimizations).

19.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

19.28.15. Finished fast OPT passes.

19.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

19.30. Executing OPT pass (performing simple optimizations).

19.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~41 debug messages>

19.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2077: { $flatten\ResetBootSystem.$procmux$2072_CMP $flatten\ResetBootSystem.$procmux$2071_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2080:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2080_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2080_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2080_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2012:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$2497 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$2497 [2]
      New connections: $auto$wreduce.cc:461:run$2497 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2033:
      Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0]
      New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] }
      New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1981:
      Old ports: A=3'000, B=3'100, Y=$flatten\SOC.\Core.\Control_Unit.$3\nextstate[2:0]
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$3\nextstate[2:0] [2]
      New connections: $flatten\SOC.\Core.\Control_Unit.$3\nextstate[2:0] [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1989:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2502 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2502 [0]
      New connections: $auto$wreduce.cc:461:run$2502 [1] = $auto$wreduce.cc:461:run$2502 [0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$913:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.i_uart_tx.uart_tx_en 1'0 $auto$wreduce.cc:461:run$2505 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$2507 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.i_uart_tx.uart_tx_en $auto$wreduce.cc:461:run$2505 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$2507 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$529:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2507 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2507 [0]
      New connections: $auto$wreduce.cc:461:run$2507 [1] = $auto$wreduce.cc:461:run$2507 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2086:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2080_Y, Y=$flatten\ResetBootSystem.$procmux$2086_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2080_Y [1], Y=$flatten\ResetBootSystem.$procmux$2086_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2086_Y [0] = 1'0
  Optimizing cells in module \top.
Performed a total of 9 changes.

19.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.30.6. Executing OPT_DFF pass (perform DFF optimizations).

19.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

19.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.30.9. Rerunning OPT passes. (Maybe there is more to do..)

19.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~41 debug messages>

19.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

19.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.30.13. Executing OPT_DFF pass (perform DFF optimizations).

19.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

19.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.30.16. Finished OPT passes. (There is nothing left to do.)

19.31. Executing TECHMAP pass (map to technology primitives).

19.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

19.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

19.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $ne.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $eq.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_bool.
Using template $paramod$7c98249b977afe59aa75782d58a190a9577d92fe\_80_ecp5_alu for cells of type $alu.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$861f5302217787cd55fd1a501bc728125f176580\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using template $paramod$3111a1a8e90c88cc8c163ba5aed0203d96ddc46d\_80_ecp5_alu for cells of type $alu.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$215440792383f7884e57d9c95f84e9552d0bf4ac\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$41ef080258eed1ff8fcfbb7776f540ab469a3d7b\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c4ef20b21801b37ea2d65c32a05dfe56e84a870d\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$c83925f608704c3fa34790ddcfce9302bdcd7533\_90_pmux for cells of type $pmux.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux.
Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $dlatch.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~3462 debug messages>

19.32. Executing OPT pass (performing simple optimizations).

19.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5835 debug messages>

19.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3375 debug messages>
Removed a total of 1125 cells.

19.32.3. Executing OPT_DFF pass (perform DFF optimizations).

19.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 273 unused cells and 3374 unused wires.
<suppressed ~274 debug messages>

19.32.5. Finished fast OPT passes.

19.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

19.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

19.35. Executing TECHMAP pass (map to technology primitives).

19.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

19.35.2. Continuing TECHMAP pass.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
No more expansions possible.
<suppressed ~1395 debug messages>

19.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

19.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

19.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

19.39. Executing ATTRMVCP pass (move or copy attributes).

19.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 6580 unused wires.
<suppressed ~1 debug messages>

19.41. Executing TECHMAP pass (map to technology primitives).

19.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

19.41.2. Continuing TECHMAP pass.

19.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$27059 ($mux).
Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$27058 ($logic_not).
<suppressed ~4 debug messages>

19.41.4. Executing OPT pass (performing simple optimizations).

19.41.4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.
<suppressed ~1 debug messages>

19.41.4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

19.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

19.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

19.41.4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

19.41.4.6. Executing OPT_DFF pass (perform DFF optimizations).

19.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

19.41.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

19.41.4.9. Rerunning OPT passes. (Maybe there is more to do..)

19.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

19.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

19.41.4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

19.41.4.13. Executing OPT_DFF pass (perform DFF optimizations).

19.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..

19.41.4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

19.41.4.16. Finished OPT passes. (There is nothing left to do.)
Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_.
No more expansions possible.
<suppressed ~4 debug messages>

19.42. Executing ABC9 pass.

19.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

19.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

19.42.3. Executing PROC pass (convert processes to netlists).

19.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27154'.
Cleaned up 1 empty switch.

19.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27155 in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

19.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

19.42.3.4. Executing PROC_INIT pass (extract init attributes).

19.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

19.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

19.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27155'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27153_EN[3:0]$27161
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27153_DATA[3:0]$27160
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27153_ADDR[3:0]$27159
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27154'.

19.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

19.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.\i' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27151_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27145_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27139_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27140_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27141_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27142_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27146_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27147_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27137_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27148_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27152_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27138_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27143_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27144_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27149_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27150_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27153_ADDR' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27155'.
  created $dff cell `$procdff$27205' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27153_DATA' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27155'.
  created $dff cell `$procdff$27206' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27153_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27155'.
  created $dff cell `$procdff$27207' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27154'.
  created direct connection (no actual register cell created).

19.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

19.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27179'.
Found and cleaned up 1 empty switch in `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27155'.
Removing empty process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27154'.
Cleaned up 1 empty switch.

19.42.3.12. Executing OPT_EXPR pass (perform const folding).

19.42.4. Executing PROC pass (convert processes to netlists).

19.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27225'.
Cleaned up 1 empty switch.

19.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27226 in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

19.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

19.42.4.4. Executing PROC_INIT pass (extract init attributes).

19.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

19.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

19.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27226'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27224_EN[3:0]$27232
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27224_DATA[3:0]$27231
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27224_ADDR[3:0]$27230
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27225'.

19.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

19.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.\i' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27222_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27217_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27212_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27208_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27209_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27213_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27214_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27218_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27210_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27219_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27223_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27215_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27211_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27220_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27216_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27221_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27224_ADDR' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27226'.
  created $dff cell `$procdff$27276' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27224_DATA' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27226'.
  created $dff cell `$procdff$27277' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27224_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27226'.
  created $dff cell `$procdff$27278' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27225'.
  created direct connection (no actual register cell created).

19.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

19.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27250'.
Found and cleaned up 1 empty switch in `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27226'.
Removing empty process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27225'.
Cleaned up 1 empty switch.

19.42.4.12. Executing OPT_EXPR pass (perform const folding).

19.42.5. Executing PROC pass (convert processes to netlists).

19.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27296'.
Cleaned up 1 empty switch.

19.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27297 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

19.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

19.42.5.4. Executing PROC_INIT pass (extract init attributes).

19.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

19.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

19.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27297'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27295_EN[3:0]$27303
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27295_DATA[3:0]$27302
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27295_ADDR[3:0]$27301
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27296'.

19.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

19.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27290_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27285_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27280_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27279_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27281_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27282_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27286_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27287_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27291_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27283_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27292_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27288_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27284_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27293_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27289_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27294_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27295_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27297'.
  created $dff cell `$procdff$27347' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27295_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27297'.
  created $dff cell `$procdff$27348' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27295_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27297'.
  created $dff cell `$procdff$27349' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27296'.
  created direct connection (no actual register cell created).

19.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

19.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27321'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27297'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27296'.
Cleaned up 1 empty switch.

19.42.5.12. Executing OPT_EXPR pass (perform const folding).

19.42.6. Executing PROC pass (convert processes to netlists).

19.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27367'.
Cleaned up 1 empty switch.

19.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27368 in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

19.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

19.42.6.4. Executing PROC_INIT pass (extract init attributes).

19.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

19.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

19.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27368'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27366_EN[3:0]$27372
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27366_DATA[3:0]$27374
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27366_ADDR[3:0]$27373
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27367'.

19.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

19.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.\i' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27363_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27358_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27353_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27350_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27354_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27355_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27359_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27351_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27360_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27364_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27356_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27365_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27352_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27361_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27357_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27362_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27366_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27368'.
  created $dff cell `$procdff$27418' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27366_ADDR' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27368'.
  created $dff cell `$procdff$27419' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27366_DATA' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27368'.
  created $dff cell `$procdff$27420' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27367'.
  created direct connection (no actual register cell created).

19.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

19.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27392'.
Found and cleaned up 1 empty switch in `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27368'.
Removing empty process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27367'.
Cleaned up 1 empty switch.

19.42.6.12. Executing OPT_EXPR pass (perform const folding).

19.42.7. Executing PROC pass (convert processes to netlists).

19.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27438'.
Cleaned up 1 empty switch.

19.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27439 in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

19.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

19.42.7.4. Executing PROC_INIT pass (extract init attributes).

19.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

19.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

19.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27439'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27437_EN[3:0]$27445
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27437_DATA[3:0]$27444
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27437_ADDR[3:0]$27443
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27438'.

19.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

19.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.\i' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27436_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27431_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27426_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27421_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27422_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27423_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27427_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27428_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27432_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27424_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27433_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27429_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27425_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27434_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27430_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27435_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27437_ADDR' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27439'.
  created $dff cell `$procdff$27489' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27437_DATA' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27439'.
  created $dff cell `$procdff$27490' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27437_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27439'.
  created $dff cell `$procdff$27491' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27438'.
  created direct connection (no actual register cell created).

19.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

19.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27463'.
Found and cleaned up 1 empty switch in `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27439'.
Removing empty process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27438'.
Cleaned up 1 empty switch.

19.42.7.12. Executing OPT_EXPR pass (perform const folding).

19.42.8. Executing PROC pass (convert processes to netlists).

19.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27509'.
Cleaned up 1 empty switch.

19.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27510 in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

19.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

19.42.8.4. Executing PROC_INIT pass (extract init attributes).

19.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

19.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

19.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27510'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27508_EN[3:0]$27516
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27508_DATA[3:0]$27515
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27508_ADDR[3:0]$27514
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27509'.

19.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

19.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.\i' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27505_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27499_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27494_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27492_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27495_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27496_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27500_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27501_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27502_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27506_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27507_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27497_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27498_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27503_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27504_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27493_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27508_ADDR' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27510'.
  created $dff cell `$procdff$27560' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27508_DATA' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27510'.
  created $dff cell `$procdff$27561' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27508_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27510'.
  created $dff cell `$procdff$27562' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.\muxwre' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27509'.
  created direct connection (no actual register cell created).

19.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

19.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27534'.
Found and cleaned up 1 empty switch in `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27510'.
Removing empty process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27509'.
Cleaned up 1 empty switch.

19.42.8.12. Executing OPT_EXPR pass (perform const folding).

19.42.9. Executing PROC pass (convert processes to netlists).

19.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27580'.
Cleaned up 1 empty switch.

19.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27581 in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

19.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

19.42.9.4. Executing PROC_INIT pass (extract init attributes).

19.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

19.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

19.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27581'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27579_EN[3:0]$27585
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27579_DATA[3:0]$27587
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27579_ADDR[3:0]$27586
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27580'.

19.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

19.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.\i' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27575_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27569_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27563_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27564_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27565_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27566_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27570_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27571_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27572_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27576_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27577_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27567_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27578_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27568_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27573_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27574_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27579_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27581'.
  created $dff cell `$procdff$27631' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27579_ADDR' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27581'.
  created $dff cell `$procdff$27632' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27579_DATA' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27581'.
  created $dff cell `$procdff$27633' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27580'.
  created direct connection (no actual register cell created).

19.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

19.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27605'.
Found and cleaned up 1 empty switch in `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27581'.
Removing empty process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27580'.
Cleaned up 1 empty switch.

19.42.9.12. Executing OPT_EXPR pass (perform const folding).

19.42.10. Executing PROC pass (convert processes to netlists).

19.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27651'.
Cleaned up 1 empty switch.

19.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27652 in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

19.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

19.42.10.4. Executing PROC_INIT pass (extract init attributes).

19.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

19.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

19.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27652'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27650_EN[3:0]$27658
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27650_DATA[3:0]$27656
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27650_ADDR[3:0]$27657
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27651'.

19.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

19.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.\i' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27645_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27639_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27634_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27635_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27641_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27640_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27636_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27648_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27637_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27646_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27647_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27642_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27638_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27644_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27643_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27649_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27650_DATA' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27652'.
  created $dff cell `$procdff$27702' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27650_ADDR' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27652'.
  created $dff cell `$procdff$27703' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27650_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27652'.
  created $dff cell `$procdff$27704' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27651'.
  created direct connection (no actual register cell created).

19.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

19.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27676'.
Found and cleaned up 1 empty switch in `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27652'.
Removing empty process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27651'.
Cleaned up 1 empty switch.

19.42.10.12. Executing OPT_EXPR pass (perform const folding).

19.42.11. Executing PROC pass (convert processes to netlists).

19.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27722'.
Cleaned up 1 empty switch.

19.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27723 in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

19.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

19.42.11.4. Executing PROC_INIT pass (extract init attributes).

19.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

19.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

19.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27723'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27721_EN[3:0]$27729
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27721_DATA[3:0]$27728
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27721_ADDR[3:0]$27727
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27722'.

19.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

19.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.\i' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27719_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27714_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27709_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27705_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27706_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27710_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27711_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27715_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27707_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27716_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27720_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27712_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27708_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27717_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27713_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27718_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27721_ADDR' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27723'.
  created $dff cell `$procdff$27773' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27721_DATA' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27723'.
  created $dff cell `$procdff$27774' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27721_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27723'.
  created $dff cell `$procdff$27775' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27722'.
  created direct connection (no actual register cell created).

19.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

19.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27747'.
Found and cleaned up 1 empty switch in `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27723'.
Removing empty process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27722'.
Cleaned up 1 empty switch.

19.42.11.12. Executing OPT_EXPR pass (perform const folding).

19.42.12. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$11553.$auto$simplemap.cc:267:simplemap_mux$27061
Found an SCC: $techmap$auto$ff.cc:266:slice$11552.$auto$simplemap.cc:267:simplemap_mux$27061
Found an SCC: $techmap$auto$ff.cc:266:slice$11551.$auto$simplemap.cc:267:simplemap_mux$27061
Found an SCC: $techmap$auto$ff.cc:266:slice$11550.$auto$simplemap.cc:267:simplemap_mux$27061
Found an SCC: $auto$simplemap.cc:38:simplemap_not$23618 $auto$ff.cc:266:slice$7380 $auto$simplemap.cc:126:simplemap_reduce$7597 $auto$simplemap.cc:126:simplemap_reduce$7582 $auto$ff.cc:266:slice$7381 $auto$ff.cc:266:slice$7382 $auto$opt_expr.cc:613:replace_const_cells$25049 $auto$simplemap.cc:267:simplemap_mux$13398 $auto$simplemap.cc:126:simplemap_reduce$13416 $auto$simplemap.cc:126:simplemap_reduce$13413 $auto$simplemap.cc:75:simplemap_bitop$13399 $auto$opt_expr.cc:613:replace_const_cells$25253 $auto$simplemap.cc:225:simplemap_logbin$7572 $auto$simplemap.cc:196:simplemap_lognot$7587 $auto$simplemap.cc:126:simplemap_reduce$7585 $auto$simplemap.cc:126:simplemap_reduce$7583 $auto$simplemap.cc:126:simplemap_reduce$13408 $auto$simplemap.cc:75:simplemap_bitop$13401 $auto$simplemap.cc:196:simplemap_lognot$7602 $auto$simplemap.cc:126:simplemap_reduce$7600 $auto$simplemap.cc:126:simplemap_reduce$7598 $auto$opt_expr.cc:613:replace_const_cells$24993 $auto$ff.cc:266:slice$7383 $auto$simplemap.cc:126:simplemap_reduce$7353 $auto$simplemap.cc:126:simplemap_reduce$7351 $auto$simplemap.cc:225:simplemap_logbin$7551 $auto$simplemap.cc:196:simplemap_lognot$7561 $auto$simplemap.cc:126:simplemap_reduce$7559 $auto$opt_expr.cc:613:replace_const_cells$25037 $auto$simplemap.cc:267:simplemap_mux$13397 $auto$simplemap.cc:126:simplemap_reduce$13411
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$4019 $auto$simplemap.cc:126:simplemap_reduce$11036 $auto$simplemap.cc:126:simplemap_reduce$11034 $auto$simplemap.cc:126:simplemap_reduce$4022 $auto$simplemap.cc:126:simplemap_reduce$4020 $auto$simplemap.cc:38:simplemap_not$4720 $auto$ff.cc:266:slice$7881 $auto$ff.cc:479:convert_ce_over_srst$25765 $auto$ff.cc:266:slice$7880 $auto$ff.cc:479:convert_ce_over_srst$25763 $auto$simplemap.cc:38:simplemap_not$23649 $auto$ff.cc:266:slice$7879 $auto$ff.cc:479:convert_ce_over_srst$25761 $auto$simplemap.cc:126:simplemap_reduce$4713 $auto$ff.cc:266:slice$7878 $auto$ff.cc:479:convert_ce_over_srst$25759 $auto$simplemap.cc:38:simplemap_not$23647 $auto$ff.cc:266:slice$7877 $auto$ff.cc:479:convert_ce_over_srst$25757 $auto$simplemap.cc:38:simplemap_not$4003 $auto$alumacc.cc:485:replace_alu$2584.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$2584.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2584.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$4716 $auto$simplemap.cc:126:simplemap_reduce$4712 $auto$simplemap.cc:38:simplemap_not$23646 $auto$ff.cc:266:slice$7876 $auto$ff.cc:479:convert_ce_over_srst$25755 $auto$simplemap.cc:126:simplemap_reduce$10453 $auto$simplemap.cc:75:simplemap_bitop$4719 $auto$simplemap.cc:126:simplemap_reduce$4718 $auto$simplemap.cc:126:simplemap_reduce$4714 $auto$simplemap.cc:38:simplemap_not$23651
Found an SCC: $auto$simplemap.cc:38:simplemap_not$13337 $auto$ff.cc:266:slice$7393 $auto$ff.cc:266:slice$7391 $auto$simplemap.cc:126:simplemap_reduce$7624 $auto$ff.cc:266:slice$7390 $auto$ff.cc:266:slice$7396 $auto$simplemap.cc:38:simplemap_not$13339 $auto$ff.cc:266:slice$7395 $auto$simplemap.cc:126:simplemap_reduce$7625 $auto$ff.cc:266:slice$7392 $auto$simplemap.cc:38:simplemap_not$13333 $auto$ff.cc:266:slice$7389 $auto$simplemap.cc:126:simplemap_reduce$7630 $auto$simplemap.cc:126:simplemap_reduce$7626 $auto$ff.cc:266:slice$7394 $auto$ff.cc:266:slice$7384 $auto$simplemap.cc:126:simplemap_reduce$7621 $auto$ff.cc:266:slice$7385 $auto$simplemap.cc:38:simplemap_not$13331 $auto$ff.cc:266:slice$7387 $auto$simplemap.cc:126:simplemap_reduce$7628 $auto$simplemap.cc:126:simplemap_reduce$7622 $auto$simplemap.cc:38:simplemap_not$13330 $auto$ff.cc:266:slice$7386 $auto$simplemap.cc:126:simplemap_reduce$7632 $auto$simplemap.cc:126:simplemap_reduce$7629 $auto$simplemap.cc:126:simplemap_reduce$7623 $auto$ff.cc:266:slice$7388 $auto$simplemap.cc:167:logic_reduce$4668 $auto$simplemap.cc:196:simplemap_lognot$7637 $auto$simplemap.cc:126:simplemap_reduce$7635 $auto$simplemap.cc:126:simplemap_reduce$7633
Found an SCC: $auto$simplemap.cc:38:simplemap_not$17198 $auto$ff.cc:266:slice$4229 $auto$ff.cc:266:slice$4235 $auto$ff.cc:266:slice$4237 $auto$simplemap.cc:38:simplemap_not$17202 $auto$ff.cc:266:slice$4233 $auto$simplemap.cc:38:simplemap_not$17201 $auto$ff.cc:266:slice$4232 $auto$ff.cc:266:slice$4225 $auto$ff.cc:266:slice$4224 $auto$ff.cc:266:slice$4228 $auto$simplemap.cc:38:simplemap_not$17209 $auto$ff.cc:266:slice$4240 $auto$simplemap.cc:126:simplemap_reduce$7107 $auto$simplemap.cc:38:simplemap_not$17200 $auto$ff.cc:266:slice$4231 $auto$simplemap.cc:38:simplemap_not$17215 $auto$ff.cc:266:slice$4246 $auto$simplemap.cc:38:simplemap_not$17221 $auto$ff.cc:266:slice$4252 $auto$alumacc.cc:485:replace_alu$2595.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7106 $auto$simplemap.cc:38:simplemap_not$17199 $auto$ff.cc:266:slice$4230 $auto$simplemap.cc:126:simplemap_reduce$7117 $auto$simplemap.cc:38:simplemap_not$17220 $auto$ff.cc:266:slice$4251 $auto$simplemap.cc:38:simplemap_not$17219 $auto$ff.cc:266:slice$4250 $auto$simplemap.cc:126:simplemap_reduce$7110 $auto$simplemap.cc:38:simplemap_not$17207 $auto$ff.cc:266:slice$4238 $auto$simplemap.cc:126:simplemap_reduce$7123 $auto$simplemap.cc:126:simplemap_reduce$7109 $auto$ff.cc:266:slice$4236 $auto$simplemap.cc:126:simplemap_reduce$7111 $auto$ff.cc:266:slice$4239 $auto$ff.cc:266:slice$4243 $auto$simplemap.cc:126:simplemap_reduce$7113 $auto$ff.cc:266:slice$4244 $auto$ff.cc:266:slice$4242 $auto$simplemap.cc:126:simplemap_reduce$7125 $auto$simplemap.cc:126:simplemap_reduce$7114 $auto$ff.cc:266:slice$4245 $auto$simplemap.cc:126:simplemap_reduce$7116 $auto$simplemap.cc:38:simplemap_not$17218 $auto$ff.cc:266:slice$4249 $auto$simplemap.cc:38:simplemap_not$17217 $auto$ff.cc:266:slice$4248 $auto$simplemap.cc:38:simplemap_not$17223 $auto$ff.cc:266:slice$4254 $auto$simplemap.cc:126:simplemap_reduce$7104 $auto$ff.cc:266:slice$4226 $auto$simplemap.cc:126:simplemap_reduce$7121 $auto$simplemap.cc:126:simplemap_reduce$7105 $auto$ff.cc:266:slice$4227 $auto$simplemap.cc:126:simplemap_reduce$7131 $auto$simplemap.cc:126:simplemap_reduce$7124 $auto$simplemap.cc:126:simplemap_reduce$7112 $auto$ff.cc:266:slice$4241 $auto$simplemap.cc:126:simplemap_reduce$7126 $auto$simplemap.cc:126:simplemap_reduce$7115 $auto$ff.cc:266:slice$4247 $auto$ff.cc:266:slice$4253 $auto$simplemap.cc:38:simplemap_not$4721 $auto$alumacc.cc:485:replace_alu$2595.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[18].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[16].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[10].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7130 $auto$simplemap.cc:126:simplemap_reduce$7122 $auto$simplemap.cc:126:simplemap_reduce$7108 $auto$ff.cc:266:slice$4234 $auto$simplemap.cc:126:simplemap_reduce$7134 $auto$simplemap.cc:126:simplemap_reduce$7129 $auto$simplemap.cc:126:simplemap_reduce$7120 $auto$simplemap.cc:126:simplemap_reduce$7103 $auto$ff.cc:266:slice$4223 $auto$simplemap.cc:126:simplemap_reduce$10472 $auto$simplemap.cc:126:simplemap_reduce$10470 $auto$simplemap.cc:126:simplemap_reduce$7137 $auto$simplemap.cc:126:simplemap_reduce$7135 $auto$simplemap.cc:126:simplemap_reduce$7132 $auto$simplemap.cc:126:simplemap_reduce$7127 $auto$simplemap.cc:126:simplemap_reduce$7118 $auto$simplemap.cc:38:simplemap_not$13238
Found 8 SCCs in module top.
Found 8 SCCs.

19.42.13. Executing ABC9_OPS pass (helper functions for ABC9).

19.42.14. Executing PROC pass (convert processes to netlists).

19.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

19.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

19.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

19.42.14.4. Executing PROC_INIT pass (extract init attributes).

19.42.14.5. Executing PROC_ARST pass (detect async resets in processes).

19.42.14.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

19.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

19.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches).

19.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs).

19.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

19.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

19.42.14.12. Executing OPT_EXPR pass (perform const folding).

19.42.15. Executing TECHMAP pass (map to technology primitives).

19.42.15.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

19.42.15.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~178 debug messages>

19.42.16. Executing OPT pass (performing simple optimizations).

19.42.16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Optimizing module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Optimizing module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Optimizing module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Optimizing module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Optimizing module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Optimizing module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.

19.42.16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

19.42.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

19.42.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Performed a total of 0 changes.

19.42.16.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

19.42.16.6. Executing OPT_DFF pass (perform DFF optimizations).

19.42.16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4..

19.42.16.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Optimizing module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Optimizing module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Optimizing module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Optimizing module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Optimizing module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Optimizing module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Optimizing module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.

19.42.16.9. Finished OPT passes. (There is nothing left to do.)

19.42.17. Executing TECHMAP pass (map to technology primitives).

19.42.17.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

19.42.17.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4 for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4 for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4 for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4 for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4 for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4 for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4 for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4 for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~523 debug messages>

19.42.18. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

19.42.19. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

19.42.20. Executing ABC9_OPS pass (helper functions for ABC9).

19.42.21. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

19.42.22. Executing TECHMAP pass (map to technology primitives).

19.42.22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

19.42.22.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~217 debug messages>

19.42.23. Executing OPT pass (performing simple optimizations).

19.42.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

19.42.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

19.42.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

19.42.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

19.42.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.42.23.6. Executing OPT_DFF pass (perform DFF optimizations).

19.42.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

19.42.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.42.23.9. Rerunning OPT passes. (Maybe there is more to do..)

19.42.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

19.42.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

19.42.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

19.42.23.13. Executing OPT_DFF pass (perform DFF optimizations).

19.42.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

19.42.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

19.42.23.16. Finished OPT passes. (There is nothing left to do.)

19.42.24. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

19.42.25. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 5939 cells with 33011 new cells, skipped 5662 cells.
  replaced 3 cell types:
    2854 $_OR_
      67 $_XOR_
    3018 $_MUX_
  not replaced 23 cell types:
     356 $_NOT_
    2797 $_AND_
    1291 TRELLIS_FF
       1 $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4
     504 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
       1 $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp
     504 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
     193 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $__ABC9_SCC_BREAKER
       1 $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4
       1 $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4
       1 $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4
       1 $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4
       1 $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4
       1 $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4
       1 $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4

19.42.25.1. Executing ABC9_OPS pass (helper functions for ABC9).

19.42.25.2. Executing ABC9_OPS pass (helper functions for ABC9).

19.42.25.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 14906 AND gates and 42574 wires from module `top' to a netlist network with 3350 inputs and 470 outputs.

19.42.25.4. Executing ABC9_EXE pass (technology mapping using ABC9).

19.42.25.5. Executing ABC9.
Sending interrupt signal to process
Aborted by Julio Nunes Avelar
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   3350/    470  and =   13749  lev =   47 (6.91)  mem = 0.35 MB  box = 705  bb = 512
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   3350/    470  and =   19979  lev =   62 (4.52)  mem = 0.41 MB  ch = 1409  box = 644  bb = 512
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   60. Obj =  140. Set =  636. CutMin = no
ABC: Node =   19979.  Ch =   987.  Total mem =    4.69 MB. Peak cut mem =    0.25 MB.
ABC: P:  Del = 6735.00.  Ar =   21167.0.  Edge =    23261.  Cut =   300969.  T =     0.07 sec
ABC: P:  Del = 6735.00.  Ar =   21358.0.  Edge =    23348.  Cut =   279733.  T =     0.07 sec
ABC: P:  Del = 6735.00.  Ar =    7881.0.  Edge =    18037.  Cut =   664046.  T =     0.15 sec
ABC: F:  Del = 6731.00.  Ar =    5675.0.  Edge =    15908.  Cut =   502023.  T =     0.12 sec
ABC: A:  Del = 6731.00.  Ar =    5307.0.  Edge =    15316.  Cut =   490868.  T =     0.20 sec
ABC: A:  Del = 6731.00.  Ar =    5289.0.  Edge =    15276.  Cut =   489705.  T =     0.20 sec
ABC: Total time =     0.81 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: Terminated
Warning: ABC: execution of command ""/eda/oss-cad-suite/lib/yosys-abc" -s -f /tmp/yosys-abc-0uMdir/abc.script 2>&1" failed: return code 143.

19.42.25.6. Executing AIGER frontend.
Terminated
script returned exit code 143
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
Stage "NextPNR" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
Stage "ECPPACK" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (openFPGAloader)
Stage "openFPGAloader" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: b057d8ea-9330-45b5-9dd7-0b5679f1c49b
Finished: ABORTED