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StepArgumentsStatus
Start of Pipeline - (14 sec in block)
node - (13 sec in block)
node block - (12 sec in block)
stage - (2.1 sec in block)git_clone
stage block (git_clone) - (1.8 sec in block)
sh - (0.41 sec in self)rm -Rf Risco-5/ build/
sh - (0.89 sec in self)git clone https://github.com/JN513/Risco-5
sh - (0.35 sec in self)cd Risco-5
stage - (8.6 sec in block)Yosys
stage block (Yosys) - (8.2 sec in block)
sh - (0.4 sec in self)mkdir -p build
sh - (7.6 sec in self) /eda/oss-cad-suite/bin/yosys -p " read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/clk_divider.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 "
stage - (0.56 sec in block)NextPNR
stage block (NextPNR) - (0.16 sec in block)
stage - (0.53 sec in block)ECPPACK
stage block (ECPPACK) - (0.13 sec in block)
stage - (0.39 sec in block)openFPGAloader
stage block (openFPGAloader) - (0.13 sec in block)