Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Warning: IO 'gpios[4]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[3]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[2]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[1]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[0]' is unconstrained in LPF and will be automatically placed
Info: Logic utilisation before packing:
Info: Total LUT4s: 8930/43848 20%
Info: logic LUTs: 5562/43848 12%
Info: carry LUTs: 296/43848 0%
Info: RAM LUTs: 2048/ 5481 37%
Info: RAMW LUTs: 1024/10962 9%
Info: Total DFFs: 1301/43848 2%
Info: Packing IOs..
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y.Y
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 276 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk_o to global network
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x3ea99aae
Info: Device utilisation:
Info: TRELLIS_IO: 17/ 245 6%
Info: DCCA: 2/ 56 3%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1301/43848 2%
Info: TRELLIS_COMB: 8989/43848 20%
Info: TRELLIS_RAMW: 512/ 5481 9%
Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 5397 cells, random placement wirelen = 456859.
Info: at initial placer iter 0, wirelen = 2210
Info: at initial placer iter 1, wirelen = 2219
Info: at initial placer iter 2, wirelen = 2000
Info: at initial placer iter 3, wirelen = 1920
Info: Running main analytical placer, max placement attempts per cell = 14636755.
Info: at iteration #1, type ALL: wirelen solved = 1907, spread = 64977, legal = 65872; time = 0.27s
Info: at iteration #2, type ALL: wirelen solved = 6941, spread = 46134, legal = 47227; time = 0.27s
Info: at iteration #3, type ALL: wirelen solved = 13303, spread = 43687, legal = 44857; time = 0.26s
Info: at iteration #4, type ALL: wirelen solved = 15340, spread = 44718, legal = 45448; time = 0.26s
Info: at iteration #5, type ALL: wirelen solved = 16947, spread = 42044, legal = 42961; time = 0.26s
Info: at iteration #6, type ALL: wirelen solved = 18202, spread = 39703, legal = 41014; time = 0.25s
Info: at iteration #7, type ALL: wirelen solved = 18225, spread = 38270, legal = 39449; time = 0.25s
Info: at iteration #8, type ALL: wirelen solved = 19188, spread = 39043, legal = 40011; time = 0.25s
Info: at iteration #9, type ALL: wirelen solved = 20411, spread = 41888, legal = 42503; time = 0.25s
Info: at iteration #10, type ALL: wirelen solved = 23068, spread = 40157, legal = 41081; time = 0.24s
Info: at iteration #11, type ALL: wirelen solved = 22444, spread = 40902, legal = 41396; time = 0.24s
Info: at iteration #12, type ALL: wirelen solved = 23390, spread = 39643, legal = 40444; time = 0.24s
Info: HeAP Placer Time: 5.12s
Info: of which solving equations: 3.20s
Info: of which spreading cells: 0.39s
Info: of which strict legalisation: 0.12s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 16804, wirelen = 39449
Info: at iteration #5: temp = 0.000000, timing cost = 9903, wirelen = 32365
Info: at iteration #10: temp = 0.000000, timing cost = 12787, wirelen = 30612
Info: at iteration #15: temp = 0.000000, timing cost = 14452, wirelen = 29790
Info: at iteration #20: temp = 0.000000, timing cost = 13972, wirelen = 29038
Info: at iteration #25: temp = 0.000000, timing cost = 13786, wirelen = 28787
Info: at iteration #30: temp = 0.000000, timing cost = 13664, wirelen = 28663
Info: at iteration #35: temp = 0.000000, timing cost = 13554, wirelen = 28626
Info: at iteration #40: temp = 0.000000, timing cost = 13566, wirelen = 28598
Info: at iteration #41: temp = 0.000000, timing cost = 13562, wirelen = 28594
Info: SA placement time 39.36s
Info: Max frequency for clock '$glbnet$clk_o': 29.17 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 142.80 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.82 ns
Info: Max delay <async> -> posedge $glbnet$clk_o : 10.84 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 13.96 ns
Info: Max delay posedge $glbnet$clk_o -> <async> : 12.52 ns
Info: Slack histogram:
Info: legend: * represents 98 endpoint(s)
Info: + represents [1,98) endpoint(s)
Info: [ 32997, 35476) |+
Info: [ 35476, 37955) |+
Info: [ 37955, 40434) |+
Info: [ 40434, 42913) |
Info: [ 42913, 45392) |
Info: [ 45392, 47871) |
Info: [ 47871, 50350) |+
Info: [ 50350, 52829) |+
Info: [ 52829, 55308) |+
Info: [ 55308, 57787) |****+
Info: [ 57787, 60266) |***************+
Info: [ 60266, 62745) |***********************************************+
Info: [ 62745, 65224) |************************************************************
Info: [ 65224, 67703) |******+
Info: [ 67703, 70182) |*+
Info: [ 70182, 72661) |+
Info: [ 72661, 75140) |****+
Info: [ 75140, 77619) |******+
Info: [ 77619, 80098) |**+
Info: [ 80098, 82577) |+
Info: Checksum: 0xf3f19479
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: routing clock net $glbnet$clk_o using global 1
Info: Routing..
Info: Setting up routing queue.
Info: Routing 43150 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 122 877 | 122 877 | 42885| 0.62 0.62|
Info: 2000 | 337 1662 | 215 785 | 42456| 0.15 0.77|
Info: 3000 | 551 2448 | 214 786 | 41986| 0.17 0.94|
Info: 4000 | 654 3345 | 103 897 | 42090| 0.13 1.07|
Info: 5000 | 734 4265 | 80 920 | 41829| 0.13 1.20|
Info: 6000 | 915 5084 | 181 819 | 41615| 0.19 1.38|
Info: 7000 | 1155 5844 | 240 760 | 41197| 0.17 1.55|
Info: 8000 | 1325 6674 | 170 830 | 40828| 0.16 1.71|
Info: 9000 | 1572 7427 | 247 753 | 40422| 0.17 1.88|
Info: 10000 | 1785 8214 | 213 787 | 39925| 0.17 2.05|
Info: 11000 | 1919 9080 | 134 866 | 39737| 0.16 2.21|
Info: 12000 | 2112 9887 | 193 807 | 39373| 0.16 2.37|
Info: 13000 | 2354 10645 | 242 758 | 39051| 0.18 2.55|
Info: 14000 | 2446 11553 | 92 908 | 38579| 0.16 2.72|
Info: 15000 | 2632 12367 | 186 814 | 38177| 0.18 2.89|
Info: 16000 | 2841 13158 | 209 791 | 37730| 0.18 3.07|
Info: 17000 | 3040 13959 | 199 801 | 37421| 0.18 3.25|
Info: 18000 | 3263 14736 | 223 777 | 37660| 0.18 3.43|
Info: 19000 | 3279 15720 | 16 984 | 37541| 0.14 3.56|
Info: 20000 | 3296 16703 | 17 983 | 37301| 0.13 3.69|
Info: 21000 | 3356 17643 | 60 940 | 37087| 0.14 3.83|
Info: 22000 | 3547 18452 | 191 809 | 37346| 0.18 4.02|
Info: 23000 | 3686 19313 | 139 861 | 36883| 0.15 4.17|
Info: 24000 | 3911 20088 | 225 775 | 36567| 0.18 4.34|
Info: 25000 | 4074 20925 | 163 837 | 36320| 0.17 4.52|
Info: 26000 | 4247 21752 | 173 827 | 36064| 0.18 4.70|
Info: 27000 | 4380 22619 | 133 867 | 35766| 0.15 4.85|
Info: 28000 | 4565 23434 | 185 815 | 35395| 0.19 5.04|
Info: 29000 | 4819 24180 | 254 746 | 37085| 0.18 5.22|
Info: 30000 | 4873 25126 | 54 946 | 36311| 0.14 5.36|
Info: 31000 | 4903 26096 | 30 970 | 35358| 0.15 5.51|
Info: 32000 | 5042 26957 | 139 861 | 37174| 0.18 5.69|
Info: 33000 | 5198 27801 | 156 844 | 36619| 0.17 5.87|
Info: 34000 | 5287 28712 | 89 911 | 35945| 0.19 6.06|
Info: 35000 | 5384 29615 | 97 903 | 35266| 0.18 6.24|
Info: 36000 | 5521 30478 | 137 863 | 35320| 0.19 6.43|
Info: 37000 | 5797 31202 | 276 724 | 34987| 0.19 6.62|
Info: 38000 | 6023 31976 | 226 774 | 34652| 0.19 6.81|
Info: 39000 | 6205 32794 | 182 818 | 34205| 0.18 6.98|
Info: 40000 | 6440 33559 | 235 765 | 33640| 0.19 7.17|
Info: 41000 | 6710 34289 | 270 730 | 33480| 0.20 7.38|
Info: 42000 | 6963 35036 | 253 747 | 33110| 0.20 7.58|
Info: 43000 | 7240 35759 | 277 723 | 32654| 0.21 7.78|
Info: 44000 | 7471 36528 | 231 769 | 32067| 0.20 7.98|
Info: 45000 | 7749 37250 | 278 722 | 31638| 0.20 8.19|
Info: 46000 | 7996 38003 | 247 753 | 31197| 0.20 8.39|
Info: 47000 | 8281 38718 | 285 715 | 30856| 0.21 8.60|
Info: 48000 | 8580 39419 | 299 701 | 30542| 0.21 8.81|
Info: 49000 | 8861 40138 | 281 719 | 30085| 0.21 9.02|
Info: 50000 | 9158 40841 | 297 703 | 29594| 0.22 9.24|
Info: 51000 | 9386 41613 | 228 772 | 29276| 0.21 9.44|
Info: 52000 | 9699 42300 | 313 687 | 28887| 0.21 9.65|
Info: 53000 | 9945 43054 | 246 754 | 28365| 0.20 9.86|
Info: 54000 | 10260 43739 | 315 685 | 28231| 0.22 10.08|
Info: 55000 | 10483 44516 | 223 777 | 27940| 0.21 10.28|
Info: 56000 | 10738 45261 | 255 745 | 27523| 0.22 10.50|
Info: 57000 | 11036 45963 | 298 702 | 27112| 0.25 10.75|
Info: 58000 | 11341 46658 | 305 695 | 26660| 0.23 10.98|
Info: 59000 | 11624 47375 | 283 717 | 26358| 0.21 11.18|
Info: 60000 | 11924 48075 | 300 700 | 26026| 0.23 11.42|
Info: 61000 | 12279 48720 | 355 645 | 25627| 0.22 11.64|
Info: 62000 | 12553 49446 | 274 726 | 25313| 0.23 11.86|
Info: 63000 | 12849 50150 | 296 704 | 25140| 0.25 12.11|
Info: 64000 | 13125 50874 | 276 724 | 24872| 0.24 12.35|
Info: 65000 | 13396 51603 | 271 729 | 24586| 0.22 12.57|
Info: 66000 | 13758 52241 | 362 638 | 24253| 0.24 12.81|
Info: 67000 | 14104 52895 | 346 654 | 23820| 0.23 13.04|
Info: 68000 | 14423 53576 | 319 681 | 23531| 0.24 13.29|
Info: 69000 | 14784 54215 | 361 639 | 23220| 0.23 13.52|
Info: 70000 | 15118 54881 | 334 666 | 22933| 0.24 13.76|
Info: 71000 | 15354 55645 | 236 764 | 23200| 0.22 13.98|
Info: 72000 | 15512 56487 | 158 842 | 22697| 0.23 14.21|
Info: 73000 | 15901 57098 | 389 611 | 22436| 0.24 14.46|
Info: 74000 | 16259 57740 | 358 642 | 22149| 0.25 14.71|
Info: 75000 | 16660 58339 | 401 599 | 21868| 0.25 14.96|
Info: 76000 | 16963 59036 | 303 697 | 21659| 0.24 15.20|
Info: 77000 | 17281 59718 | 318 682 | 21526| 0.26 15.45|
Info: 78000 | 17684 60315 | 403 597 | 21548| 0.24 15.70|
Info: 79000 | 17961 61038 | 277 723 | 21308| 0.24 15.94|
Info: 80000 | 18329 61670 | 368 632 | 20926| 0.24 16.18|
Info: 81000 | 18753 62246 | 424 576 | 20611| 0.24 16.42|
Info: 82000 | 19193 62806 | 440 560 | 20352| 0.25 16.67|
Info: 83000 | 19674 63325 | 481 519 | 20077| 0.26 16.93|
Info: 84000 | 20107 63892 | 433 567 | 19981| 0.26 17.19|
Info: 85000 | 20517 64482 | 410 590 | 19657| 0.26 17.45|
Info: 86000 | 21002 64997 | 485 515 | 19521| 0.26 17.72|
Info: 87000 | 21451 65548 | 449 551 | 19395| 0.24 17.96|
Info: 88000 | 21808 66191 | 357 643 | 19296| 0.23 18.19|
Info: 89000 | 22194 66805 | 386 614 | 19033| 0.26 18.45|
Info: 90000 | 22621 67378 | 427 573 | 18858| 0.27 18.72|
Info: 91000 | 23072 67927 | 451 549 | 18616| 0.25 18.96|
Info: 92000 | 23557 68442 | 485 515 | 18356| 0.26 19.23|
Info: 93000 | 23866 69133 | 309 691 | 19706| 0.24 19.47|
Info: 94000 | 24078 69921 | 212 788 | 19329| 0.26 19.73|
Info: 95000 | 24307 70692 | 229 771 | 18764| 0.26 19.99|
Info: 96000 | 24561 71438 | 254 746 | 18811| 0.26 20.25|
Info: 97000 | 24801 72198 | 240 760 | 18644| 0.25 20.51|
Info: 98000 | 25160 72839 | 359 641 | 18661| 0.25 20.76|
Info: 99000 | 25249 73750 | 89 911 | 19097| 0.22 20.98|
Info: 100000 | 25312 74687 | 63 937 | 18769| 0.23 21.21|
Info: 101000 | 25611 75388 | 299 701 | 18376| 0.26 21.47|
Info: 102000 | 26055 75944 | 444 556 | 18540| 0.27 21.74|
Info: 103000 | 26311 76688 | 256 744 | 18120| 0.23 21.97|
Info: 104000 | 26912 77087 | 601 399 | 17970| 0.26 22.23|
Info: 105000 | 27482 77517 | 570 430 | 17787| 0.27 22.50|
Info: 106000 | 28055 77944 | 573 427 | 17572| 0.24 22.74|
Info: 107000 | 28562 78437 | 507 493 | 17443| 0.25 23.00|
Info: 108000 | 29119 78880 | 557 443 | 17174| 0.26 23.25|
Info: 109000 | 29666 79333 | 547 453 | 16984| 0.26 23.51|
Info: 110000 | 30213 79786 | 547 453 | 16735| 0.24 23.75|
Info: 111000 | 30735 80264 | 522 478 | 16560| 0.26 24.01|
Info: 112000 | 31291 80708 | 556 444 | 16317| 0.25 24.26|
Info: 113000 | 31691 81308 | 400 600 | 16211| 0.25 24.51|
Info: 114000 | 32172 81827 | 481 519 | 15951| 0.24 24.76|
Info: 115000 | 32687 82312 | 515 485 | 15716| 0.26 25.02|
Info: 116000 | 33201 82775 | 514 463 | 15496| 0.28 25.30|
Info: 117000 | 33656 83252 | 455 477 | 15185| 0.24 25.53|
Info: 118000 | 34253 83601 | 597 349 | 14891| 0.24 25.77|
Info: 119000 | 34771 84030 | 518 429 | 14653| 0.25 26.03|
Info: 120000 | 35289 84454 | 518 424 | 14525| 0.25 26.28|
Info: 121000 | 35748 84946 | 459 492 | 14254| 0.26 26.54|
Info: 122000 | 36290 85377 | 542 431 | 14070| 0.25 26.79|
Info: 123000 | 36722 85886 | 432 509 | 13849| 0.24 27.03|
Info: 124000 | 37235 86326 | 513 440 | 13549| 0.24 27.27|
Info: 125000 | 37732 86794 | 497 468 | 13335| 0.26 27.53|
Info: 126000 | 38248 87248 | 516 454 | 13193| 0.26 27.79|
Info: 127000 | 38765 87677 | 517 429 | 12917| 0.25 28.04|
Info: 128000 | 39331 88045 | 566 368 | 12597| 0.29 28.33|
Info: 129000 | 39849 88490 | 518 445 | 12414| 0.27 28.60|
Info: 130000 | 40303 89018 | 454 528 | 12269| 0.28 28.88|
Info: 131000 | 40815 89464 | 512 446 | 11951| 0.25 29.13|
Info: 132000 | 41146 90037 | 331 573 | 11599| 0.25 29.39|
Info: 133000 | 41410 90721 | 264 684 | 10934| 0.22 29.60|
Info: 134000 | 41510 91608 | 100 887 | 10056| 0.13 29.73|
Info: 135000 | 41566 92551 | 56 943 | 9129| 0.10 29.83|
Info: 136000 | 41605 93511 | 39 960 | 8171| 0.09 29.92|
Info: 137000 | 41639 94473 | 34 962 | 7208| 0.09 30.01|
Info: 138000 | 41683 95426 | 44 953 | 6262| 0.10 30.12|
Info: 139000 | 41787 96317 | 104 891 | 5426| 0.14 30.26|
Info: 140000 | 41921 97175 | 134 858 | 4575| 0.14 30.40|
Info: 141000 | 42271 97821 | 350 646 | 4079| 0.24 30.64|
Info: 142000 | 42669 98418 | 398 597 | 3612| 0.28 30.92|
Info: 143000 | 43062 99008 | 393 590 | 3146| 0.27 31.20|
Info: 144000 | 43527 99533 | 465 525 | 2772| 0.33 31.52|
Info: 145000 | 43996 100055 | 469 522 | 2378| 0.30 31.82|
Info: 146000 | 44420 100608 | 424 553 | 1993| 0.29 32.11|
Info: 147000 | 44834 101188 | 414 580 | 1564| 0.31 32.42|
Info: 148000 | 45327 101693 | 493 505 | 1211| 0.32 32.74|
Info: 149000 | 45858 102162 | 531 469 | 919| 0.33 33.08|
Info: 150000 | 46389 102622 | 531 460 | 802| 0.35 33.43|
Info: 151000 | 46676 103062 | 287 440 | 191| 0.34 33.77|
Info: 151244 | 46712 103137 | 36 75 | 0| 0.11 33.88|
Info: Routing complete.
Info: Router1 time 33.88s
Info: Checksum: 0x1a82f7e6
Info: Critical path report for clock '$glbnet$clk_o' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_2.Q
Info: 0.8 1.4 Net SOC.Core.Control_Unit.state[0] (46,29) -> (46,29)
Info: Sink SOC.Bus.slave_1_write_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_1.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/core/core.v:97.14-113.2
Info: Risco-5/src/core/control_unit.v:25.11-25.16
Info: Risco-5/src/peripheral/soc.v:28.3-36.2
Info: 0.2 1.6 Source SOC.Bus.slave_1_write_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_1.F
Info: 1.0 2.6 Net SOC.Bus.slave_1_write_LUT4_Z_B_PFUMX_Z_C0[4] (46,29) -> (47,23)
Info: Sink SOC.Bus.slave_1_write_LUT4_Z_B_PFUMX_Z_C0_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.9 Source SOC.Bus.slave_1_write_LUT4_Z_B_PFUMX_Z_C0_LUT4_C.F
Info: 1.9 4.8 Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[1] (47,23) -> (43,12)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.0 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.F
Info: 1.5 6.5 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (43,12) -> (42,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.B
Info: 0.4 7.0 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.0 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.0 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.0 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (42,16) -> (42,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.0 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.0 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.0 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.0 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (42,16) -> (42,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.1 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.1 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.1 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.1 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (42,16) -> (43,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.2 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.2 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.2 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.2 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (43,16) -> (43,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.2 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.2 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.2 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.2 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (43,16) -> (43,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.3 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.3 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.3 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.3 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (43,16) -> (43,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.4 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.4 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.4 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.4 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (43,16) -> (44,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.5 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.5 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (44,16) -> (44,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.5 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.5 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (44,16) -> (44,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.5 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.5 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (44,16) -> (44,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.5 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.5 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (44,16) -> (44,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.6 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.6 Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (44,16) -> (44,16)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.6 Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.6 Net $nextpnr_CCU2C_15$CIN (44,16) -> (44,16)
Info: Sink $nextpnr_CCU2C_15$CCU2_COMB0.FCI
Info: 0.4 8.0 Source $nextpnr_CCU2C_15$CCU2_COMB0.F
Info: 1.8 9.9 Net SOC.Bus.slave_1_write_LUT4_Z_B[1] (44,16) -> (25,17)
Info: Sink SOC.Memory.address_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.1 Source SOC.Memory.address_LUT4_Z_2.F
Info: 2.0 12.1 Net SOC.slave_address[3] (25,17) -> (15,16)
Info: Sink SOC.Memory.memory.0.174$DPRAM_COMB1.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/soc.v:21.5-21.18
Info: 0.2 12.3 Source SOC.Memory.memory.0.174$DPRAM_COMB1.F
Info: 0.9 13.2 Net SOC.Memory.memory.0.158_DO[2] (15,16) -> (14,16)
Info: Sink SOC.Memory.memory.0.150_DO_2_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.4 Source SOC.Memory.memory.0.150_DO_2_LUT4_Z.F
Info: 0.7 14.2 Net SOC.Memory.memory.0.150_DO_2[4] (14,16) -> (14,15)
Info: Sink SOC.Memory.memory.0.190_DO_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 14.4 Source SOC.Memory.memory.0.190_DO_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.6 15.0 Net SOC.Memory.memory.0.190_DO[3] (14,15) -> (13,15)
Info: Sink SOC.Memory.memory.0.134_DO_2_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 15.3 Source SOC.Memory.memory.0.134_DO_2_LUT4_Z_1.F
Info: 0.5 15.7 Net SOC.Memory.memory.0.134_DO_2[3] (13,15) -> (13,14)
Info: Sink SOC.Memory.memory.0.134_DO_2_LUT4_B.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 16.0 Source SOC.Memory.memory.0.134_DO_2_LUT4_B.F
Info: 1.1 17.0 Net SOC.Memory.memory.0.126_DO_LUT4_B_Z[4] (13,14) -> (17,13)
Info: Sink SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 17.3 Source SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 17.3 Net SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_SD_L6MUX21_Z_D1 (17,13) -> (17,13)
Info: Sink SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 17.5 Source SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.5 19.0 Net SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_SD[5] (17,13) -> (21,17)
Info: Sink SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 19.3 Source SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 2.1 21.4 Net SOC.Core.read_data_LUT4_Z_16_D[2] (21,17) -> (42,21)
Info: Sink SOC.Core.read_data_LUT4_Z_16.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 21.7 Source SOC.Core.read_data_LUT4_Z_16.F
Info: 1.3 22.9 Net SOC.read_data[25] (42,21) -> (42,27)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_6.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/soc.v:20.34-20.43
Info: 0.0 22.9 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_6.M
Info: 5.2 ns logic, 17.7 ns routing
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source ClkDivider.clk_counter_TRELLIS_FF_Q_26.Q
Info: 1.1 1.7 Net reset_LUT4_B_C_LUT4_Z_1_D_PFUMX_Z_C0[0] (17,3) -> (18,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 2.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (18,2) -> (18,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (18,2) -> (18,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.2 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.2 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (18,2) -> (18,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.2 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.2 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (18,2) -> (18,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (18,2) -> (18,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (18,2) -> (19,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (19,2) -> (19,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (19,2) -> (19,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.4 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.4 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (19,2) -> (19,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.4 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.4 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (19,2) -> (19,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (19,2) -> (19,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (19,2) -> (19,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (19,2) -> (19,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (19,2) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (20,2) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (20,2) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.7 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.7 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (20,2) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.7 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.7 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (20,2) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (20,2) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (20,2) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (20,2) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (20,2) -> (21,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.9 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.9 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (21,2) -> (21,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.9 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.9 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN (21,2) -> (21,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 3.0 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (21,2) -> (21,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 3.0 Net $nextpnr_CCU2C_1$CIN (21,2) -> (21,2)
Info: Sink $nextpnr_CCU2C_1$CCU2_COMB0.FCI
Info: 0.4 3.4 Source $nextpnr_CCU2C_1$CCU2_COMB0.F
Info: 0.9 4.3 Net reset_LUT4_B_C_LUT4_Z_D[1] (21,2) -> (21,3)
Info: Sink reset_LUT4_B_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.5 Source reset_LUT4_B_C_LUT4_Z.F
Info: 0.9 5.5 Net reset_LUT4_B_C[1] (21,3) -> (19,4)
Info: Sink reset_LUT4_B.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.7 Source reset_LUT4_B.F
Info: 0.9 6.6 Net reset_LUT4_B_Z (19,4) -> (16,3)
Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info: 0.4 7.0 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info: 3.2 ns logic, 3.8 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source reset$tr_io.O
Info: 2.6 2.6 Net reset$TRELLIS_IO_IN (0,29) -> (19,4)
Info: Sink reset_LUT4_B.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.8 Source reset_LUT4_B.F
Info: 0.9 3.7 Net reset_LUT4_B_Z (19,4) -> (16,3)
Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info: 0.4 4.1 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info: 0.7 ns logic, 3.5 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk_o':
Info: curr total
Info: 0.0 0.0 Source gpios[3]$tr_io.O
Info: 1.8 1.8 Net gpios[3]$TRELLIS_IO_IN (56,0) -> (44,7)
Info: Sink SOC.GPIOS.Gpios[3].direction_LUT4_B.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 2.1 Source SOC.GPIOS.Gpios[3].direction_LUT4_B.F
Info: 0.0 2.1 Net SOC.GPIOS.Gpios[3].direction_LUT4_B_Z (44,7) -> (44,7)
Info: Sink SOC.GPIOS.Gpios[3].direction_LUT4_B_Z_PFUMX_ALUT_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info: 0.2 2.2 Source SOC.GPIOS.Gpios[3].direction_LUT4_B_Z_PFUMX_ALUT_BLUT_LUT4_Z.OFX
Info: 1.4 3.6 Net SOC.GPIOS.Gpios[3].direction_LUT4_B_Z_PFUMX_ALUT_Z[1] (44,7) -> (39,8)
Info: Sink SOC.Core.read_data_LUT4_Z_2.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.9 Source SOC.Core.read_data_LUT4_Z_2.F
Info: 2.2 6.1 Net SOC.read_data[3] (39,8) -> (42,29)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_28.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/soc.v:20.34-20.43
Info: 0.0 6.1 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_28.M
Info: 0.6 ns logic, 5.5 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source ClkDivider.clk_o_auto_TRELLIS_FF_Q.Q
Info: 3.5 4.0 Net clk_o (20,4) -> (64,7)
Info: Sink led_LUT4_Z_1.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:10.6-10.11
Info: 0.2 4.3 Source led_LUT4_Z_1.F
Info: 2.5 6.8 Net led[7]$TRELLIS_IO_OUT (64,7) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.0 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk_o' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_31.Q
Info: 2.3 2.8 Net SOC.Leds.data[0] (42,28) -> (17,32)
Info: Sink led_LUT4_Z_3.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: Risco-5/src/peripheral/soc.v:83.6-92.2
Info: 0.2 3.1 Source led_LUT4_Z_3.F
Info: 3.4 6.5 Net led[0]$TRELLIS_IO_OUT (17,32) -> (0,59)
Info: Sink led[0]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.7 ns routing
Info: Max frequency for clock '$glbnet$clk_o': 43.63 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 143.12 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.11 ns
Info: Max delay <async> -> posedge $glbnet$clk_o : 6.11 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.76 ns
Info: Max delay posedge $glbnet$clk_o -> <async> : 6.49 ns
Info: Slack histogram:
Info: legend: * represents 164 endpoint(s)
Info: + represents [1,164) endpoint(s)
Info: [ 33013, 35474) |+
Info: [ 35474, 37935) |+
Info: [ 37935, 40396) |+
Info: [ 40396, 42857) |
Info: [ 42857, 45318) |
Info: [ 45318, 47779) |
Info: [ 47779, 50240) |
Info: [ 50240, 52701) |
Info: [ 52701, 55162) |
Info: [ 55162, 57623) |
Info: [ 57623, 60084) |
Info: [ 60084, 62545) |+
Info: [ 62545, 65006) |+
Info: [ 65006, 67467) |+
Info: [ 67467, 69928) |***************+
Info: [ 69928, 72389) |************************************************************
Info: [ 72389, 74850) |*****+
Info: [ 74850, 77311) |*+
Info: [ 77311, 79772) |******+
Info: [ 79772, 82233) |+
5 warnings, 0 errors
Info: Program finished normally.
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