Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained --ignore-loops
Info: constraining clock net 'clk' to 25.00 MHz
Warning: IO 'gpios[4]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[3]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[2]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[1]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[0]' is unconstrained in LPF and will be automatically placed
Info: Logic utilisation before packing:
Info: Total LUT4s: 8860/43848 20%
Info: logic LUTs: 5460/43848 12%
Info: carry LUTs: 328/43848 0%
Info: RAM LUTs: 2048/ 5481 37%
Info: RAMW LUTs: 1024/10962 9%
Info: Total DFFs: 1302/43848 2%
Info: Packing IOs..
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y.Y
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 286 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk_o to global network
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xd3654adc
Info: Device utilisation:
Info: TRELLIS_IO: 17/ 245 6%
Info: DCCA: 2/ 56 3%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1302/43848 2%
Info: TRELLIS_COMB: 8923/43848 20%
Info: TRELLIS_RAMW: 512/ 5481 9%
Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 5411 cells, random placement wirelen = 450833.
Info: at initial placer iter 0, wirelen = 2388
Info: at initial placer iter 1, wirelen = 1982
Info: at initial placer iter 2, wirelen = 1985
Info: at initial placer iter 3, wirelen = 2209
Info: Running main analytical placer, max placement attempts per cell = 14461442.
Info: at iteration #1, type ALL: wirelen solved = 2086, spread = 62956, legal = 63809; time = 0.28s
Info: at iteration #2, type ALL: wirelen solved = 8541, spread = 44241, legal = 45172; time = 0.26s
Info: at iteration #3, type ALL: wirelen solved = 12325, spread = 44589, legal = 45745; time = 0.26s
Info: at iteration #4, type ALL: wirelen solved = 15098, spread = 42260, legal = 43688; time = 0.26s
Info: at iteration #5, type ALL: wirelen solved = 16764, spread = 40788, legal = 41860; time = 0.25s
Info: at iteration #6, type ALL: wirelen solved = 18622, spread = 39265, legal = 40611; time = 0.25s
Info: at iteration #7, type ALL: wirelen solved = 18717, spread = 37122, legal = 38625; time = 0.25s
Info: at iteration #8, type ALL: wirelen solved = 19960, spread = 36213, legal = 37663; time = 0.24s
Info: at iteration #9, type ALL: wirelen solved = 19982, spread = 36577, legal = 37678; time = 0.24s
Info: at iteration #10, type ALL: wirelen solved = 21072, spread = 39131, legal = 39970; time = 0.24s
Info: at iteration #11, type ALL: wirelen solved = 23016, spread = 36770, legal = 37800; time = 0.24s
Info: at iteration #12, type ALL: wirelen solved = 22548, spread = 37723, legal = 38801; time = 0.24s
Info: at iteration #13, type ALL: wirelen solved = 23367, spread = 36904, legal = 38037; time = 0.24s
Info: HeAP Placer Time: 5.45s
Info: of which solving equations: 3.37s
Info: of which spreading cells: 0.44s
Info: of which strict legalisation: 0.14s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 10170, wirelen = 37663
Info: at iteration #5: temp = 0.000000, timing cost = 12672, wirelen = 31387
Info: at iteration #10: temp = 0.000000, timing cost = 10005, wirelen = 29798
Info: at iteration #15: temp = 0.000000, timing cost = 12545, wirelen = 29047
Info: at iteration #20: temp = 0.000000, timing cost = 11405, wirelen = 28311
Info: at iteration #24: temp = 0.000000, timing cost = 12142, wirelen = 28149
Info: SA placement time 23.51s
Info: Max frequency for clock '$glbnet$clk_o': 31.32 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 162.26 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.94 ns
Info: Max delay <async> -> posedge $glbnet$clk_o : 9.28 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 14.08 ns
Info: Max delay posedge $glbnet$clk_o -> <async> : 12.88 ns
Info: Slack histogram:
Info: legend: * represents 105 endpoint(s)
Info: + represents [1,105) endpoint(s)
Info: [ 33837, 36274) |+
Info: [ 36274, 38711) |+
Info: [ 38711, 41148) |+
Info: [ 41148, 43585) |
Info: [ 43585, 46022) |
Info: [ 46022, 48459) |
Info: [ 48459, 50896) |
Info: [ 50896, 53333) |+
Info: [ 53333, 55770) |+
Info: [ 55770, 58207) |+
Info: [ 58207, 60644) |*********+
Info: [ 60644, 63081) |******************+
Info: [ 63081, 65518) |*****************************+
Info: [ 65518, 67955) |************************************************************
Info: [ 67955, 70392) |******+
Info: [ 70392, 72829) |*****+
Info: [ 72829, 75266) |*******+
Info: [ 75266, 77703) |**+
Info: [ 77703, 80140) |+
Info: [ 80140, 82577) |+
Info: Checksum: 0xfc78a960
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: routing clock net $glbnet$clk_o using global 1
Info: Routing..
Info: Setting up routing queue.
Info: Routing 43111 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 263 736 | 263 736 | 42533| 0.73 0.73|
Info: 2000 | 451 1548 | 188 812 | 42002| 0.15 0.89|
Info: 3000 | 713 2286 | 262 738 | 41422| 0.17 1.06|
Info: 4000 | 810 3189 | 97 903 | 41293| 0.14 1.20|
Info: 5000 | 951 4048 | 141 859 | 40686| 0.15 1.35|
Info: 6000 | 1157 4842 | 206 794 | 40070| 0.16 1.51|
Info: 7000 | 1357 5642 | 200 800 | 39483| 0.16 1.67|
Info: 8000 | 1544 6455 | 187 813 | 38967| 0.16 1.84|
Info: 9000 | 1742 7257 | 198 802 | 38325| 0.17 2.00|
Info: 10000 | 1899 8100 | 157 843 | 38133| 0.17 2.17|
Info: 11000 | 2064 8935 | 165 835 | 37758| 0.17 2.34|
Info: 12000 | 2293 9706 | 229 771 | 37212| 0.18 2.52|
Info: 13000 | 2530 10469 | 237 763 | 36756| 0.17 2.69|
Info: 14000 | 2809 11190 | 279 721 | 36365| 0.19 2.88|
Info: 15000 | 2958 12041 | 149 851 | 36156| 0.16 3.04|
Info: 16000 | 3151 12848 | 193 807 | 35764| 0.17 3.22|
Info: 17000 | 3328 13671 | 177 823 | 35429| 0.18 3.39|
Info: 18000 | 3568 14431 | 240 760 | 34908| 0.20 3.59|
Info: 19000 | 3842 15157 | 274 726 | 34516| 0.19 3.78|
Info: 20000 | 4044 15955 | 202 798 | 34264| 0.18 3.96|
Info: 21000 | 4296 16703 | 252 748 | 33777| 0.18 4.15|
Info: 22000 | 4522 17477 | 226 774 | 33463| 0.19 4.33|
Info: 23000 | 4754 18245 | 232 768 | 33236| 0.19 4.52|
Info: 24000 | 5009 18990 | 255 745 | 32781| 0.19 4.71|
Info: 25000 | 5323 19676 | 314 686 | 32448| 0.22 4.94|
Info: 26000 | 5595 20404 | 272 728 | 32330| 0.22 5.15|
Info: 27000 | 5854 21145 | 259 741 | 32090| 0.19 5.35|
Info: 28000 | 6092 21907 | 238 762 | 31594| 0.20 5.55|
Info: 29000 | 6370 22629 | 278 722 | 31187| 0.20 5.75|
Info: 30000 | 6660 23339 | 290 710 | 30854| 0.21 5.96|
Info: 31000 | 6962 24037 | 302 698 | 30599| 0.21 6.17|
Info: 32000 | 7123 24876 | 161 839 | 30475| 0.19 6.36|
Info: 33000 | 7417 25582 | 294 706 | 30030| 0.21 6.57|
Info: 34000 | 7756 26243 | 339 661 | 29778| 0.24 6.81|
Info: 35000 | 8044 26955 | 288 712 | 29285| 0.20 7.01|
Info: 36000 | 8221 27778 | 177 823 | 29161| 0.20 7.22|
Info: 37000 | 8526 28473 | 305 695 | 28850| 0.22 7.43|
Info: 38000 | 8844 29155 | 318 682 | 28535| 0.22 7.66|
Info: 39000 | 9167 29832 | 323 677 | 28264| 0.23 7.89|
Info: 40000 | 9520 30479 | 353 647 | 27989| 0.23 8.12|
Info: 41000 | 9860 31139 | 340 660 | 27592| 0.24 8.36|
Info: 42000 | 10235 31764 | 375 625 | 27480| 0.28 8.64|
Info: 43000 | 10548 32451 | 313 687 | 27174| 0.21 8.85|
Info: 44000 | 10750 33249 | 202 798 | 27246| 0.21 9.05|
Info: 45000 | 11017 33982 | 267 733 | 26845| 0.23 9.28|
Info: 46000 | 11378 34621 | 361 639 | 26769| 0.26 9.55|
Info: 47000 | 11649 35350 | 271 729 | 26562| 0.23 9.77|
Info: 48000 | 11910 36089 | 261 739 | 26439| 0.24 10.01|
Info: 49000 | 12293 36706 | 383 617 | 26405| 0.29 10.30|
Info: 50000 | 12655 37344 | 362 638 | 26299| 0.25 10.55|
Info: 51000 | 12976 38023 | 321 679 | 26059| 0.23 10.78|
Info: 52000 | 13335 38664 | 359 641 | 25811| 0.27 11.05|
Info: 53000 | 13690 39309 | 355 645 | 25577| 0.26 11.31|
Info: 54000 | 13984 40015 | 294 706 | 25367| 0.28 11.58|
Info: 55000 | 14289 40710 | 305 695 | 25159| 0.23 11.81|
Info: 56000 | 14642 41357 | 353 647 | 25018| 0.26 12.07|
Info: 57000 | 14967 42032 | 325 675 | 24739| 0.28 12.35|
Info: 58000 | 15321 42678 | 354 646 | 24548| 0.26 12.62|
Info: 59000 | 15681 43318 | 360 640 | 24345| 0.25 12.87|
Info: 60000 | 16030 43969 | 349 651 | 24152| 0.29 13.16|
Info: 61000 | 16315 44684 | 285 715 | 23967| 0.24 13.39|
Info: 62000 | 16607 45392 | 292 708 | 23933| 0.27 13.66|
Info: 63000 | 16942 46057 | 335 665 | 23665| 0.30 13.96|
Info: 64000 | 17289 46710 | 347 653 | 23596| 0.24 14.21|
Info: 65000 | 17553 47446 | 264 736 | 23485| 0.22 14.42|
Info: 66000 | 17664 48335 | 111 889 | 23449| 0.20 14.62|
Info: 67000 | 17976 49023 | 312 688 | 23226| 0.29 14.91|
Info: 68000 | 18264 49735 | 288 712 | 23430| 0.27 15.18|
Info: 69000 | 18467 50532 | 203 797 | 23073| 0.22 15.40|
Info: 70000 | 18846 51153 | 379 621 | 22818| 0.29 15.69|
Info: 71000 | 19172 51827 | 326 674 | 22750| 0.31 16.00|
Info: 72000 | 19516 52483 | 344 656 | 22590| 0.28 16.28|
Info: 73000 | 19775 53224 | 259 741 | 22584| 0.24 16.53|
Info: 74000 | 19993 54006 | 218 782 | 22360| 0.24 16.76|
Info: 75000 | 20244 54755 | 251 749 | 22153| 0.23 16.99|
Info: 76000 | 20660 55339 | 416 584 | 21772| 0.26 17.24|
Info: 77000 | 21069 55930 | 409 591 | 21404| 0.25 17.49|
Info: 78000 | 21483 56516 | 414 586 | 21126| 0.27 17.76|
Info: 79000 | 21908 57091 | 425 575 | 20915| 0.32 18.09|
Info: 80000 | 22322 57677 | 414 586 | 20655| 0.25 18.34|
Info: 81000 | 22733 58266 | 411 589 | 20297| 0.25 18.59|
Info: 82000 | 23188 58811 | 455 545 | 20040| 0.27 18.87|
Info: 83000 | 23636 59363 | 448 552 | 19761| 0.28 19.15|
Info: 84000 | 24104 59895 | 468 532 | 19509| 0.28 19.43|
Info: 85000 | 24570 60429 | 466 534 | 19215| 0.28 19.71|
Info: 86000 | 25004 60995 | 434 566 | 19023| 0.29 20.00|
Info: 87000 | 25437 61562 | 433 567 | 18747| 0.26 20.26|
Info: 88000 | 25875 62124 | 438 562 | 18620| 0.28 20.54|
Info: 89000 | 26279 62720 | 404 596 | 18358| 0.25 20.79|
Info: 90000 | 26752 63247 | 473 527 | 18005| 0.26 21.05|
Info: 91000 | 27223 63776 | 471 529 | 17841| 0.27 21.32|
Info: 92000 | 27687 64312 | 464 536 | 17596| 0.26 21.58|
Info: 93000 | 28239 64760 | 552 448 | 17346| 0.26 21.84|
Info: 94000 | 28661 65338 | 422 578 | 17203| 0.26 22.11|
Info: 95000 | 29190 65809 | 529 471 | 17034| 0.26 22.36|
Info: 96000 | 29686 66313 | 496 504 | 16846| 0.29 22.65|
Info: 97000 | 30200 66799 | 514 486 | 16578| 0.25 22.90|
Info: 98000 | 30752 67247 | 552 448 | 16256| 0.26 23.16|
Info: 99000 | 31262 67737 | 510 490 | 16060| 0.26 23.42|
Info: 100000 | 31632 68367 | 370 630 | 15927| 0.23 23.65|
Info: 101000 | 31963 69036 | 331 669 | 16420| 0.23 23.88|
Info: 102000 | 32175 69824 | 212 788 | 15808| 0.23 24.11|
Info: 103000 | 32675 70324 | 500 500 | 15573| 0.29 24.40|
Info: 104000 | 33021 70978 | 346 654 | 16237| 0.24 24.64|
Info: 105000 | 33133 71866 | 112 888 | 15421| 0.23 24.88|
Info: 106000 | 33579 72400 | 446 534 | 15164| 0.26 25.13|
Info: 107000 | 34096 72876 | 517 476 | 14929| 0.27 25.40|
Info: 108000 | 34499 73411 | 403 535 | 14526| 0.25 25.66|
Info: 109000 | 34948 73878 | 449 467 | 14200| 0.24 25.89|
Info: 110000 | 35451 74332 | 503 454 | 14024| 0.30 26.19|
Info: 111000 | 35960 74749 | 509 417 | 13659| 0.24 26.43|
Info: 112000 | 36495 75145 | 535 396 | 13365| 0.25 26.68|
Info: 113000 | 36939 75614 | 444 469 | 12984| 0.29 26.98|
Info: 114000 | 37491 75995 | 552 381 | 12617| 0.25 27.22|
Info: 115000 | 37988 76419 | 497 424 | 12280| 0.24 27.46|
Info: 116000 | 38506 76841 | 518 422 | 11936| 0.24 27.71|
Info: 117000 | 39084 77223 | 578 382 | 11695| 0.26 27.97|
Info: 118000 | 39612 77669 | 528 446 | 11480| 0.27 28.24|
Info: 119000 | 40089 78186 | 477 517 | 11438| 0.28 28.51|
Info: 120000 | 40522 78719 | 433 533 | 11177| 0.28 28.80|
Info: 121000 | 40921 79271 | 399 552 | 10790| 0.27 29.07|
Info: 122000 | 41135 80011 | 214 740 | 10065| 0.20 29.27|
Info: 123000 | 41322 80815 | 187 804 | 9310| 0.16 29.42|
Info: 124000 | 41530 81601 | 208 786 | 8552| 0.18 29.61|
Info: 125000 | 41623 82507 | 93 906 | 7688| 0.12 29.73|
Info: 126000 | 41701 83427 | 78 920 | 6793| 0.13 29.86|
Info: 127000 | 41748 84380 | 47 953 | 5848| 0.10 29.96|
Info: 128000 | 41981 85131 | 233 751 | 5242| 0.23 30.19|
Info: 129000 | 42061 86046 | 80 915 | 4331| 0.11 30.30|
Info: 130000 | 42407 86700 | 346 654 | 3988| 0.34 30.64|
Info: 131000 | 42835 87272 | 428 572 | 3857| 0.48 31.12|
Info: 132000 | 43050 88055 | 215 783 | 3219| 0.23 31.35|
Info: 133000 | 43496 88607 | 446 552 | 2835| 0.32 31.67|
Info: 134000 | 43957 89135 | 461 528 | 2501| 0.32 31.99|
Info: 135000 | 44451 89625 | 494 490 | 2234| 0.34 32.33|
Info: 136000 | 44894 90169 | 443 544 | 1906| 0.36 32.69|
Info: 137000 | 45379 90678 | 485 509 | 1674| 0.38 33.07|
Info: 138000 | 45883 91174 | 504 496 | 1400| 0.43 33.50|
Info: 139000 | 46400 91655 | 517 481 | 1060| 0.37 33.87|
Info: 140000 | 46983 92072 | 583 417 | 880| 0.42 34.29|
Info: 141000 | 47492 92554 | 509 482 | 565| 0.39 34.69|
Info: 141590 | 47513 92760 | 21 206 | 0| 0.16 34.85|
Info: Routing complete.
Info: Router1 time 34.85s
Info: Checksum: 0x03cefe60
Info: Critical path report for clock '$glbnet$clk_o' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info: 1.7 2.2 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_3_B_LUT4_Z_B[1] (47,7) -> (52,8)
Info: Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/core/core.v:97.14-113.2
Info: Risco-5/src/core/control_unit.v:46.11-46.16
Info: Risco-5/src/peripheral/soc.v:28.3-36.2
Info: 0.2 2.4 Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info: 0.8 3.2 Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (52,8) -> (59,8)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.5 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_LUT4_Z.F
Info: 2.3 5.7 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0 (59,8) -> (49,16)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.B
Info: 0.4 6.2 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.2 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (49,16) -> (49,16)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.2 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.2 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (49,16) -> (49,16)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.3 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.3 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (49,16) -> (49,16)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.3 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.3 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (49,16) -> (49,16)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.3 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.3 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (49,16) -> (49,16)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.3 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.3 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (49,16) -> (50,16)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.4 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.4 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (50,16) -> (50,16)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.4 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.4 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (50,16) -> (50,16)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.5 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.5 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (50,16) -> (50,16)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.5 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.5 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (50,16) -> (50,16)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.5 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.5 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (50,16) -> (50,16)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.5 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.5 Net $nextpnr_CCU2C_5$CIN (50,16) -> (50,16)
Info: Sink $nextpnr_CCU2C_5$CCU2_COMB0.FCI
Info: 0.4 7.0 Source $nextpnr_CCU2C_5$CCU2_COMB0.F
Info: 1.9 8.9 Net SOC.Memory.address_LUT4_Z_1_C[1] (50,16) -> (27,18)
Info: Sink SOC.Memory.address_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 9.1 Source SOC.Memory.address_LUT4_Z.F
Info: 2.1 11.2 Net SOC.slave_address[5] (27,18) -> (21,6)
Info: Sink SOC.Memory.memory.0.62$DPRAM_COMB3.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/soc.v:21.5-21.18
Info: 0.2 11.5 Source SOC.Memory.memory.0.62$DPRAM_COMB3.F
Info: 0.8 12.3 Net SOC.Memory.memory.0.6_DO[2] (21,6) -> (22,6)
Info: Sink SOC.Memory.memory.0.30_DO_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 12.6 Source SOC.Memory.memory.0.30_DO_LUT4_Z.F
Info: 0.9 13.4 Net SOC.Memory.memory.0.30_DO[4] (22,6) -> (23,7)
Info: Sink SOC.Memory.memory.0.14_DO_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 13.7 Source SOC.Memory.memory.0.14_DO_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.8 14.5 Net SOC.Memory.memory.0.14_DO[3] (23,7) -> (23,8)
Info: Sink SOC.Memory.memory.0.14_DO_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 14.8 Source SOC.Memory.memory.0.14_DO_LUT4_C.F
Info: 0.9 15.6 Net SOC.Memory.memory.0.70_DO_LUT4_C_Z[2] (23,8) -> (23,9)
Info: Sink SOC.Memory.memory.0.70_DO_LUT4_C_Z_LUT4_A.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 15.9 Source SOC.Memory.memory.0.70_DO_LUT4_C_Z_LUT4_A.F
Info: 1.2 17.1 Net SOC.Core.read_data_LUT4_Z_22_C_LUT4_Z_1_D_LUT4_Z_B[3] (23,9) -> (30,9)
Info: Sink SOC.Core.read_data_LUT4_Z_22_C_LUT4_Z_1_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 17.3 Source SOC.Core.read_data_LUT4_Z_22_C_LUT4_Z_1_D_LUT4_Z.F
Info: 0.6 17.9 Net SOC.Core.read_data_LUT4_Z_22_C_LUT4_Z_1_D[2] (30,9) -> (30,9)
Info: Sink SOC.Core.read_data_LUT4_Z_22_C_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 18.1 Source SOC.Core.read_data_LUT4_Z_22_C_LUT4_Z_1.F
Info: 1.1 19.3 Net SOC.Core.read_data_LUT4_Z_22_C[3] (30,9) -> (32,13)
Info: Sink SOC.Core.read_data_LUT4_Z_22.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 19.5 Source SOC.Core.read_data_LUT4_Z_22.F
Info: 2.0 21.5 Net SOC.read_data[27] (32,13) -> (45,23)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_4.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/soc.v:20.34-20.43
Info: 0.0 21.5 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_4.M
Info: 4.4 ns logic, 17.1 ns routing
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source ClkDivider.clk_counter_TRELLIS_FF_Q_25.Q
Info: 1.4 1.9 Net ClkDivider.clk_counter[6] (21,3) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:14.26-14.37
Info: 0.4 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (20,2) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.4 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.4 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (20,2) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.4 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.4 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (20,2) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (20,2) -> (20,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (20,2) -> (21,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (21,2) -> (21,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (21,2) -> (21,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (21,2) -> (21,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (21,2) -> (21,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.7 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.7 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (21,2) -> (21,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.7 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.7 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (21,2) -> (21,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (21,2) -> (21,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (21,2) -> (22,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (22,2) -> (22,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (22,2) -> (22,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.9 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.9 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (22,2) -> (22,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.9 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.9 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (22,2) -> (22,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 3.0 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (22,2) -> (22,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 3.0 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (22,2) -> (22,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 3.0 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (22,2) -> (22,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 3.0 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (22,2) -> (23,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 3.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 3.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (23,2) -> (23,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 3.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 3.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN (23,2) -> (23,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 3.2 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 3.2 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (23,2) -> (23,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 3.2 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 3.2 Net $nextpnr_CCU2C_1$CIN (23,2) -> (23,2)
Info: Sink $nextpnr_CCU2C_1$CCU2_COMB0.FCI
Info: 0.4 3.6 Source $nextpnr_CCU2C_1$CCU2_COMB0.F
Info: 0.4 4.0 Net reset_LUT4_B_C_LUT4_Z_D[1] (23,2) -> (23,2)
Info: Sink reset_LUT4_B_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.3 Source reset_LUT4_B_C_LUT4_Z.F
Info: 0.9 5.2 Net reset_LUT4_B_C[1] (23,2) -> (22,4)
Info: Sink reset_LUT4_B.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.4 Source reset_LUT4_B.F
Info: 0.7 6.1 Net reset_LUT4_B_Z (22,4) -> (23,3)
Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 0.4 6.5 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 3.2 ns logic, 3.4 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source reset$tr_io.O
Info: 3.1 3.1 Net reset$TRELLIS_IO_IN (0,29) -> (22,4)
Info: Sink reset_LUT4_B.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.3 Source reset_LUT4_B.F
Info: 0.7 4.0 Net reset_LUT4_B_Z (22,4) -> (23,3)
Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 0.4 4.4 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 0.7 ns logic, 3.7 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk_o':
Info: curr total
Info: 0.0 0.0 Source gpios[0]$tr_io.O
Info: 3.1 3.1 Net gpios[0]$TRELLIS_IO_IN (90,29) -> (50,29)
Info: Sink SOC.GPIOS.Gpios[0].direction_LUT4_C.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 3.4 Source SOC.GPIOS.Gpios[0].direction_LUT4_C.F
Info: 0.0 3.4 Net SOC.GPIOS.Gpios[0].direction_LUT4_C_Z (50,29) -> (50,29)
Info: Sink SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_PFUMX_ALUT_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info: 0.2 3.5 Source SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_PFUMX_ALUT_BLUT_LUT4_Z.OFX
Info: 1.1 4.6 Net SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_PFUMX_ALUT_Z[1] (50,29) -> (47,29)
Info: Sink SOC.Core.read_data_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.8 Source SOC.Core.read_data_LUT4_Z.F
Info: 1.0 5.8 Net SOC.read_data[0] (47,29) -> (47,25)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/soc.v:20.34-20.43
Info: 0.0 5.8 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info: 0.6 ns logic, 5.2 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source ClkDivider.clk_o_auto_TRELLIS_FF_Q.Q
Info: 3.6 4.2 Net clk_o (21,4) -> (73,9)
Info: Sink led_LUT4_Z_4.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:10.6-10.11
Info: 0.2 4.4 Source led_LUT4_Z_4.F
Info: 2.7 7.1 Net led[7]$TRELLIS_IO_OUT (73,9) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.3 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk_o' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_28.Q
Info: 2.7 3.2 Net SOC.Core.read_data_LUT4_Z_3_D_LUT4_Z_D[0] (49,25) -> (60,29)
Info: Sink led_LUT4_Z_5.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: Risco-5/src/peripheral/soc.v:83.6-92.2
Info: 0.2 3.5 Source led_LUT4_Z_5.F
Info: 2.7 6.2 Net led[3]$TRELLIS_IO_OUT (60,29) -> (90,29)
Info: Sink led[3]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.4 ns routing
Info: Max frequency for clock '$glbnet$clk_o': 46.48 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 153.14 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.39 ns
Info: Max delay <async> -> posedge $glbnet$clk_o : 5.85 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.07 ns
Info: Max delay posedge $glbnet$clk_o -> <async> : 6.19 ns
Info: Slack histogram:
Info: legend: * represents 105 endpoint(s)
Info: + represents [1,105) endpoint(s)
Info: [ 33470, 35908) |+
Info: [ 35908, 38346) |+
Info: [ 38346, 40784) |+
Info: [ 40784, 43222) |
Info: [ 43222, 45660) |
Info: [ 45660, 48098) |
Info: [ 48098, 50536) |
Info: [ 50536, 52974) |
Info: [ 52974, 55412) |
Info: [ 55412, 57850) |
Info: [ 57850, 60288) |
Info: [ 60288, 62726) |+
Info: [ 62726, 65164) |+
Info: [ 65164, 67602) |+
Info: [ 67602, 70040) |***************************+
Info: [ 70040, 72478) |************************************************************
Info: [ 72478, 74916) |**********************************+
Info: [ 74916, 77354) |**************+
Info: [ 77354, 79792) |***+
Info: [ 79792, 82230) |*+
5 warnings, 0 errors
Info: Program finished normally.
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