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Parameter DEPTH bound to: 8 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 100000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 100000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
Parameter WIDHT bound to: 8 - type: integer
INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
WARNING: [Synth 8-3848] Net interrupt_on_hold in module/entity CSR_Unit does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:20]
WARNING: [Synth 8-6014] Unused sequential element buffer_full_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:49]
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:43]
WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[2] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module UART is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2113.785 ; gain = 489.684 ; free physical = 8815 ; free virtual = 28935
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2131.598 ; gain = 507.496 ; free physical = 8815 ; free virtual = 28934
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2131.598 ; gain = 507.496 ; free physical = 8815 ; free virtual = 28934
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2131.598 ; gain = 0.000 ; free physical = 8814 ; free virtual = 28934
Info: at iteration #5: temp = 0.000000, timing cost = 3893, wirelen = 22995
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2278.348 ; gain = 0.000 ; free physical = 8797 ; free virtual = 28916
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2278.383 ; gain = 0.000 ; free physical = 8796 ; free virtual = 28916
Info: at iteration #10: temp = 0.000000, timing cost = 3310, wirelen = 22238
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8789 ; free virtual = 28909
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8789 ; free virtual = 28909
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8789 ; free virtual = 28909
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 0000000000000001 | 0000
DECODE | 0000000000000010 | 0001
MEMADR | 0000000000000100 | 0010
MEMREAD | 0000000000001000 | 0011
MEMWB | 0000000000010000 | 0100
MEMWRITE | 0000000000100000 | 0101
EXECUTER | 0000000001000000 | 0110
EXECUTEI | 0000000010000000 | 1000
JAL | 0000000100000000 | 1001
BEQ | 0000001000000000 | 1010
AUIPC | 0000010000000000 | 1100
LUI | 0000100000000000 | 1101
JALR_PC | 0001000000000000 | 1110
JALR | 0010000000000000 | 1011
ALUWB | 0100000000000000 | 0111
EXECUTECSR | 1000000000000000 | 1111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8788 ; free virtual = 28908
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
3 Input 32 Bit Adders := 1
2 Input 11 Bit Adders := 2
2 Input 6 Bit Adders := 4
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---XORs :
2 Input 32 Bit XORs := 1
+---Registers :
33 Bit Registers := 1
32 Bit Registers := 44
16 Bit Registers := 2
11 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 1
4 Bit Registers := 2
1 Bit Registers := 17
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
3 Input 33 Bit Muxes := 1
4 Input 32 Bit Muxes := 19
2 Input 32 Bit Muxes := 36
8 Input 32 Bit Muxes := 1
16 Input 32 Bit Muxes := 1
16 Input 16 Bit Muxes := 1
11 Input 16 Bit Muxes := 1
2 Input 16 Bit Muxes := 1
2 Input 8 Bit Muxes := 3
5 Input 8 Bit Muxes := 1
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
10 Input 4 Bit Muxes := 1
8 Input 4 Bit Muxes := 1
23 Input 4 Bit Muxes := 1
10 Input 3 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 15
16 Input 2 Bit Muxes := 3
4 Input 2 Bit Muxes := 4
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 49
16 Input 1 Bit Muxes := 6
4 Input 1 Bit Muxes := 2
13 Input 1 Bit Muxes := 2
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Info: at iteration #15: temp = 0.000000, timing cost = 3061, wirelen = 21885
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":172)
WARN (NL0002) : The module "MUX" instantiated to "MemoryAddressMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
Info: at iteration #20: temp = 0.000000, timing cost = 3322, wirelen = 21787
Info: at iteration #21: temp = 0.000000, timing cost = 3290, wirelen = 21778
Info: SA placement time 16.77s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 36.22 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.87 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.76 ns
Info: Slack histogram:
Info: legend: * represents 42 endpoint(s)
Info: + represents [1,42) endpoint(s)
Info: [ 12393, 13736) |+
Info: [ 13736, 15079) |+
Info: [ 15079, 16422) |*+
Info: [ 16422, 17765) |**+
Info: [ 17765, 19108) |*********+
Info: [ 19108, 20451) |****+
Info: [ 20451, 21794) |*+
Info: [ 21794, 23137) |**********+
Info: [ 23137, 24480) |**************+
Info: [ 24480, 25823) |**********************************************************+
Info: [ 25823, 27166) |************************************************************
Info: [ 27166, 28509) |****************+
Info: [ 28509, 29852) |*****+
Info: [ 29852, 31195) |+
Info: [ 31195, 32538) |+
Info: [ 32538, 33881) |*+
Info: [ 33881, 35224) |*********+
Info: [ 35224, 36567) |*******+
Info: [ 36567, 37910) |***+
Info: [ 37910, 39253) |***+
Info: Checksum: 0x200f4fb2
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 28986 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 163 836 | 163 836 | 28237| 0.62 0.62|
Info: 2000 | 306 1693 | 143 857 | 27496| 0.24 0.87|
Info: 3000 | 411 2588 | 105 895 | 26858| 0.22 1.09|
Info: 4000 | 555 3444 | 144 856 | 26050| 0.26 1.35|
Info: 5000 | 665 4334 | 110 890 | 25244| 0.28 1.63|
Info: 6000 | 803 5196 | 138 862 | 24663| 0.24 1.87|
Info: 7000 | 953 6046 | 150 850 | 24143| 0.25 2.12|
[10%] Placement Phase 0 completed
Info: 8000 | 1049 6950 | 96 904 | 23495| 0.31 2.43|
Info: 9000 | 1256 7743 | 207 793 | 22736| 0.27 2.69|
Info: 10000 | 1452 8547 | 196 804 | 22156| 0.26 2.95|
Info: 11000 | 1668 9331 | 216 784 | 21525| 0.30 3.25|
Info: 12000 | 1862 10137 | 194 806 | 20802| 0.25 3.50|
Info: 13000 | 2071 10928 | 209 791 | 20072| 0.26 3.77|
Info: 14000 | 2315 11684 | 244 756 | 19457| 0.27 4.04|
[20%] Placement Phase 1 completed
Info: 15000 | 2484 12515 | 169 831 | 18799| 0.27 4.31|
Info: 16000 | 2730 13269 | 246 754 | 18142| 0.31 4.62|
Info: 17000 | 2973 14026 | 243 757 | 17559| 0.30 4.92|
Info: 18000 | 3276 14723 | 303 697 | 17021| 0.31 5.23|
Info: 19000 | 3548 15451 | 272 728 | 16563| 0.35 5.58|
Info: 20000 | 3851 16148 | 303 697 | 16019| 0.30 5.88|
Info: 21000 | 4160 16839 | 309 691 | 15391| 0.31 6.20|
Info: 22000 | 4494 17505 | 334 666 | 14905| 0.34 6.54|
Info: 23000 | 4812 18187 | 318 682 | 14346| 0.29 6.83|
Info: 24000 | 5117 18882 | 305 695 | 13842| 0.32 7.15|
Info: 25000 | 5531 19468 | 414 586 | 13328| 0.32 7.47|
Info: 26000 | 5983 20016 | 452 548 | 12853| 0.32 7.79|
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8605 ; free virtual = 28735
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Info: 27000 | 6448 20551 | 465 535 | 12424| 0.33 8.12|
Info: 28000 | 6843 21156 | 395 605 | 11914| 0.30 8.42|
Info: 29000 | 7278 21721 | 435 565 | 11517| 0.33 8.75|
Info: 30000 | 7672 22310 | 394 589 | 11066| 0.34 9.09|
Info: 31000 | 8065 22860 | 393 550 | 10596| 0.30 9.38|
Info: 32000 | 8321 23456 | 256 596 | 9917| 0.22 9.60|
Info: 33000 | 8595 24044 | 274 588 | 9311| 0.25 9.85|
Info: 34000 | 8830 24689 | 235 645 | 8800| 0.29 10.14|
Info: 35000 | 9111 25324 | 281 635 | 8111| 0.22 10.36|
Info: 36000 | 9418 25950 | 307 626 | 7467| 0.24 10.61|
Info: 37000 | 9734 26569 | 316 619 | 6997| 0.30 10.90|
Info: 38000 | 10158 27085 | 424 516 | 6476| 0.30 11.21|
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8604 ; free virtual = 28734
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
Info: 39000 | 10413 27741 | 255 656 | 5805| 0.27 11.48|
Info: 40000 | 10501 28633 | 88 892 | 4941| 0.17 11.64|
Info: 41000 | 10523 29598 | 22 965 | 3966| 0.08 11.72|
Info: 42000 | 10565 30551 | 42 953 | 3011| 0.09 11.81|
Info: 43000 | 10677 31434 | 112 883 | 2138| 0.19 12.00|
Info: 44000 | 10903 32105 | 226 671 | 1462| 0.33 12.33|
Info: 45000 | 11014 32945 | 111 840 | 622| 0.24 12.58|
Info: 45626 | 11018 33288 | 4 343 | 0| 0.13 12.71|
Info: Routing complete.
Info: Router1 time 12.71s
Info: Checksum: 0xe97b2b82
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.instruction_register_TRELLIS_FF_Q_19.Q
Info: 1.8 2.3 Net SOC.Core.instruction_register[12] (8,24) -> (15,33)
Info: Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_C_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/core/core.v:56.12-56.32
Info: 0.2 2.6 Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_C_LUT4_Z.F
Info: 0.7 3.3 Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_B[1] (15,33) -> (15,26)
Info: Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_B_LUT4_B_Z_L6MUX21_Z_1_SD_L6MUX21_SD_1_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 3.5 Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_B_LUT4_B_Z_L6MUX21_Z_1_SD_L6MUX21_SD_1_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.6 4.1 Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_B_LUT4_B_Z_L6MUX21_Z_1_SD_L6MUX21_SD_1_Z[5] (15,26) -> (15,27)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_1_C_LUT4_Z_D_PFUMX_Z_1_C0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 4.4 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_1_C_LUT4_Z_D_PFUMX_Z_1_C0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.2 5.6 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_1_C_LUT4_Z_D_PFUMX_Z_1_C0[4] (15,27) -> (15,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_1_C_LUT4_Z_D_PFUMX_Z_1_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 5.9 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_1_C_LUT4_Z_D_PFUMX_Z_1_BLUT_LUT4_Z.OFX
Info: 0.7 6.6 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_A_LUT4_Z_1_C_LUT4_Z_D[4] (15,36) -> (15,35)
Info: Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_B_LUT4_B_C_LUT4_C_Z_LUT4_C_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 6.8 Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_B_LUT4_B_C_LUT4_C_Z_LUT4_C_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 1.3 8.2 Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_B_LUT4_B_C_LUT4_C_Z_LUT4_C_Z_PFUMX_BLUT_Z[6] (15,35) -> (23,30)
Info: Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_B_LUT4_B_Z_L6MUX21_Z_SD_LUT4_C_Z_LUT4_C_Z_LUT4_D_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 8.4 Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_B_LUT4_B_Z_L6MUX21_Z_SD_LUT4_C_Z_LUT4_C_Z_LUT4_D_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.4 9.8 Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_B_LUT4_B_Z_L6MUX21_Z_SD_LUT4_C_Z_LUT4_C_Z_LUT4_D_Z[5] (23,30) -> (22,41)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_8_B_PFUMX_Z_1_C0_L6MUX21_Z_SD_LUT4_Z_D_LUT4_C_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 10.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_8_B_PFUMX_Z_1_C0_L6MUX21_Z_SD_LUT4_Z_D_LUT4_C_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 10.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_8_B_PFUMX_Z_1_C0_L6MUX21_Z_SD_LUT4_Z_D_LUT4_C_D_L6MUX21_Z_D1 (22,41) -> (22,41)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_8_B_PFUMX_Z_1_C0_L6MUX21_Z_SD_LUT4_Z_D_LUT4_C_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 10.3 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_8_B_PFUMX_Z_1_C0_L6MUX21_Z_SD_LUT4_Z_D_LUT4_C_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.9 11.2 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_8_B_PFUMX_Z_1_C0_L6MUX21_Z_SD[3] (22,41) -> (19,41)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_8_B_PFUMX_Z_1_C0_L6MUX21_Z_SD_LUT4_Z_D_LUT4_C_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 11.4 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_8_B_PFUMX_Z_1_C0_L6MUX21_Z_SD_LUT4_Z_D_LUT4_C_1.F
Info: 0.7 12.1 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_8_B_PFUMX_Z_1_C0_L6MUX21_Z_SD_LUT4_Z_D_LUT4_C_1_Z[4] (19,41) -> (19,39)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_D_LUT4_D_Z_LUT4_Z_2_D_LUT4_C_Z_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 12.4 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_D_LUT4_D_Z_LUT4_Z_2_D_LUT4_C_Z_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.6 13.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_D_LUT4_D_Z_LUT4_Z_2_D_LUT4_C_Z_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_C_Z[3] (19,39) -> (19,41)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_D_LUT4_D_Z_LUT4_Z_2_D_LUT4_C_Z_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_C_Z_LUT4_B.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.3 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_D_LUT4_D_Z_LUT4_Z_2_D_LUT4_C_Z_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_C_Z_LUT4_B.F
Info: 0.4 13.7 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_D_LUT4_D_Z_LUT4_Z_2_D_LUT4_C_Z_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_C_Z_LUT4_B_Z[1] (19,41) -> (19,41)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_D_LUT4_D_Z_LUT4_Z_2_D_LUT4_C_Z_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_C_Z_LUT4_B_Z_LUT4_D.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.9 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_D_LUT4_D_Z_LUT4_Z_2_D_LUT4_C_Z_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_C_Z_LUT4_B_Z_LUT4_D.F
Info: 1.3 15.2 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_D_LUT4_D_Z_LUT4_Z_2_D_LUT4_C_Z_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_C_Z_LUT4_B_Z_LUT4_D_Z[4] (19,41) -> (19,32)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_1_CIN_CCU2C_COUT_S0_LUT4_D_Z_PFUMX_Z_C0_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_D_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_D_Z_PFUMX_Z_2_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 15.5 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_1_CIN_CCU2C_COUT_S0_LUT4_D_Z_PFUMX_Z_C0_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_D_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_D_Z_PFUMX_Z_2_BLUT_LUT4_Z.OFX
Info: 1.3 16.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_1_CIN_CCU2C_COUT_S0_LUT4_D_Z_PFUMX_Z_C0_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_D_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_D_Z[6] (19,32) -> (22,24)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_A_Z_L6MUX21_Z_3_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 17.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_A_Z_L6MUX21_Z_3_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.5 18.6 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_7_B_LUT4_A_Z[6] (22,24) -> (22,36)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 18.8 Source SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.7 20.5 Net SOC.Core.pc_load (22,36) -> (23,21)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_14.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:48.38-48.45
Info: 0.0 20.5 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_14.CE
Info: 4.3 ns logic, 16.2 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[2]$tr_io.O
Info: 4.8 4.8 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (12,23)
Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_B.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 5.1 Source SOC.GPIOS.Gpios[2].direction_LUT4_B.F
Info: 0.6 5.7 Net SOC.Core.read_data_LUT4_Z_18_C[3] (12,23) -> (13,24)
Info: Sink SOC.Core.read_data_LUT4_Z_18.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.9 Source SOC.Core.read_data_LUT4_Z_18.F
Info: 0.4 6.4 Net SOC.read_data[2] (13,24) -> (13,24)
Info: Sink SOC.Core.memory_register_TRELLIS_FF_Q_29.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:21.34-21.43
Info: 0.0 6.4 Setup SOC.Core.memory_register_TRELLIS_FF_Q_29.M
Info: 0.5 ns logic, 5.9 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info: 3.8 4.4 Net SOC.GPIOS.gpio_direction[2] (5,25) -> (71,23)
Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info: Defined in:
Info: Risco-5/src/peripheral/gpios.v:14.19-14.33
Info: 0.2 4.6 Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info: 0.7 5.3 Net gpios_$_TBUF__Y_3_E (71,23) -> (77,23)
Info: Sink gpios[2]$tr_io$invert_T.A
Info: 0.2 5.6 Source gpios[2]$tr_io$invert_T.F
Info: 1.5 7.1 Net gpios[2]$tr_io$invert_T$conn$Z (77,23) -> (90,23)
Info: Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 6.1 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 48.81 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.37 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.10 ns
Info: Slack histogram:
Info: legend: * represents 57 endpoint(s)
Info: + represents [1,57) endpoint(s)
Info: [ 19511, 20489) |**+
Info: [ 20489, 21467) |*****+
Info: [ 21467, 22445) |***+
Info: [ 22445, 23423) |+
Info: [ 23423, 24401) |+
Info: [ 24401, 25379) |*+
Info: [ 25379, 26357) |*********+
Info: [ 26357, 27335) |**********+
Info: [ 27335, 28313) |***********************+
Info: [ 28313, 29291) |************************************************************
Info: [ 29291, 30269) |******+
Info: [ 30269, 31247) |+
Info: [ 31247, 32225) |******+
Info: [ 32225, 33203) |****+
Info: [ 33203, 34181) |+
Info: [ 34181, 35159) |*+
Info: [ 35159, 36137) |***+
Info: [ 36137, 37115) |*******+
Info: [ 37115, 38093) |**+
Info: [ 38093, 39071) |**+
Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8758 ; free virtual = 28907
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[30%] Placement Phase 2 completed
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8787 ; free virtual = 28936
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8775 ; free virtual = 28924
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8775 ; free virtual = 28924
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8775 ; free virtual = 28924
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8775 ; free virtual = 28924
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8775 ; free virtual = 28924
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8775 ; free virtual = 28924
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 1|
|2 |CARRY4 | 55|
|3 |LUT1 | 10|
|4 |LUT2 | 140|
|5 |LUT3 | 51|
|6 |LUT4 | 141|
|7 |LUT5 | 371|
|8 |LUT6 | 1366|
|9 |MUXF7 | 256|
|10 |RAM256X1S | 64|
|11 |RAM32M | 2|
|12 |RAM32X1D | 4|
|13 |FDRE | 1739|
|14 |FDSE | 5|
|15 |LD | 4|
|16 |IBUF | 2|
|17 |IOBUF | 8|
|18 |OBUF | 9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8775 ; free virtual = 28924
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 43 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2278.383 ; gain = 507.496 ; free physical = 8775 ; free virtual = 28924
Synthesis Optimization Complete : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2278.383 ; gain = 654.281 ; free physical = 8775 ; free virtual = 28924
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2278.383 ; gain = 0.000 ; free physical = 9059 ; free virtual = 29209
INFO: [Netlist 29-17] Analyzing 393 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2350.379 ; gain = 0.000 ; free physical = 9058 ; free virtual = 29207
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 82 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 8 instances
LD => LDCE: 4 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 8250af15
INFO: [Common 17-83] Releasing license: Synthesis
75 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 2350.414 ; gain = 1035.320 ; free physical = 9058 ; free virtual = 29207
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2060.396; main = 1773.178; forked = 434.099
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3236.867; main = 2350.383; forked = 982.531
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.68 . Memory (MB): peak = 2414.410 ; gain = 63.996 ; free physical = 9058 ; free virtual = 29207
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 143e2baec
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2518.230 ; gain = 103.820 ; free physical = 9014 ; free virtual = 29164
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 143e2baec
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.137 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28900
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 143e2baec
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.137 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28900
Phase 1 Initialization | Checksum: 143e2baec
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.137 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28900
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 143e2baec
Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2768.137 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28900
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 143e2baec
Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2768.137 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28900
Phase 2 Timer Update And Timing Data Collection | Checksum: 143e2baec
Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2768.137 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28900
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 6 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 204605c91
Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2768.137 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28900
Retarget | Checksum: 204605c91
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 2 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 204605c91
Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2768.137 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28900
Constant propagation | Checksum: 204605c91
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 15dad2d02
Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2768.137 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28899
Sweep | Checksum: 15dad2d02
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 15dad2d02
Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2800.152 ; gain = 32.016 ; free physical = 8750 ; free virtual = 28899
BUFG optimization | Checksum: 15dad2d02
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 15dad2d02
Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2800.152 ; gain = 32.016 ; free physical = 8750 ; free virtual = 28899
Shift Register Optimization | Checksum: 15dad2d02
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 14a4ea2af
Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2800.152 ; gain = 32.016 ; free physical = 8750 ; free virtual = 28899
Post Processing Netlist | Checksum: 14a4ea2af
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1cf01f192
Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2800.152 ; gain = 32.016 ; free physical = 8750 ; free virtual = 28899
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.152 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28899
Phase 9.2 Verifying Netlist Connectivity | Checksum: 1cf01f192
Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2800.152 ; gain = 32.016 ; free physical = 8750 ; free virtual = 28899
Phase 9 Finalization | Checksum: 1cf01f192
Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2800.152 ; gain = 32.016 ; free physical = 8750 ; free virtual = 28899
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 2 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 8 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 1cf01f192
Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2800.152 ; gain = 32.016 ; free physical = 8750 ; free virtual = 28899
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.152 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28899
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1cf01f192
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.152 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28899
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1cf01f192
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.152 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28899
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.152 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28899
Ending Netlist Obfuscation Task | Checksum: 1cf01f192
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.152 ; gain = 0.000 ; free physical = 8750 ; free virtual = 28899
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2800.152 ; gain = 449.738 ; free physical = 8750 ; free virtual = 28899
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2832.168 ; gain = 0.000 ; free physical = 8749 ; free virtual = 28898
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 143689282
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2832.168 ; gain = 0.000 ; free physical = 8749 ; free virtual = 28898
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2832.168 ; gain = 0.000 ; free physical = 8749 ; free virtual = 28898
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 106e7cf05
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2832.168 ; gain = 0.000 ; free physical = 8749 ; free virtual = 28899
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1cdc0e798
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8749 ; free virtual = 28899
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1cdc0e798
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8749 ; free virtual = 28899
Phase 1 Placer Initialization | Checksum: 1cdc0e798
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8749 ; free virtual = 28899
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1a5439612
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8743 ; free virtual = 28893
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1af78d0fa
Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8743 ; free virtual = 28893
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1af78d0fa
Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8743 ; free virtual = 28893
Phase 2.4 Global Placement Core
[50%] Placement Phase 3 completed
Running routing......
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 116bb453f
Time (s): cpu = 00:00:24 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8722 ; free virtual = 28872
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 34 LUTNM shape to break, 48 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 14, two critical 20, total 34, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 55 nets or LUTs. Breaked 34 LUTs, combined 21 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8722 ; free virtual = 28872
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 34 | 21 | 55 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 34 | 21 | 55 | 0 | 9 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1782a92e6
Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8722 ; free virtual = 28872
Phase 2.4 Global Placement Core | Checksum: e0dcbdc9
Time (s): cpu = 00:00:30 ; elapsed = 00:00:08 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8722 ; free virtual = 28872
Phase 2 Global Placement | Checksum: e0dcbdc9
Time (s): cpu = 00:00:30 ; elapsed = 00:00:08 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8722 ; free virtual = 28872
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 17ac39db6
Time (s): cpu = 00:00:31 ; elapsed = 00:00:08 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8722 ; free virtual = 28872
Phase 3.2 Commit Most Macros & LUTRAMs
[60%] Routing Phase 0 completed
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17fc7c12c
Time (s): cpu = 00:00:33 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8669 ; free virtual = 28818
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1f69fb7bb
Time (s): cpu = 00:00:33 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8669 ; free virtual = 28818
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 2146babac
Time (s): cpu = 00:00:33 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8669 ; free virtual = 28818
Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 18d02401b
Time (s): cpu = 00:00:36 ; elapsed = 00:00:11 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8668 ; free virtual = 28818
Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 11c676d1c
Time (s): cpu = 00:00:38 ; elapsed = 00:00:12 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8668 ; free virtual = 28817
Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 153f7ae85
Time (s): cpu = 00:00:38 ; elapsed = 00:00:12 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8668 ; free virtual = 28817
Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1d3efe367
Time (s): cpu = 00:00:38 ; elapsed = 00:00:12 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8668 ; free virtual = 28817
Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 24df6b01b
Time (s): cpu = 00:00:45 ; elapsed = 00:00:16 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8666 ; free virtual = 28815
Phase 3 Detail Placement | Checksum: 24df6b01b
Time (s): cpu = 00:00:45 ; elapsed = 00:00:16 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8666 ; free virtual = 28815
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
[70%] Routing Phase 1 completed
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: f68b2eba
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.827 | TNS=-43.115 |
Phase 1 Physical Synthesis Initialization | Checksum: 159a1e503
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8665 ; free virtual = 28815
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 159a1e503
Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8665 ; free virtual = 28815
Phase 4.1.1.1 BUFG Insertion | Checksum: f68b2eba
Time (s): cpu = 00:00:48 ; elapsed = 00:00:17 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8665 ; free virtual = 28815
Phase 4.1.1.2 Post Placement Timing Optimization
[80%] Routing Phase 2 completed
WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Wed Apr 3 02:07:01 2024
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.161. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1da15cde9
Time (s): cpu = 00:01:22 ; elapsed = 00:00:47 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8960 ; free virtual = 29116
Time (s): cpu = 00:01:22 ; elapsed = 00:00:47 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8960 ; free virtual = 29116
Phase 4.1 Post Commit Optimization | Checksum: 1da15cde9
Time (s): cpu = 00:01:22 ; elapsed = 00:00:47 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8960 ; free virtual = 29116
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1da15cde9
Time (s): cpu = 00:01:22 ; elapsed = 00:00:47 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8960 ; free virtual = 29116
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 8x8|
|___________|___________________|___________________|
| South| 1x1| 2x2|
|___________|___________________|___________________|
| East| 1x1| 2x2|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1da15cde9
Time (s): cpu = 00:01:22 ; elapsed = 00:00:47 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8960 ; free virtual = 29116
Phase 4.3 Placer Reporting | Checksum: 1da15cde9
Time (s): cpu = 00:01:22 ; elapsed = 00:00:47 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8960 ; free virtual = 29116
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8960 ; free virtual = 29116
Time (s): cpu = 00:01:22 ; elapsed = 00:00:47 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8960 ; free virtual = 29116
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1dd3651a7
Time (s): cpu = 00:01:22 ; elapsed = 00:00:47 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8960 ; free virtual = 29116
Ending Placer Task | Checksum: e77b4651
Time (s): cpu = 00:01:22 ; elapsed = 00:00:47 . Memory (MB): peak = 2839.195 ; gain = 7.027 ; free physical = 8960 ; free virtual = 29116
37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:24 ; elapsed = 00:00:47 . Memory (MB): peak = 2839.195 ; gain = 39.043 ; free physical = 8960 ; free virtual = 29116
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8957 ; free virtual = 29113
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8960 ; free virtual = 29116
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: e0eab53f ConstDB: 0 ShapeSum: 6909112 RouteDB: 0
Post Restoration Checksum: NetGraph: e8009f99 | NumContArr: 1aa24a4e | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 287f4df21
Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8938 ; free virtual = 29094
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 287f4df21
Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8938 ; free virtual = 29094
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 287f4df21
Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8938 ; free virtual = 29094
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 123ec124d
Time (s): cpu = 00:00:36 ; elapsed = 00:00:28 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8913 ; free virtual = 29069
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.388 | TNS=0.000 | WHS=-0.204 | THS=-15.599|
Router Utilization Summary
Global Vertical Routing Utilization = 0.000609305 %
Global Horizontal Routing Utilization = 0.00269963 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 3354
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 3351
Number of Partially Routed Nets = 3
Number of Node Overlaps = 3
Phase 2 Router Initialization | Checksum: 1bbd18bb2
Time (s): cpu = 00:00:39 ; elapsed = 00:00:28 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8904 ; free virtual = 29060
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 1bbd18bb2
Time (s): cpu = 00:00:39 ; elapsed = 00:00:28 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8904 ; free virtual = 29060
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 2f30e0566
Time (s): cpu = 00:00:42 ; elapsed = 00:00:29 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29059
Phase 3 Initial Routing | Checksum: 2f30e0566
Time (s): cpu = 00:00:42 ; elapsed = 00:00:29 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29059
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 1783
Number of Nodes with overlaps = 663
Number of Nodes with overlaps = 363
Number of Nodes with overlaps = 208
Number of Nodes with overlaps = 134
Number of Nodes with overlaps = 87
Number of Nodes with overlaps = 34
Number of Nodes with overlaps = 19
Number of Nodes with overlaps = 21
Number of Nodes with overlaps = 8
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.056 | TNS=-56.244| WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 2f4df617f
Time (s): cpu = 00:01:16 ; elapsed = 00:00:42 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29059
Phase 4.2 Global Iteration 1
Number of Nodes with overlaps = 592
Number of Nodes with overlaps = 357
Number of Nodes with overlaps = 235
Number of Nodes with overlaps = 169
Number of Nodes with overlaps = 112
Number of Nodes with overlaps = 83
Number of Nodes with overlaps = 58
Number of Nodes with overlaps = 36
Number of Nodes with overlaps = 15
Number of Nodes with overlaps = 16
Number of Nodes with overlaps = 10
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 7
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.706 | TNS=-23.418| WHS=N/A | THS=N/A |
Phase 4.2 Global Iteration 1 | Checksum: 322045194
Time (s): cpu = 00:01:48 ; elapsed = 00:00:57 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8901 ; free virtual = 29045
Phase 4.3 Global Iteration 2
Number of Nodes with overlaps = 532
Number of Nodes with overlaps = 250
Number of Nodes with overlaps = 237
Number of Nodes with overlaps = 151
Number of Nodes with overlaps = 116
Number of Nodes with overlaps = 84
Number of Nodes with overlaps = 39
Number of Nodes with overlaps = 46
Number of Nodes with overlaps = 35
Number of Nodes with overlaps = 23
Number of Nodes with overlaps = 17
Number of Nodes with overlaps = 14
Number of Nodes with overlaps = 8
Number of Nodes with overlaps = 13
Number of Nodes with overlaps = 13
Number of Nodes with overlaps = 8
Number of Nodes with overlaps = 9
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.550 | TNS=-12.456| WHS=N/A | THS=N/A |
Phase 4.3 Global Iteration 2 | Checksum: 221344951
Time (s): cpu = 00:02:14 ; elapsed = 00:01:11 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29062
Phase 4.4 Global Iteration 3
Number of Nodes with overlaps = 640
Number of Nodes with overlaps = 328
Number of Nodes with overlaps = 268
Number of Nodes with overlaps = 120
Number of Nodes with overlaps = 91
Number of Nodes with overlaps = 43
Number of Nodes with overlaps = 25
Number of Nodes with overlaps = 17
Number of Nodes with overlaps = 11
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.564 | TNS=-13.331| WHS=N/A | THS=N/A |
Phase 4.4 Global Iteration 3 | Checksum: 32f9f1f27
Time (s): cpu = 00:02:40 ; elapsed = 00:01:22 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29063
Phase 4 Rip-up And Reroute | Checksum: 32f9f1f27
Time (s): cpu = 00:02:40 ; elapsed = 00:01:22 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29063
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 25430253c
Time (s): cpu = 00:02:42 ; elapsed = 00:01:22 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29064
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.542 | TNS=-11.972| WHS=N/A | THS=N/A |
Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 29b498d37
Time (s): cpu = 00:02:42 ; elapsed = 00:01:22 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29063
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 29b498d37
Time (s): cpu = 00:02:42 ; elapsed = 00:01:22 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29063
Phase 5 Delay and Skew Optimization | Checksum: 29b498d37
Time (s): cpu = 00:02:42 ; elapsed = 00:01:22 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29063
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 327179686
Time (s): cpu = 00:02:44 ; elapsed = 00:01:23 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29064
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.521 | TNS=-11.274| WHS=0.036 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 2c5d2c0c6
Time (s): cpu = 00:02:44 ; elapsed = 00:01:23 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29064
Phase 6 Post Hold Fix | Checksum: 2c5d2c0c6
Time (s): cpu = 00:02:44 ; elapsed = 00:01:23 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29064
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 1.14336 %
Global Horizontal Routing Utilization = 1.3729 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
--GLOBAL Congestion:
Utilization threshold used for congestion level computation: 0.85
Congestion Report
North Dir 1x1 Area, Max Cong = 71.1712%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 86.4865%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
INT_R_X27Y146 -> INT_R_X27Y146
East Dir 1x1 Area, Max Cong = 72.0588%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 79.4118%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: 2c5d2c0c6
Time (s): cpu = 00:02:44 ; elapsed = 00:01:23 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29064
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 2c5d2c0c6
Time (s): cpu = 00:02:44 ; elapsed = 00:01:23 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29064
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 22a50cdd8
Time (s): cpu = 00:02:44 ; elapsed = 00:01:23 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29064
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.521 | TNS=-11.274| WHS=0.036 | THS=0.000 |
WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 22a50cdd8
Time (s): cpu = 00:02:45 ; elapsed = 00:01:23 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29063
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 1192b4d81
Time (s): cpu = 00:02:46 ; elapsed = 00:01:24 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29063
Ending Routing Task | Checksum: 1192b4d81
Time (s): cpu = 00:02:46 ; elapsed = 00:01:24 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29063
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
15 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:02:47 ; elapsed = 00:01:24 . Memory (MB): peak = 2839.195 ; gain = 0.000 ; free physical = 8903 ; free virtual = 29063
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (12)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (4)
5. checking no_input_delay (9)
6. checking no_output_delay (17)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (12)
-------------------------
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[6]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[7]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[9]/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (4)
------------------------------------------------
There are 4 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (9)
------------------------------
There are 9 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (17)
--------------------------------
There are 17 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
-0.522 -11.239 40 6708 0.037 0.000 0 6708 3.750 0.000 0 2033
Timing constraints are not met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin -0.522 -11.239 40 6708 0.037 0.000 0 6708 3.750 0.000 0 2033
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[9]_0[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 3152.422 ; gain = 225.395 ; free physical = 8570 ; free virtual = 28734
INFO: [Common 17-206] Exiting Vivado at Wed Apr 3 02:08:52 2024...
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
[Pipeline] }
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Open file DONE
Parse file DONE
load program
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
Loading: [====== ] 11.11%[Pipeline] }
Load SRAM: [========= ] 18.00%[Pipeline] // stage
[Pipeline] }
Loading: [============ ] 22.23%
Load SRAM: [=================== ] 38.00%
Loading: [================= ] 33.34%
Load SRAM: [============================= ] 58.00%
Loading: [======================= ] 44.46%
Load SRAM: [======================================= ] 78.00%
Loading: [============================ ] 55.57%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
[Pipeline] }
Lock released on resource [nexys4]
Loading: [================================== ] 66.68%[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Loading: [======================================= ] 77.80%
Loading: [============================================= ] 88.91%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
[Pipeline] }
+ echo testando na tang nano
testando na tang nano
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
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