Console Output

+ /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb /eda/oss-cad-suite/bin/Risco-5/src/core/*.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v
/eda/oss-cad-suite/bin/Risco-5/src/core/*.v: No such file or directory
error: Unable to find the root module "soc_tb" in the Verilog source.
     : Perhaps ``-s soc_tb'' is incorrect?
1 error(s) during elaboration.