Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco_5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v
[Pipeline] sh
+ /eda/oss-cad-suite/bin/vvp build/soc_test.o
ERROR: Risco-5/src/peripheral/memory.v:29: $readmemh: Unable to open software/memory/generic.hex for reading.
VCD info: dumpfile build/soc.vcd opened for output.
Risco-5/tests/soc_test.v:34: $finish called at 3606 (1s)
[Pipeline] sh
+ rm -f Risco-5/software/memory/generic.hex
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Síntese)
[Pipeline] parallel
[Pipeline] { (Branch: OSS-Cad-Suite)
[Pipeline] { (Branch: Gowin)
[Pipeline] { (Branch: Vivado)
[Pipeline] stage
[Pipeline] { (OSS-Cad-Suite)
[Pipeline] stage
[Pipeline] { (Gowin)
[Pipeline] stage
[Pipeline] { (Vivado)
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
[Pipeline] sh
+ rm -rf Risco-5/impl/pnr
[Pipeline] sh
+ cd Risco-5/fpga/nexys4_ddr
+ mkdir build
+ /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl
+ /eda/oss-cad-suite/bin/yosys -p                                          read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)

-- Running command `                                         read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v
Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\Alu'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:139: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v
Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation.
Generating RTLIL representation for module `\CSR_Unit'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v
Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

22. Executing SYNTH_ECP5 pass.

22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

22.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

22.3. Executing HIERARCHY pass (managing design hierarchy).

22.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: FIFO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   0 design levels: CSR_Unit            
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: Alu                 
root of   0 design levels: ResetBootSystem     
root of   3 design levels: top                 
Automatically selected top as design top module.

22.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 8192
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6

22.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 8192
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6
Generating RTLIL representation for module `$paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC'.
Parameter \CYCLES = 20

22.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \WIDHT = 5

22.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 5
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600

22.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

22.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

22.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:139: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

22.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

22.3.12. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \WIDHT = 6

22.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 6
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200

22.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Generating RTLIL representation for module `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 8192

22.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 8192
Generating RTLIL representation for module `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

22.3.16. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

22.3.19. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100

22.3.20. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\GPIOS'.
Removing unused module `\FIFO'.
Removing unused module `\Core'.
Removing unused module `\ResetBootSystem'.
Removed 14 unused modules.

22.4. Executing PROC pass (convert processes to netlists).

22.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$566'.
Found and cleaned up 1 empty switch in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:0$977'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:0$977'.
Cleaned up 2 empty switches.

22.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$673 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$625 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$567 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:24$888 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$1070 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$1068 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$1060 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$1057 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$1051 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$1046 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$1041 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$1032 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$1019 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$1017 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$1009 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$995 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$989 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$984 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:239$775 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:45$975 in module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:33$938 in module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$286 in module LEDs.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:76$928 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:41$914 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$912 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:24$144 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$133 in module PC.
Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:14$132 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:14$132 in module MUX.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$130 in module Immediate_Generator.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:187$128 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:178$124 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:164$122 in module CSR_Unit.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:118$115 in module CSR_Unit.
Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$676 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:574$80 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:564$79 in module Control_Unit.
Marked 10 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:139$34 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:131$33 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$26 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$26 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:23$11 in module Alu.
Removed a total of 2 dead cases.

22.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 14 redundant assignments.
Promoted 145 assignments to connections.

22.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$674'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$1072'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$1025'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$781'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
  Set init value: \pc_old = 0
  Set init value: \temp_reg1 = 0
  Set init value: \temp_reg2 = 0
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$289'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$931'.
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \buffer_full = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$136'.
  Set init value: \Output = 0
Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$129'.
  Set init value: \csr_mcause = 0
  Set init value: \csr_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mepc = 0
  Set init value: \csr_mie_mfie = 16'0000000000000000
  Set init value: \csr_mie_meie = 1'0
  Set init value: \csr_mie_msie = 1'0
  Set init value: \csr_mie_mtie = 1'0
  Set init value: \csr_mip_mfip = 16'0000000000000000
  Set init value: \csr_mip_meip = 1'0
  Set init value: \csr_mip_mtip = 1'0
  Set init value: \csr_mip_msip = 1'0
  Set init value: \csr_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mscratch = 0
  Set init value: \csr_mstatus_mie = 1'0
  Set init value: \csr_mstatus_mpie = 1'0
  Set init value: \csr_mtvec = 0
  Set init value: \csr_mtval = 0
  Set init value: \csr_write_data = 0
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$682'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$81'.
  Set init value: \state = 6'000000
  Set init value: \is_immediate = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \reg_write = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \csr_write_enable = 1'0
  Set init value: \alu_input_selector = 1'0
  Set init value: \save_address = 1'0
  Set init value: \save_value = 1'0
  Set init value: \save_value_2 = 1'0
  Set init value: \control_memory_op = 1'0
  Set init value: \write_data_in = 1'0
  Set init value: \lorD = 2'00
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 3'000
  Set init value: \alu_src_b = 3'000
  Set init value: \memory_to_reg = 3'000
  Set init value: \control_unit_memory_op = 3'010
  Set init value: \control_unit_aluop = 4'0000
  Set init value: \clear_hal_byte_one_block_option = 3'000
  Set init value: \clear_hal_byte_one_block_option_2 = 3'000
  Set init value: \nextstate = 6'000000

22.4.5. Executing PROC_ARST pass (detect async resets in processes).

22.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~101 debug messages>

22.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$674'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$673'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$625'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$624_EN[3:0]$631
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$624_DATA[3:0]$630
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$624_ADDR[3:0]$629
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$567'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$565_EN[3:0]$573
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$565_DATA[3:0]$572
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$565_ADDR[3:0]$571
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$566'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$888'.
     1/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$900
     2/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_DATA[7:0]$899
     3/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_ADDR[5:0]$898
     4/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$895
     5/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_DATA[7:0]$894
     6/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_ADDR[5:0]$893
     7/8: $0\write_ptr[5:0]
     8/8: $0\read_ptr[5:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$1072'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1070'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$1068'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$1060'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$1057'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$1051'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1046'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$1041'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$1032'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$1025'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$1019'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$1017'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$1009'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$995'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$989'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$984'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$781'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:239$775'.
     1/9: $0\alu_out_register[31:0]
     2/9: $0\register_data_2[31:0]
     3/9: $0\register_data_1[31:0]
     4/9: $0\memory_register[31:0]
     5/9: $0\temp_reg3[31:0]
     6/9: $0\temp_reg2[31:0]
     7/9: $0\temp_reg1[31:0]
     8/9: $0\pc_old[31:0]
     9/9: $0\instruction_register[31:0]
Creating decoders for process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:45$975'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$938'.
     1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$971
     2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_DATA[31:0]$970
     3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_ADDR[31:0]$969
     4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$974
     5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_DATA[31:0]$973
     6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_ADDR[31:0]$972
     7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$961
     8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_DATA[31:0]$960
     9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_ADDR[31:0]$959
    10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$967
    11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_DATA[31:0]$966
    12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_ADDR[31:0]$965
    13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$964
    14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_DATA[31:0]$963
    15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_ADDR[31:0]$962
    16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$957
    17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_DATA[31:0]$956
    18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_ADDR[31:0]$955
    19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$954
    20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_DATA[31:0]$953
    21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_ADDR[31:0]$952
    22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$951
    23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_DATA[31:0]$950
    24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_ADDR[31:0]$949
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$289'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$286'.
     1/1: $0\data[32:0]
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$931'.
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$928'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$914'.
     1/9: $0\rx_fifo_write[0:0]
     2/9: $0\rx_fifo_read[0:0]
     3/9: $0\tx_fifo_write[0:0]
     4/9: $0\tx_fifo_read[0:0]
     5/9: $0\uart_tx_en[0:0]
     6/9: $0\rx_fifo_write_data[7:0]
     7/9: $0\tx_fifo_write_data[7:0]
     8/9: $0\uart_tx_data[7:0]
     9/9: $0\buffer_full[0:0]
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$912'.
     1/2: $0\gpio_value[5:0]
     2/2: $0\gpio_direction[5:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$162'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
     1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$159
     2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$139_DATA[31:0]$158
     3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$139_ADDR[4:0]$157
     4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$160
     5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$151
     6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$155
     7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$154
     8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$139_DATA[31:0]$153
     9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$139_ADDR[4:0]$152
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$136'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$133'.
     1/1: $0\Output[31:0]
Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:14$132'.
     1/1: $1\S[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$130'.
     1/4: $4\immediate[31:0]
     2/4: $3\immediate[31:0]
     3/4: $2\immediate[31:0]
     4/4: $1\immediate[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$129'.
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$128'.
     1/1: $1\csr_data_out[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124'.
     1/1: $1\csr_write_data[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
     1/4: $0\csr_mip_msip[0:0]
     2/4: $0\csr_mip_mtip[0:0]
     3/4: $0\csr_mip_meip[0:0]
     4/4: $0\csr_mip_mfip[15:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
     1/13: $0\csr_mtval[31:0]
     2/13: $0\csr_mtvec[31:0]
     3/13: $0\csr_mstatus_mpie[0:0]
     4/13: $0\csr_mstatus_mie[0:0]
     5/13: $0\csr_mscratch[31:0]
     6/13: $0\csr_minstret[63:0]
     7/13: $0\csr_mie_mtie[0:0]
     8/13: $0\csr_mie_msie[0:0]
     9/13: $0\csr_mie_meie[0:0]
    10/13: $0\csr_mie_mfie[15:0]
    11/13: $0\csr_mepc[31:0]
    12/13: $0\csr_mcycle[63:0]
    13/13: $0\csr_mcause[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$682'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$676'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$81'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:574$80'.
     1/2: $0\clear_hal_byte_one_block_option_2[2:0]
     2/2: $0\clear_hal_byte_one_block_option[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:564$79'.
     1/1: $0\wb_filter[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
     1/21: $0\write_data_in[0:0]
     2/21: $0\save_value_2[0:0]
     3/21: $0\save_value[0:0]
     4/21: $0\control_memory_op[0:0]
     5/21: $0\save_address[0:0]
     6/21: $0\control_unit_aluop[3:0]
     7/21: $0\alu_input_selector[0:0]
     8/21: $0\csr_write_enable[0:0]
     9/21: $0\is_immediate[0:0]
    10/21: $0\reg_write[0:0]
    11/21: $0\alu_src_a[2:0]
    12/21: $0\alu_src_b[2:0]
    13/21: $0\aluop[1:0]
    14/21: $0\pc_source[0:0]
    15/21: $0\ir_write[0:0]
    16/21: $0\memory_to_reg[2:0]
    17/21: $0\memory_write[0:0]
    18/21: $0\memory_read[0:0]
    19/21: $0\lorD[1:0]
    20/21: $0\pc_write[0:0]
    21/21: $0\pc_write_cond[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:139$34'.
     1/10: $10\nextstate[5:0]
     2/10: $9\nextstate[5:0]
     3/10: $8\nextstate[5:0]
     4/10: $7\nextstate[5:0]
     5/10: $6\nextstate[5:0]
     6/10: $5\nextstate[5:0]
     7/10: $4\nextstate[5:0]
     8/10: $3\nextstate[5:0]
     9/10: $2\nextstate[5:0]
    10/10: $1\nextstate[5:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:131$33'.
     1/1: $0\state[5:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
     1/4: $4\aluop_out[3:0]
     2/4: $3\aluop_out[3:0]
     3/4: $2\aluop_out[3:0]
     4/4: $1\aluop_out[3:0]
Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.
     1/1: $1\ALU_out_S[31:0]

22.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$1041'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$984'.
No latch inferred for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.\read_data' from process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:45$975'.
No latch inferred for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\read_data' from process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$928'.
No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:17$137_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$162'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:14$132'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$130'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_code' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$129'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_interrupt_flag' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$129'.
No latch inferred for signal `\CSR_Unit.\csr_utime' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$129'.
No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$128'.
No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124'.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [0]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [1]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [2]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [3]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [4]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [5]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [6]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [7]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [8]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [9]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [10]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [11]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [12]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [13]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [14]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [15]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [16]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [17]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [18]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [19]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [20]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [21]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [22]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [23]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [24]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [25]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [26]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [27]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [28]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [29]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [30]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [31]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:574$80'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:574$80`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:574$80`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:574$80`.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:574$80'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:574$80`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:574$80`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:574$80`.
No latch inferred for signal `\Control_Unit.\wb_filter' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:564$79'.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\alu_input_selector' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_input_selector` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\save_address' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_address` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\save_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\save_value_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value_2` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\control_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_memory_op` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\write_data_in' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\write_data_in` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\control_unit_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'1 for non-memory siginal `\Control_Unit.\control_unit_memory_op [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\control_unit_aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:139$34'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:139$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:139$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:139$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:139$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [4]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:139$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [5]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:139$34`.
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26': $auto$proc_dlatch.cc:433:proc_dlatch$2842
No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.

22.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$673'.
  created $dff cell `$procdff$2865' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$609_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$610_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$611_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$612_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$613_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$614_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$615_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$616_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$617_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$618_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$619_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$620_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$621_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$622_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$623_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$624_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$625'.
  created $dff cell `$procdff$2866' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$624_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$625'.
  created $dff cell `$procdff$2867' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$624_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$625'.
  created $dff cell `$procdff$2868' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$549_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$550_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$551_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$552_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$553_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$554_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$555_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$556_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$557_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$558_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$559_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$560_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$561_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$562_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$563_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$564_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$565_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$567'.
  created $dff cell `$procdff$2869' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$565_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$567'.
  created $dff cell `$procdff$2870' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$565_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$567'.
  created $dff cell `$procdff$2871' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$566'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$888'.
  created $dff cell `$procdff$2872' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$888'.
  created $dff cell `$procdff$2873' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$888'.
  created $dff cell `$procdff$2874' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$888'.
  created $dff cell `$procdff$2875' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$888'.
  created $dff cell `$procdff$2876' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1070'.
  created $dff cell `$procdff$2877' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1070'.
  created $dff cell `$procdff$2878' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$1068'.
  created $dff cell `$procdff$2879' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$1060'.
  created $dff cell `$procdff$2880' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$1057'.
  created $dff cell `$procdff$2881' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$1051'.
  created $dff cell `$procdff$2882' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1046'.
  created $dff cell `$procdff$2883' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1046'.
  created $dff cell `$procdff$2884' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$1032'.
  created $dff cell `$procdff$2885' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$1019'.
  created $dff cell `$procdff$2886' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$1017'.
  created $dff cell `$procdff$2887' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$1009'.
  created $dff cell `$procdff$2888' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$995'.
  created $dff cell `$procdff$2889' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$989'.
  created $dff cell `$procdff$2890' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$989'.
  created $dff cell `$procdff$2891' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:239$775'.
  created $dff cell `$procdff$2892' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:239$775'.
  created $dff cell `$procdff$2893' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:239$775'.
  created $dff cell `$procdff$2894' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:239$775'.
  created $dff cell `$procdff$2895' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:239$775'.
  created $dff cell `$procdff$2896' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:239$775'.
  created $dff cell `$procdff$2897' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:239$775'.
  created $dff cell `$procdff$2898' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:239$775'.
  created $dff cell `$procdff$2899' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg3' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:239$775'.
  created $dff cell `$procdff$2900' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$938'.
  created $dff cell `$procdff$2901' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$938'.
  created $dff cell `$procdff$2902' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$938'.
  created $dff cell `$procdff$2903' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$938'.
  created $dff cell `$procdff$2904' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$938'.
  created $dff cell `$procdff$2905' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$938'.
  created $dff cell `$procdff$2906' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$938'.
  created $dff cell `$procdff$2907' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$938'.
  created $dff cell `$procdff$2908' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$938'.
  created $dff cell `$procdff$2909' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$286'.
  created $dff cell `$procdff$2910' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_en' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$914'.
  created $dff cell `$procdff$2911' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$914'.
  created $dff cell `$procdff$2912' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$914'.
  created $dff cell `$procdff$2913' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$914'.
  created $dff cell `$procdff$2914' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$914'.
  created $dff cell `$procdff$2915' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\buffer_full' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$914'.
  created $dff cell `$procdff$2916' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$914'.
  created $dff cell `$procdff$2917' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$914'.
  created $dff cell `$procdff$2918' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$914'.
  created $dff cell `$procdff$2919' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$912'.
  created $dff cell `$procdff$2920' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$912'.
  created $dff cell `$procdff$2921' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
  created $dff cell `$procdff$2922' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$139_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
  created $dff cell `$procdff$2923' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$139_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
  created $dff cell `$procdff$2924' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
  created $dff cell `$procdff$2925' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
  created $dff cell `$procdff$2926' with positive edge clock.
Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$133'.
  created $dff cell `$procdff$2927' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mfip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
  created $dff cell `$procdff$2928' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_meip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
  created $dff cell `$procdff$2929' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mtip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
  created $dff cell `$procdff$2930' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_msip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
  created $dff cell `$procdff$2931' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2932' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcycle' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2933' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2934' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mfie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2935' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_meie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2936' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_msie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2937' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mtie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2938' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_minstret' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2939' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2940' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2941' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mpie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2942' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2943' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$2944' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$676'.
  created $dff cell `$procdff$2945' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$676'.
  created $dff cell `$procdff$2946' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$676'.
  created $dff cell `$procdff$2947' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:131$33'.
  created $dff cell `$procdff$2948' with positive edge clock.

22.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$674'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$673'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$673'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$648'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$625'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$591'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$567'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$566'.
Found and cleaned up 3 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$888'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$888'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$1072'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1070'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1070'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$1068'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$1068'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$1060'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$1060'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$1057'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$1057'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$1051'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$1051'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1046'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1046'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$1041'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$1041'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$1032'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$1032'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$1025'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$1019'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$1019'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$1017'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$1017'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$1009'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$1009'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$995'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$995'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$989'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$989'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$984'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$984'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$781'.
Found and cleaned up 5 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:239$775'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:239$775'.
Found and cleaned up 1 empty switch in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:45$975'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:45$975'.
Found and cleaned up 3 empty switches in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$938'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$938'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$289'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$286'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$286'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$931'.
Found and cleaned up 1 empty switch in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$928'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$928'.
Found and cleaned up 5 empty switches in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$914'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$914'.
Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$912'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$912'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$162'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:24$144'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$136'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$133'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$133'.
Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:14$132'.
Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:14$132'.
Found and cleaned up 4 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$130'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$130'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$129'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$128'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$128'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$682'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$676'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$676'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$81'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:574$80'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:574$80'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:564$79'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:564$79'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:252$66'.
Found and cleaned up 10 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:139$34'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:139$34'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:131$33'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:131$33'.
Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.
Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:23$11'.
Cleaned up 101 empty switches.

22.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~4 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~9 debug messages>
Optimizing module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
<suppressed ~5 debug messages>
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
<suppressed ~9 debug messages>
Optimizing module GPIO.
<suppressed ~3 debug messages>
Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
<suppressed ~4 debug messages>
Optimizing module BUS.
Optimizing module Registers.
<suppressed ~2 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
<suppressed ~1 debug messages>
Optimizing module CSR_Unit.
<suppressed ~2 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module Control_Unit.
<suppressed ~25 debug messages>
Optimizing module ALU_Control.
<suppressed ~15 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC.
Optimizing module top.

22.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
Deleting now unused module LEDs.
Deleting now unused module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Deleting now unused module GPIO.
Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module Alu.
Deleting now unused module $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC.
<suppressed ~30 debug messages>

22.6. Executing TRIBUF pass.

22.7. Executing DEMINOUT pass (demote inout ports to input or output).

22.8. Executing OPT_EXPR pass (perform const folding).
[Pipeline] sh
Optimizing module top.
<suppressed ~47 debug messages>

22.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 63 unused cells and 828 unused wires.
<suppressed ~84 debug messages>

22.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [15] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [14] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [13] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [12] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [11] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [10] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [9] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [8] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [7] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [6] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [5] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [4] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [3] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [2] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [1] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [0] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_external is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_timer is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_software is used but has no driver.
Found and reported 19 problems.

22.11. Executing OPT pass (performing simple optimizations).

22.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~11 debug messages>

22.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~822 debug messages>
Removed a total of 274 cells.

22.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2430.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2448.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2469.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2494.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2527.
    dead port 1/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2577.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2579.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2629.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2631.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2680.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2739.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1710.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1712.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1723.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1738.
    dead port 1/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1693.
    dead port 2/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1693.
    dead port 3/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1693.
    dead port 4/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1693.
    dead port 1/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1693.
    dead port 2/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1693.
    dead port 3/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1693.
    dead port 4/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1693.
    dead port 5/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1693.
    dead port 6/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1693.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1653.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1659.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1665.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1671.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1450.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1452.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1459.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1461.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1468.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1470.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1477.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1479.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1486.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1488.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1495.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1497.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1503.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1509.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1515.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1521.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1527.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1533.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1539.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1545.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1551.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1100.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1106.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1112.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1100.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1106.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1112.
Removed 56 multiplexer ports.
<suppressed ~145 debug messages>

22.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2023: { $flatten\SOC.\Core.\Control_Unit.$procmux$2020_CMP $auto$opt_reduce.cc:134:opt_pmux$2999 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2044: $auto$opt_reduce.cc:134:opt_pmux$3001
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2062: $auto$opt_reduce.cc:134:opt_pmux$3003
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2111: $auto$opt_reduce.cc:134:opt_pmux$3005
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2136: $auto$opt_reduce.cc:134:opt_pmux$3007
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2153: { $auto$opt_reduce.cc:134:opt_pmux$3011 $auto$opt_reduce.cc:134:opt_pmux$3009 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2181: $auto$opt_reduce.cc:134:opt_pmux$3013
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2201: $auto$opt_reduce.cc:134:opt_pmux$3015
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2204: $auto$opt_reduce.cc:134:opt_pmux$3017
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2211: { $flatten\SOC.\Core.\Control_Unit.$procmux$2065_CMP $auto$opt_reduce.cc:134:opt_pmux$3029 $auto$opt_reduce.cc:134:opt_pmux$3027 $auto$opt_reduce.cc:134:opt_pmux$3025 $auto$opt_reduce.cc:134:opt_pmux$3023 $auto$opt_reduce.cc:134:opt_pmux$3021 $auto$opt_reduce.cc:134:opt_pmux$3019 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2245: { $flatten\SOC.\Core.\Control_Unit.$procmux$2238_CMP $auto$opt_reduce.cc:134:opt_pmux$3043 $auto$opt_reduce.cc:134:opt_pmux$3041 $auto$opt_reduce.cc:134:opt_pmux$3039 $flatten\SOC.\Core.\Control_Unit.$procmux$2160_CMP $auto$opt_reduce.cc:134:opt_pmux$3037 $flatten\SOC.\Core.\Control_Unit.$procmux$2157_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2156_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2155_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2154_CMP $auto$opt_reduce.cc:134:opt_pmux$3035 $auto$opt_reduce.cc:134:opt_pmux$3033 $auto$opt_reduce.cc:134:opt_pmux$3031 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2802: { $flatten\SOC.\Core.\ALU_Control.$procmux$2809_CMP $auto$opt_reduce.cc:134:opt_pmux$3045 $flatten\SOC.\Core.\ALU_Control.$procmux$2806_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2805_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2804_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2803_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2816: { $auto$opt_reduce.cc:134:opt_pmux$3049 $auto$opt_reduce.cc:134:opt_pmux$3047 $flatten\SOC.\Core.\ALU_Control.$procmux$2809_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2825: { $flatten\SOC.\Core.\ALU_Control.$procmux$2827_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2826_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2280: { $auto$opt_reduce.cc:134:opt_pmux$3051 $flatten\SOC.\Core.\Control_Unit.$procmux$2216_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2287: $auto$opt_reduce.cc:134:opt_pmux$3053
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2338: { $flatten\SOC.\Core.\Control_Unit.$procmux$2209_CMP $auto$opt_reduce.cc:134:opt_pmux$3055 $flatten\SOC.\Core.\Control_Unit.$procmux$2197_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2354: $auto$opt_reduce.cc:134:opt_pmux$3057
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2376: $auto$opt_reduce.cc:134:opt_pmux$3059
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2394: { $auto$opt_reduce.cc:134:opt_pmux$3063 $auto$opt_reduce.cc:134:opt_pmux$3061 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2406: $auto$opt_reduce.cc:134:opt_pmux$3065
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2728: { $auto$opt_reduce.cc:134:opt_pmux$3067 $flatten\SOC.\Core.\Control_Unit.$procmux$2736_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2735_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2734_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2733_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2732_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2731_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2730_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2729_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2743: { $flatten\SOC.\Core.\Control_Unit.$procmux$2274_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2243_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2242_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2381_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2117_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2215_CMP $auto$opt_reduce.cc:134:opt_pmux$3071 $flatten\SOC.\Core.\Control_Unit.$procmux$2167_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2208_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2240_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2116_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2166_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2238_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2115_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2099_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2066_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2065_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2162_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2233_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2064_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2160_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2159_CMP $auto$opt_reduce.cc:134:opt_pmux$3069 $flatten\SOC.\Core.\Control_Unit.$procmux$2227_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2046_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2226_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2113_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2157_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2156_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2063_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2155_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2154_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2220_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1752: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1773_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1772_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1765_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1764_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1763_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1762_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1761_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1760_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1759_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1758_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1757_CMP $auto$opt_reduce.cc:134:opt_pmux$3079 $auto$opt_reduce.cc:134:opt_pmux$3077 $auto$opt_reduce.cc:134:opt_pmux$3075 $auto$opt_reduce.cc:134:opt_pmux$3073 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1735: $auto$opt_reduce.cc:134:opt_pmux$3081
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1741: { $flatten\SOC.\Core.\Control_Unit.$procmux$2733_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2734_CMP $auto$opt_reduce.cc:134:opt_pmux$3085 $flatten\SOC.\Core.\Control_Unit.$procmux$2735_CMP $auto$opt_reduce.cc:134:opt_pmux$3083 $flatten\SOC.\Core.\Control_Unit.$procmux$2729_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2737_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1650:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1668:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1674:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1447:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1447_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1447_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1447_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] $flatten\SOC.\Memory.$procmux$1447_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1474:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1474_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1474_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1474_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] $flatten\SOC.\Memory.$procmux$1474_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1501:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1501_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1501_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1501_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] $flatten\SOC.\Memory.$procmux$1501_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1097:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1097_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1097_Y [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$1097_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$1097_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1097_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1097_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1097_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1097_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1097_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1097_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1097:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1097_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1097_Y [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$1097_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$1097_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1097_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1097_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1097_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1097_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1097_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1097_Y [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1677:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$160, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1668_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1680:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$159, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1650_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1519:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$974, B=0, Y=$flatten\SOC.\Memory.$procmux$1519_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1474_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1519_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1519_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] $flatten\SOC.\Memory.$procmux$1519_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1537:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$971, B=0, Y=$flatten\SOC.\Memory.$procmux$1537_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1447_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1537_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1537_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] $flatten\SOC.\Memory.$procmux$1537_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1572:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$961, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1501_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_EN[31:0]$941 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1115:
      Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$900, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891
      New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1097_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1115:
      Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$900, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891
      New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1097_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_EN[7:0]$891 [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1554:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$967, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1519_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_EN[31:0]$947 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1563:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$964, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1537_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_EN[31:0]$944 [0] }
  Optimizing cells in module \top.
Performed a total of 43 changes.

22.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~18 debug messages>
Removed a total of 6 cells.

22.11.6. Executing OPT_DFF pass (perform DFF optimizations).

22.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+ mkdir -p Risco-5/impl/pnr
Finding unused cells or wires in module \top..
Removed 2 unused cells and 338 unused wires.
<suppressed ~3 debug messages>

22.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.9. Rerunning OPT passes. (Maybe there is more to do..)

22.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~144 debug messages>

22.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2245: { $flatten\SOC.\Core.\Control_Unit.$procmux$2238_CMP $auto$opt_reduce.cc:134:opt_pmux$3043 $auto$opt_reduce.cc:134:opt_pmux$3041 $auto$opt_reduce.cc:134:opt_pmux$3039 $flatten\SOC.\Core.\Control_Unit.$procmux$2160_CMP $auto$opt_reduce.cc:134:opt_pmux$3037 $auto$opt_reduce.cc:134:opt_pmux$3089 $auto$opt_reduce.cc:134:opt_pmux$3087 $auto$opt_reduce.cc:134:opt_pmux$3035 $auto$opt_reduce.cc:134:opt_pmux$3033 $auto$opt_reduce.cc:134:opt_pmux$3031 }
  Optimizing cells in module \top.
Performed a total of 1 changes.

22.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.11.13. Executing OPT_DFF pass (perform DFF optimizations).

22.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.16. Rerunning OPT passes. (Maybe there is more to do..)

22.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~144 debug messages>

22.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.11.20. Executing OPT_DFF pass (perform DFF optimizations).

22.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.23. Finished OPT passes. (There is nothing left to do.)

22.12. Executing FSM pass (extract and optimize FSM).

22.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.CSR_Unit.csr_mip_mfip as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state.
Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.

22.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$2879
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1034_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1049_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1062_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1048_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1062_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$1053_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1049_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1048_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1034_Y
  ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1034_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1048_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1049_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$1053_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1062_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'0--0 ->      3'001 8'01010001
  transition:      3'000 4'1--0 ->      3'000 8'01010000
  transition:      3'000 4'---1 ->      3'000 8'01010000
  transition:      3'010 4'--00 ->      3'010 8'00100010
  transition:      3'010 4'--10 ->      3'011 8'00100011
  transition:      3'010 4'---1 ->      3'000 8'00100000
  transition:      3'001 4'-0-0 ->      3'001 8'00011001
  transition:      3'001 4'-1-0 ->      3'010 8'00011010
  transition:      3'001 4'---1 ->      3'000 8'00011000
  transition:      3'011 4'-0-0 ->      3'011 8'10010011
  transition:      3'011 4'-1-0 ->      3'000 8'10010000
  transition:      3'011 4'---1 ->      3'000 8'10010000

22.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3090' from module `\top'.

22.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 7 unused cells and 7 unused wires.
<suppressed ~8 debug messages>

22.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3090' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].

22.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3090' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

22.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3090' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$3090 (\SOC.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_rx.payload_done
    2: \SOC.Uart.i_uart_rx.next_bit
    3: \SOC.Uart.i_uart_rx.rxd_reg

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1062_Y
    1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$1053_Y
    2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1049_Y
    3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1048_Y
    4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1034_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'1--0   ->     0 5'01010
      1:     0 4'---1   ->     0 5'01010
      2:     0 4'0--0   ->     2 5'01010
      3:     1 4'---1   ->     0 5'00100
      4:     1 4'--00   ->     1 5'00100
      5:     1 4'--10   ->     3 5'00100
      6:     2 4'---1   ->     0 5'00011
      7:     2 4'-1-0   ->     1 5'00011
      8:     2 4'-0-0   ->     2 5'00011
      9:     3 4'-1-0   ->     0 5'10010
     10:     3 4'---1   ->     0 5'10010
     11:     3 4'-0-0   ->     3 5'10010

-------------------------------------

22.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3090' from module `\top'.

22.13. Executing OPT pass (performing simple optimizations).

22.13.1. Executing OPT_EXPR pass (perform const folding).
[Pipeline] sh
Optimizing module top.
<suppressed ~5 debug messages>

22.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

22.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~143 debug messages>

22.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2891 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1381_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1375_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1366_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1357_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1348_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1339_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1321_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1330_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3140 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$3140 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1375_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1366_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1357_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1348_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1339_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1321_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1330_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2889 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1297_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3145 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1297_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2888 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1286_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3151 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1016_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2887 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2886 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1275_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$3156 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1275_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2885 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1264_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3162 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2884 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1241_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1232_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1223_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1214_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1205_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1196_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1178_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1187_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3164 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2882 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1160_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3168 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1056_Y, Q = \SOC.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2881 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1155_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3172 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2880 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1147_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3174 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1067_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2878 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2877 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2873 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1124_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3180 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$903_Y, Q = \SOC.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2872 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1129_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3182 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$908_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2873 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1124_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3184 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$903_Y, Q = \SOC.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2872 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1129_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3186 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$908_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2919 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1615_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3188 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2918 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1620_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3190 ($sdff) from module top (D = \SOC.Uart.write_data [7:0], Q = \SOC.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2917 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1625_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3192 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2915 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1590_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2914 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1595_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2913 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1600_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2911 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1605_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$2910 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1580_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3198 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2921 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1636_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3200 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2920 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1644_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3204 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2927 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1688_Y, Q = \SOC.Core.Pc.Output, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3210 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2948 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 6'000000).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2944 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1796_Y, Q = \SOC.Core.CSR_Unit.csr_mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3213 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mtval).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2943 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 1'0 \SOC.Core.CSR_Unit.csr_write_data [0] }, Q = \SOC.Core.CSR_Unit.csr_mtvec).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2942 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1822_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$3222 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2941 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1839_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3226 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mstatus_mie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2940 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1855_Y, Q = \SOC.Core.CSR_Unit.csr_mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3230 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mscratch).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2939 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1868_Y, Q = \SOC.Core.CSR_Unit.csr_minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3234 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1868_Y, Q = \SOC.Core.CSR_Unit.csr_minstret).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2938 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1886_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mtie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3238 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mie_mtie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2937 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1904_Y, Q = \SOC.Core.CSR_Unit.csr_mie_msie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3242 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mie_msie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2936 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1922_Y, Q = \SOC.Core.CSR_Unit.csr_mie_meie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3246 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [11], Q = \SOC.Core.CSR_Unit.csr_mie_meie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2935 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1940_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mfie, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3250 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [31:16], Q = \SOC.Core.CSR_Unit.csr_mie_mfie).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2934 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.csr_mepc).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2933 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1963_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3259 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1963_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2932 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1974_Y, Q = \SOC.Core.CSR_Unit.csr_mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3263 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mcause).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2931 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_software, Q = \SOC.Core.CSR_Unit.csr_mip_msip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2930 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_timer, Q = \SOC.Core.CSR_Unit.csr_mip_mtip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2929 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_external, Q = \SOC.Core.CSR_Unit.csr_mip_meip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2928 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_fast, Q = \SOC.Core.CSR_Unit.csr_mip_mfip, rval = 16'0000000000000000).
Adding EN signal on $flatten\SOC.\Core.$procdff$2900 ($dff) from module top (D = \SOC.Core.alu_out_register, Q = \SOC.Core.temp_reg3).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2899 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1418_Y, Q = \SOC.Core.temp_reg2, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3276 ($sdff) from module top (D = \SOC.Core.memory_register, Q = \SOC.Core.temp_reg2).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2898 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1423_Y, Q = \SOC.Core.temp_reg1, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3278 ($sdff) from module top (D = \SOC.Core.alu_out_register, Q = \SOC.Core.temp_reg1).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2897 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1428_Y, Q = \SOC.Core.pc_old, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3280 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2896 ($dff) from module top (D = \SOC.Core.register_data_2_out, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2895 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2894 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2893 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2892 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1433_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3286 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2947 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2946 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2945 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3254 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3254 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3217 ($dffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$3199 ($sdffe) from module top.

22.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 136 unused cells and 132 unused wires.
<suppressed ~137 debug messages>

22.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

22.13.9. Rerunning OPT passes. (Maybe there is more to do..)

22.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~98 debug messages>

22.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$3170: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o }
  Optimizing cells in module \top.
Performed a total of 1 changes.

22.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~18 debug messages>
Removed a total of 6 cells.

22.13.13. Executing OPT_DFF pass (perform DFF optimizations).

22.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 7 unused wires.
<suppressed ~2 debug messages>

22.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.16. Rerunning OPT passes. (Maybe there is more to do..)

22.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~98 debug messages>

22.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.20. Executing OPT_DFF pass (perform DFF optimizations).

22.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.23. Finished OPT passes. (There is nothing left to do.)

22.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2953 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2955 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:17$161 (SOC.Core.RegisterBank.registers).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2950 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2951 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2952 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$976 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$936 (SOC.Memory.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2949 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$887 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2949 (SOC.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$887 (SOC.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1991_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$680 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$679 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$679 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$678 ($lt).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3299 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3294 ($ne).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$911 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1587_CMP0 ($eq).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$procmux$1586 ($pmux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1121 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1109 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$908 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$907 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$901 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$883 ($eq).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1121 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1109 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$908 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$907 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$901 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$883 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$1045 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$1044 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$1043 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$1042 ($mux).
Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:111$1037 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:109$1035 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$1011 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$1003 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$1001 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$998 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$997 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$993 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$988 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$987 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$986 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$985 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$981 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$979 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$285 ($mux).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$165 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$168 ($ge).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$169 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$172 ($ge).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$173 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$176 ($ge).
Removed top 22 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$177 ($le).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:75$207 ($mux).
Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:84$223 ($mux).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$237 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Memory.$procmux$1443_CMP0 ($eq).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1560 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1569 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1578 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1700_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1700_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1699_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1698_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1700_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1699_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1698_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1700_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1699_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1698_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2737_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2736_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2735_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2732_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2731_CMP0 ($eq).
Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2728 ($pmux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2627 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2574 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2525 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2492 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2446 ($mux).
Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2381_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2357_CMP0 ($eq).
Removed top 5 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2243_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2242_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2240_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2238_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2233_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2219_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2217_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2216_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2215_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2213_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2212_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2209_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2208_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2207_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2206_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2203_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2202_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2197_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2167_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2166_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2162_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2161_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2117_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2116_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2115_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2099_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2066_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2065_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2064_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2023 ($pmux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2021_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2020_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:474$75 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:454$69 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:203$48 ($eq).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:159$35 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:100$32 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2827_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2809_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2808_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2807_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2795 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2840_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2839_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2838_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2837_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1778_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1765_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1764_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1763_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1762_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1761_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1760_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1759_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1758_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1757_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$121 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$119 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$118 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$164 ($ge).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1513 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1531 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1549 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1465 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1492 ($mux).
Removed top 19 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$215 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$679_Y.
Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$237_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25_Y.
Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0].
Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$6\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$7\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$9\nextstate[5:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:454$69_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:474$75_Y.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_ADDR[31:0]$939.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_ADDR[31:0]$942.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_ADDR[31:0]$945.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$932_ADDR[31:0]$959.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_ADDR[31:0]$962.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_ADDR[31:0]$965.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$933_ADDR[31:0]$969.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$934_ADDR[31:0]$972.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_ADDR[5:0]$889.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_ADDR[5:0]$898.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$907_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$908_Y.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_ADDR[5:0]$889.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$877_ADDR[5:0]$898.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$907_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$908_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$1042_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$1043_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$1044_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$1045_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$985_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$986_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$987_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$988_Y.

22.15. Executing PEEPOPT pass (run peephole optimizers).
+ cd Risco-5/fpga/tangnano20k/
+ /eda/gowin/IDE/bin/gw_sh run.tcl
*** GOWIN Tcl Command Line Console  *** 
current device: GW2AR-18C  GW2AR-LV18QN88C8/I7
add new file: "pinout.cst"
add new file: "top.sdc"
add new file: "main.v"
add new file: "../../debug/reset.v"
add new file: "../../src/core/alu_control.v"
add new file: "../../src/core/alu.v"
add new file: "../../src/core/control_unit.v"
add new file: "../../src/core/core.v"
add new file: "../../src/core/immediate_generator.v"
add new file: "../../src/core/mux.v"
add new file: "../../src/core/pc.v"
add new file: "../../src/core/registers.v"
add new file: "../../src/core/csr_unit.v"
add new file: "../../src/peripheral/bus.v"
add new file: "../../src/peripheral/gpio.v"
add new file: "../../src/peripheral/gpios.v"
add new file: "../../src/peripheral/leds.v"
add new file: "../../src/peripheral/memory.v"
add new file: "../../src/peripheral/soc.v"
add new file: "../../src/peripheral/uart_rx.v"
add new file: "../../src/peripheral/uart_tx.v"
add new file: "../../src/peripheral/uart.v"
add new file: "../../src/peripheral/fifo.v"
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v'
Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":139)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v'
WARN  (EX3801) : Parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":17)
WARN  (EX3801) : Parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":18)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v'
WARN  (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":40)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v'
WARN  (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18)
Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1)
Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37)
Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/fpga_test_3.hex")'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1)
WARN  (EX3073) : Port 'interrupt_on_hold' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":237)
Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":1)
Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1)
Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1)
Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1)
Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":454)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":461)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":474)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":481)
Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1)
WARN  (EX2420) : Latch inferred for net 'aluop_out[3]'; We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":57)
Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1)
Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1)
Compiling module 'CSR_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1)
WARN  (EX3780) : Using initial value of 'csr_utime' since it is never assigned("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":114)

22.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 39 unused wires.
<suppressed ~1 debug messages>

22.17. Executing SHARE pass (SAT-based resource sharing).
Found 5 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$887 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:57$174_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:55$170_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$166_Y $flatten\SOC.\Uart.$procmux$1589_CMP $flatten\SOC.\Uart.$procmux$1588_CMP $flatten\SOC.\Uart.$procmux$1587_CMP }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$936 ($memrd):
    Found 7 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1444_CMP $flatten\SOC.\Memory.$procmux$1443_CMP $flatten\SOC.\Memory.$procmux$1442_CMP $flatten\SOC.\Memory.$procmux$1441_CMP \SOC.Memory.option [1:0] $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$166_Y \SOC.Bus.slave_0_write \SOC.Bus.slave_0_read }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\RegisterBank.$memrd$\registers$Risco-5/src/core/registers.v:22$143 ($memrd):
    Found 11 activation_patterns using ctrl signal { $flatten\SOC.\Core.\Alu.$procmux$2831_CMP $flatten\SOC.\Core.\Alu.$procmux$2832_CMP $flatten\SOC.\Core.\Alu.$procmux$2833_CMP $flatten\SOC.\Core.\Alu.$procmux$2834_CMP $flatten\SOC.\Core.\Alu.$procmux$2835_CMP $flatten\SOC.\Core.\Alu.$procmux$2836_CMP $flatten\SOC.\Core.\Alu.$procmux$2837_CMP $flatten\SOC.\Core.\Alu.$procmux$2838_CMP $flatten\SOC.\Core.\Alu.$procmux$2839_CMP $flatten\SOC.\Core.\Alu.$procmux$2840_CMP $flatten\SOC.\Core.\Alu.$procmux$2841_CMP $flatten\SOC.\Core.\AluInputBMUX.$procmux$1698_CMP }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:44$23 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2832_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:42$22 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2833_CMP.
    No candidates found.

22.18. Executing TECHMAP pass (map to technology primitives).

22.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

22.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~296 debug messages>

22.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.21. Executing TECHMAP pass (map to technology primitives).

22.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

22.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

22.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

22.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$679 ($add).
  creating $macc model for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:134$764 ($add).
  creating $macc model for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:132$763 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15 ($sub).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$116 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$117 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$118 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$119 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$120 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$121 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$880 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$902 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$907 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$880 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$902 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$907 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1056 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1067 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$1005 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1016 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1016.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$1005.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1067.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1056.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$907.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$902.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$880.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$907.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$902.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$880.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$121.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$120.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$119.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$118.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$117.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$116.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14.
  creating $alu model for $macc $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:132$763.
  creating $alu model for $macc $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:134$764.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$679.
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$678 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$164 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$168 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$172 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$176 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$165 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$169 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$173 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$177 ($le): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$680 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$678.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21 ($eq): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24.
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$177: $auto$alumacc.cc:485:replace_alu$3363
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$173: $auto$alumacc.cc:485:replace_alu$3376
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$169: $auto$alumacc.cc:485:replace_alu$3389
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$165: $auto$alumacc.cc:485:replace_alu$3402
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$176: $auto$alumacc.cc:485:replace_alu$3415
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$172: $auto$alumacc.cc:485:replace_alu$3424
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$168: $auto$alumacc.cc:485:replace_alu$3433
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$164: $auto$alumacc.cc:485:replace_alu$3442
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$678, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$680: $auto$alumacc.cc:485:replace_alu$3451
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$679: $auto$alumacc.cc:485:replace_alu$3462
  creating $alu cell for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:134$764: $auto$alumacc.cc:485:replace_alu$3465
  creating $alu cell for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:132$763: $auto$alumacc.cc:485:replace_alu$3468
  creating $alu cell for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21: $auto$alumacc.cc:485:replace_alu$3471
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14: $auto$alumacc.cc:485:replace_alu$3484
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15: $auto$alumacc.cc:485:replace_alu$3487
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$116: $auto$alumacc.cc:485:replace_alu$3490
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$117: $auto$alumacc.cc:485:replace_alu$3493
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$118: $auto$alumacc.cc:485:replace_alu$3496
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$119: $auto$alumacc.cc:485:replace_alu$3499
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$120: $auto$alumacc.cc:485:replace_alu$3502
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$121: $auto$alumacc.cc:485:replace_alu$3505
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$902: $auto$alumacc.cc:485:replace_alu$3508
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$880: $auto$alumacc.cc:485:replace_alu$3511
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$907: $auto$alumacc.cc:485:replace_alu$3514
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$902: $auto$alumacc.cc:485:replace_alu$3517
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$880: $auto$alumacc.cc:485:replace_alu$3520
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$907: $auto$alumacc.cc:485:replace_alu$3523
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1056: $auto$alumacc.cc:485:replace_alu$3526
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1067: $auto$alumacc.cc:485:replace_alu$3529
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$1005: $auto$alumacc.cc:485:replace_alu$3532
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1016: $auto$alumacc.cc:485:replace_alu$3535
  created 31 $alu and 0 $macc cells.

22.23. Executing OPT pass (performing simple optimizations).

22.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

22.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~10 debug messages>
Removed a total of 2 cells.

22.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~98 debug messages>

22.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.23.6. Executing OPT_DFF pass (perform DFF optimizations).

22.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 20 unused wires.
<suppressed ~2 debug messages>

22.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.23.9. Rerunning OPT passes. (Maybe there is more to do..)

22.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~98 debug messages>

22.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.23.13. Executing OPT_DFF pass (perform DFF optimizations).

22.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
WARN  (EX2565) : Input 'response' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":196)
WARN  (EX2565) : Input 'save_pc' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":237)
Compiling module 'Memory(MEMORY_FILE="../../software/memory/fpga_test_3.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":15)
Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1)
Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1)
WARN  (EX3791) : Expression size 33 truncated to fit in target size 32("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":21)
Compiling module 'UART(CLOCK_FREQ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1)
Compiling module 'FIFO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":15)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":35)
Compiling module 'uart_tool_rx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":10)
Compiling module 'uart_tool_tx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":10)
Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1)
Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1)
WARN  (EX2565) : Input 'instruction_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
NOTE  (EX0101) : Current top module is "top"
WARN  (EX0211) : The output port "interrupt_on_hold" of module "CSR_Unit" has no driver, assigning undriven bits to Z, simulation mismatch possible("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":20)
[5%] Running netlist conversion ...
WARN  (CV0016) : Input reset is unused("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":3)
Finding unused cells or wires in module \top..

22.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.23.16. Finished OPT passes. (There is nothing left to do.)

22.24. Executing MEMORY pass.

22.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

22.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

22.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Core.RegisterBank.registers write port 0.
  Analyzing top.SOC.Core.RegisterBank.registers write port 1.
  Analyzing top.SOC.Core.RegisterBank.registers write port 2.
  Analyzing top.SOC.Memory.memory write port 0.
  Analyzing top.SOC.Memory.memory write port 1.
  Analyzing top.SOC.Memory.memory write port 2.
  Analyzing top.SOC.Uart.RX_FIFO.memory write port 0.
  Analyzing top.SOC.Uart.TX_FIFO.memory write port 0.

22.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

22.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[2] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Core.RegisterBank.registers'[1] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.
Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': merged address FF to cell.

22.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 44 unused wires.
<suppressed ~7 debug messages>

22.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
  Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Memory.memory by address:
  Merging ports 0, 1 (address \SOC.Memory.address [12:2]).
  Merging ports 0, 2 (address \SOC.Memory.address [12:2]).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing:
  Checking group clocked with posedge \clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 13 cells.
  Size of unconstrained SAT problem: 103 variables, 281 clauses
  Merging port 1 into port 0.

22.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

22.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>

22.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

22.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 2 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[2]
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted addr FF from read port 0 of top.SOC.Uart.RX_FIFO.memory: $\SOC.Uart.RX_FIFO.memory$rdreg[0]
mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0]
<suppressed ~1084 debug messages>

22.27. Executing TECHMAP pass (map to technology primitives).

22.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

22.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Running device independent optimization ...
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

22.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$8e5e72577b4c3b167a98ad5915719acd6a2ff3f4\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$58f24e643e5858c811559272a02c6d84f974d8a6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b7ec8ee89a7cd4851359941621e9dedf8c3b7d83\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$6d2a7df30888468e46c2233cf858b33a106d24cc\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1a510b238205ce75968c294c5a2f9682007038e9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$d697ed060a7caa7345cbd011d88bf1d0e8cd46a0\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$882b16869816e01f56a454af0eb6e24b6778fa0c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b6fd6d9e43fa3d8e6bc64941b5b57ab422f7e603\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$983d377398e8a630797eecf765a80311ec60d100\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c8ec1437ade7762ec3882c3e3f576764a2f7bb09\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1de9eb29388171a23037c69580dd741dfa07544f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$ccbfc2f8b7417ea49ec4f806e284aeee31f607b3\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b1d6656f42d8fe2eb2a963373a2667cf617d2bc5\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$80ae742e83efa97f5ae3dddd041ab9a1ef9ac7b6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$9a18a5918aa94986c2ace7118a70e41127dc33df\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c4c009ae968ecf5722a8a929fbdc163f47dedcc6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$7e65f9170886a0570d9059c94eef599a8e7c0c53\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$88ca364434c15edf84547ebc10bbf93659adea39\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$219b7093d2a2ec9427a92a1f7d983c7335efd508\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$0f1e956af4a0dd7da6349454a915a33336b22174\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$20534e299f87b4db290b2588b7ce04615b91104c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$73e415998dfd4e0d8b84ec3ac6390921a6a2c53b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$7d81e3db939f1224434306a374696f893743b990\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
Using template $paramod$060a68a0493c8190183716105f9d8172975de01f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1419 debug messages>

22.28. Executing OPT pass (performing simple optimizations).

22.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~103 debug messages>

22.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~30 debug messages>
Removed a total of 10 cells.

22.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $\SOC.Uart.RX_FIFO.memory$rdreg[0] ($dff) from module top (D = $auto$rtlil.cc:2582:Mux$3589, Q = $\SOC.Uart.RX_FIFO.memory$rdreg[0]$q, rval = 3'000).
Adding SRST signal on $auto$ff.cc:266:slice$3288 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1988_Y, Q = \ResetBootSystem.counter, rval = 6'000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3267 ($sdff) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$3270 ($sdff) from module top.

22.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 19 unused cells and 7630 unused wires.
<suppressed ~20 debug messages>

22.28.5. Rerunning OPT passes. (Removed registers in this run.)

22.28.6. Executing OPT_EXPR pass (perform const folding).
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
Optimizing module top.

22.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$6077 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$3314 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

22.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 1 unused wires.
<suppressed ~2 debug messages>

22.28.10. Rerunning OPT passes. (Removed registers in this run.)

22.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.28.13. Executing OPT_DFF pass (perform DFF optimizations).

22.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.28.15. Finished fast OPT passes.

22.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

22.30. Executing OPT pass (performing simple optimizations).

22.30.1. Executing OPT_EXPR pass (perform const folding).
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
Optimizing module top.

22.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$3611: $auto$rtlil.cc:2489:ReduceOr$3605 -> 1'1
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~65 debug messages>

22.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$3596:
      Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Memory.write_data [15:0] }, B=\SOC.Memory.write_data, Y=$auto$rtlil.cc:2582:Mux$3597
      New ports: A=\SOC.Memory.buffer [31:16], B=\SOC.Memory.write_data [31:16], Y=$auto$rtlil.cc:2582:Mux$3597 [31:16]
      New connections: $auto$rtlil.cc:2582:Mux$3597 [15:0] = \SOC.Memory.write_data [15:0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$1997: { $flatten\ResetBootSystem.$procmux$1992_CMP $flatten\ResetBootSystem.$procmux$1991_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2000:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2000_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2000_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2000_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2795:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$3316 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3316 [2]
      New connections: $auto$wreduce.cc:461:run$3316 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2816:
      Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0]
      New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] }
      New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1752: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1773_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1772_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1765_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1764_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1763_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1762_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1761_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1760_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1759_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1758_CMP $auto$opt_reduce.cc:134:opt_pmux$3079 $auto$opt_reduce.cc:134:opt_pmux$3077 $auto$opt_reduce.cc:134:opt_pmux$3075 $auto$opt_reduce.cc:134:opt_pmux$3073 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2153:
      Old ports: A=4'0000, B=8'10001001, Y=\SOC.Core.control_unit_aluop
      New ports: A=2'00, B=4'1011, Y={ \SOC.Core.control_unit_aluop [3] \SOC.Core.control_unit_aluop [0] }
      New connections: \SOC.Core.control_unit_aluop [2:1] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2428:
      Old ports: A=6'000000, B=6'100101, Y=$flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0] [0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0] [0] 2'00 $flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2446:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$3325 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3325 [2]
      New connections: $auto$wreduce.cc:461:run$3325 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2467:
      Old ports: A=6'011111, B=6'100010, Y=$flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0]
      New ports: A=2'01, B=2'10, Y={ $flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0] [5] $flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0] [0] }
      New connections: $flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0] [4:1] = { $flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0] [0] 1'1 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2492:
      Old ports: A=3'110, B=3'011, Y=$auto$wreduce.cc:461:run$3324 [2:0]
      New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$3324 [2] $auto$wreduce.cc:461:run$3324 [0] }
      New connections: $auto$wreduce.cc:461:run$3324 [1] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2525:
      Old ports: A=5'00000, B=5'10010, Y=$auto$wreduce.cc:461:run$3323 [4:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3323 [1]
      New connections: { $auto$wreduce.cc:461:run$3323 [4:2] $auto$wreduce.cc:461:run$3323 [0] } = { $auto$wreduce.cc:461:run$3323 [1] 3'000 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2574:
      Old ports: A=5'00101, B=5'11000, Y=$auto$wreduce.cc:461:run$3322 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3322 [3] $auto$wreduce.cc:461:run$3322 [0] }
      New connections: { $auto$wreduce.cc:461:run$3322 [4] $auto$wreduce.cc:461:run$3322 [2:1] } = { $auto$wreduce.cc:461:run$3322 [3] $auto$wreduce.cc:461:run$3322 [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2627:
      Old ports: A=5'00011, B=5'10110, Y=$auto$wreduce.cc:461:run$3321 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3321 [2] $auto$wreduce.cc:461:run$3321 [0] }
      New connections: { $auto$wreduce.cc:461:run$3321 [4:3] $auto$wreduce.cc:461:run$3321 [1] } = { $auto$wreduce.cc:461:run$3321 [2] 2'01 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2678:
      Old ports: A={ 1'0 $auto$wreduce.cc:461:run$3322 [4:0] }, B={ 1'0 $auto$wreduce.cc:461:run$3321 [4:0] }, Y=$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0]
      New ports: A=$auto$wreduce.cc:461:run$3322 [4:0], B=$auto$wreduce.cc:461:run$3321 [4:0], Y=$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0] [4:0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0] [5] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:100$32:
      Old ports: A=2'11, B=2'01, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1:0]
      New ports: A=1'1, B=1'0, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1]
      New connections: \SOC.Core.Control_Unit.second_block_write_src_b [0] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1708:
      Old ports: A={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] }, B={ 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [24], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [31:6] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] \SOC.Core.instruction_register [24:20] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1735:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, B={ 19'0000000000000000000 \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [31], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:14] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1440:
      Old ports: A=\SOC.Memory.buffer, B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7:0] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:0] 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data
      New ports: A=\SOC.Memory.buffer [31:8], B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:8] 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8]
      New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1259:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$3344 [0] 1'0 $auto$wreduce.cc:461:run$3345 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$3347 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$3344 [0] $auto$wreduce.cc:461:run$3345 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$3347 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$1045:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3347 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3347 [0]
      New connections: $auto$wreduce.cc:461:run$3347 [1] = $auto$wreduce.cc:461:run$3347 [0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1396:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$3349 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$3351 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$3349 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$3351 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$988:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3351 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3351 [0]
      New connections: $auto$wreduce.cc:461:run$3351 [1] = $auto$wreduce.cc:461:run$3351 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$3600:
      Old ports: A=$auto$rtlil.cc:2582:Mux$3597, B={ \SOC.Memory.buffer [31:8] \SOC.Memory.write_data [7:0] }, Y=$auto$rtlil.cc:2582:Mux$3601
      New ports: A={ $auto$rtlil.cc:2582:Mux$3597 [31:16] \SOC.Memory.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$3601 [31:8]
      New connections: $auto$rtlil.cc:2582:Mux$3601 [7:0] = \SOC.Memory.write_data [7:0]
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2006:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2000_Y, Y=$flatten\ResetBootSystem.$procmux$2006_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2000_Y [1], Y=$flatten\ResetBootSystem.$procmux$2006_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2006_Y [0] = 1'0
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1719:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0]
      New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12:5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] }
  Optimizing cells in module \top.
Performed a total of 29 changes.

22.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

22.30.6. Executing OPT_DFF pass (perform DFF optimizations).

22.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

22.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~1 debug messages>

22.30.9. Rerunning OPT passes. (Maybe there is more to do..)

22.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~67 debug messages>

22.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2678:
      Old ports: A={ $auto$wreduce.cc:461:run$3321 [4] $auto$wreduce.cc:461:run$3321 [4] $auto$wreduce.cc:461:run$3321 [0] 1'0 $auto$wreduce.cc:461:run$3321 [0] }, B={ $auto$wreduce.cc:461:run$3321 [4] 1'0 $auto$wreduce.cc:461:run$3321 [4] 1'1 $auto$wreduce.cc:461:run$3321 [0] }, Y=$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0] [4:0]
      New ports: A={ $auto$wreduce.cc:461:run$3321 [4] $auto$wreduce.cc:461:run$3321 [0] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$3321 [4] 1'1 }, Y=$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0] [3:1]
      New connections: { $flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0] [4] $flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0] [0] } = { $auto$wreduce.cc:461:run$3321 [4] $auto$wreduce.cc:461:run$3321 [0] }
  Optimizing cells in module \top.
Performed a total of 1 changes.

22.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3155 ($sdff) from module top.

22.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

22.30.16. Rerunning OPT passes. (Maybe there is more to do..)

22.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~68 debug messages>

22.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.20. Executing OPT_DFF pass (perform DFF optimizations).

22.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.30.23. Finished OPT passes. (There is nothing left to do.)

22.31. Executing TECHMAP pass (map to technology primitives).

22.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

22.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$bf541dd3c0ba8228982b61e7bfbc350a2c253f4c\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $ne.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$21b43a343f2bc4ba62df8a2c90631d371d8e7ce8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $tribuf.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux.
Using template $paramod$91e5b74f11633b3386c40b03efcf15406a306835\_80_ecp5_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$d16a138d50c5473e76a26446ec9bb0a651b19901\_80_ecp5_alu for cells of type $alu.
Using template $paramod$531b0e8664cf0177363f10a943e616839f246c95\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3945f32547a814e98e0af098256e32675d1d77b0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$19e9557905baa9d3741d0daa66e2ef076e9bab7d\_90_pmux for cells of type $pmux.
Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux.
Using template $paramod$2116a631f856d4d4902c2618dca73dafa3b8c9c0\_90_alu for cells of type $alu.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$f1fc4bc1d42e857fca43ce0fdd0da6ff25c612c4\_90_pmux for cells of type $pmux.
Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux.
Using template $paramod$1f20d8d82f527b368f9fd3d5ec59522d2ba6b9fc\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$e25898cce02b4d043ab08e065e45db8cf66c901c\_90_pmux for cells of type $pmux.
Using template $paramod$a285b5a57fe61eabc57c91b8c412748ee1151a85\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_xor.
Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $dlatch.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using template $paramod$e4e871699ef984d49b67460a907fd39b385c5c53\_90_demux for cells of type $demux.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
No more expansions possible.
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
<suppressed ~5299 debug messages>

22.32. Executing OPT pass (performing simple optimizations).

22.32.1. Executing OPT_EXPR pass (perform const folding).
[75%] Tech-Mapping Phase 2 completed
Optimizing module top.
<suppressed ~11151 debug messages>

22.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~5436 debug messages>
Removed a total of 1812 cells.

22.32.3. Executing OPT_DFF pass (perform DFF optimizations).

22.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 758 unused cells and 5196 unused wires.
<suppressed ~759 debug messages>

22.32.5. Finished fast OPT passes.

22.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

22.35. Executing TECHMAP pass (map to technology primitives).

22.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

22.35.2. Continuing TECHMAP pass.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
No more expansions possible.

****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source run.tcl
# read_verilog "main.v"
<suppressed ~926 debug messages>

22.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~28 debug messages>

22.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

22.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

22.39. Executing ATTRMVCP pass (move or copy attributes).

22.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 4549 unused wires.
<suppressed ~1 debug messages>

22.41. Executing TECHMAP pass (map to technology primitives).

22.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

22.41.2. Continuing TECHMAP pass.

22.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$36247 ($mux).
Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$36246 ($logic_not).
<suppressed ~4 debug messages>

22.41.4. Executing OPT pass (performing simple optimizations).

22.41.4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.
<suppressed ~1 debug messages>

22.41.4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

22.41.4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.6. Executing OPT_DFF pass (perform DFF optimizations).

22.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

22.41.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

22.41.4.9. Rerunning OPT passes. (Maybe there is more to do..)

22.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

22.41.4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.13. Executing OPT_DFF pass (perform DFF optimizations).

22.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..

22.41.4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

22.41.4.16. Finished OPT passes. (There is nothing left to do.)
Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_.
No more expansions possible.
<suppressed ~4 debug messages>

22.42. Executing ABC9 pass.

22.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.3. Executing PROC pass (convert processes to netlists).

22.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36351'.
Cleaned up 1 empty switch.

22.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36352 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.3.4. Executing PROC_INIT pass (extract init attributes).

22.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36352'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36350_EN[3:0]$36358
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36350_DATA[3:0]$36357
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36350_ADDR[3:0]$36356
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36351'.

22.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36335_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36336_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36340_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36341_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36345_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36337_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36346_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36342_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36338_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36347_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36343_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36348_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36349_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36344_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36339_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36334_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36350_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36352'.
  created $dff cell `$procdff$36402' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36350_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36352'.
  created $dff cell `$procdff$36403' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36350_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36352'.
  created $dff cell `$procdff$36404' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36351'.
  created direct connection (no actual register cell created).

22.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36376'.
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36352'.
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36351'.
Cleaned up 1 empty switch.

22.42.3.12. Executing OPT_EXPR pass (perform const folding).

22.42.4. Executing PROC pass (convert processes to netlists).

22.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36422'.
Cleaned up 1 empty switch.

22.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36423 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.4.4. Executing PROC_INIT pass (extract init attributes).

22.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36423'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36421_EN[3:0]$36427
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36421_DATA[3:0]$36429
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36421_ADDR[3:0]$36428
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36422'.

22.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36408_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36413_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36418_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36410_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36419_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36406_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36415_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36411_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36420_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36416_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36409_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36414_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36417_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36412_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36407_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36405_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36421_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36423'.
  created $dff cell `$procdff$36473' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36421_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36423'.
  created $dff cell `$procdff$36474' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36421_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36423'.
  created $dff cell `$procdff$36475' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36422'.
  created direct connection (no actual register cell created).

22.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36447'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36423'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36422'.
Cleaned up 1 empty switch.

22.42.4.12. Executing OPT_EXPR pass (perform const folding).

22.42.5. Executing PROC pass (convert processes to netlists).

22.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36493'.
Cleaned up 1 empty switch.

22.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36494 in module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.5.4. Executing PROC_INIT pass (extract init attributes).

22.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
Creating decoders for process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36494'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36492_EN[3:0]$36500
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36492_DATA[3:0]$36499
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36492_ADDR[3:0]$36498
Creating decoders for process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36493'.

22.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.\i' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36482_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36487_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36483_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36479_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36488_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36484_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36489_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36476_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36486_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36478_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36491_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36477_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36481_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36490_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36485_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36480_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36492_ADDR' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36494'.
  created $dff cell `$procdff$36544' with positive edge clock.
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36492_DATA' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36494'.
  created $dff cell `$procdff$36545' with positive edge clock.
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36492_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36494'.
  created $dff cell `$procdff$36546' with positive edge clock.
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36493'.
  created direct connection (no actual register cell created).

22.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36518'.
Found and cleaned up 1 empty switch in `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36494'.
Removing empty process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36493'.
Cleaned up 1 empty switch.

22.42.5.12. Executing OPT_EXPR pass (perform const folding).

22.42.6. Executing PROC pass (convert processes to netlists).

22.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36564'.
Cleaned up 1 empty switch.

22.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36565 in module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.6.4. Executing PROC_INIT pass (extract init attributes).

22.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
Creating decoders for process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36565'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36563_EN[3:0]$36569
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36563_DATA[3:0]$36571
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36563_ADDR[3:0]$36570
Creating decoders for process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36564'.

22.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.\i' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36557_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36556_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36551_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36559_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36555_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36547_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36553_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36554_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36561_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36550_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36560_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36548_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36549_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36562_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36558_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36552_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36563_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36565'.
  created $dff cell `$procdff$36615' with positive edge clock.
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36563_ADDR' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36565'.
  created $dff cell `$procdff$36616' with positive edge clock.
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36563_DATA' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36565'.
  created $dff cell `$procdff$36617' with positive edge clock.
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.\muxwre' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36564'.
  created direct connection (no actual register cell created).

22.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36589'.
Found and cleaned up 1 empty switch in `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36565'.
Removing empty process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36564'.
Cleaned up 1 empty switch.

22.42.6.12. Executing OPT_EXPR pass (perform const folding).

22.42.7. Executing PROC pass (convert processes to netlists).

22.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36635'.
Cleaned up 1 empty switch.

22.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36636 in module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.7.4. Executing PROC_INIT pass (extract init attributes).

22.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
Creating decoders for process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36636'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36634_EN[3:0]$36640
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36634_DATA[3:0]$36641
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36634_ADDR[3:0]$36642
Creating decoders for process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36635'.

22.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.\i' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36633_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36626_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36621_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36631_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36620_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36630_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36629_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36625_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36623_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36618_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36619_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36624_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36627_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36632_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36628_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36622_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36634_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36636'.
  created $dff cell `$procdff$36686' with positive edge clock.
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36634_DATA' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36636'.
  created $dff cell `$procdff$36687' with positive edge clock.
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36634_ADDR' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36636'.
  created $dff cell `$procdff$36688' with positive edge clock.
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36635'.
  created direct connection (no actual register cell created).

22.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36660'.
Found and cleaned up 1 empty switch in `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36636'.
Removing empty process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36635'.
Cleaned up 1 empty switch.

22.42.7.12. Executing OPT_EXPR pass (perform const folding).

22.42.8. Executing PROC pass (convert processes to netlists).

22.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36706'.
Cleaned up 1 empty switch.

22.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36707 in module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.8.4. Executing PROC_INIT pass (extract init attributes).

22.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
Creating decoders for process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36707'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36705_EN[3:0]$36711
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36705_DATA[3:0]$36712
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36705_ADDR[3:0]$36713
Creating decoders for process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36706'.

22.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36689_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.\i' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36694_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36699_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36695_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36703_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36702_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36697_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36696_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36691_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36701_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36690_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36700_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36693_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36704_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36698_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36692_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36705_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36707'.
  created $dff cell `$procdff$36757' with positive edge clock.
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36705_DATA' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36707'.
  created $dff cell `$procdff$36758' with positive edge clock.
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36705_ADDR' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36707'.
  created $dff cell `$procdff$36759' with positive edge clock.
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.\muxwre' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36706'.
  created direct connection (no actual register cell created).

22.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36731'.
Found and cleaned up 1 empty switch in `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36707'.
Removing empty process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36706'.
Cleaned up 1 empty switch.

22.42.8.12. Executing OPT_EXPR pass (perform const folding).

22.42.9. Executing PROC pass (convert processes to netlists).

22.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36777'.
Cleaned up 1 empty switch.

22.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36778 in module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.9.4. Executing PROC_INIT pass (extract init attributes).

22.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
Creating decoders for process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36778'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36776_EN[3:0]$36784
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36776_DATA[3:0]$36783
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36776_ADDR[3:0]$36782
Creating decoders for process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36777'.

22.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36775_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36761_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36766_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36767_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36770_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36771_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.\i' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36763_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36764_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36765_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36769_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36773_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36772_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36774_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36768_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36762_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36760_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36776_ADDR' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36778'.
  created $dff cell `$procdff$36828' with positive edge clock.
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36776_DATA' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36778'.
  created $dff cell `$procdff$36829' with positive edge clock.
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36776_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36778'.
  created $dff cell `$procdff$36830' with positive edge clock.
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.\muxwre' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36777'.
  created direct connection (no actual register cell created).

22.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36802'.
Found and cleaned up 1 empty switch in `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36778'.
Removing empty process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36777'.
Cleaned up 1 empty switch.

22.42.9.12. Executing OPT_EXPR pass (perform const folding).

22.42.10. Executing PROC pass (convert processes to netlists).

22.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36848'.
Cleaned up 1 empty switch.

22.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36849 in module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.10.4. Executing PROC_INIT pass (extract init attributes).

22.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
Creating decoders for process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36849'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36847_EN[3:0]$36855
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36847_DATA[3:0]$36854
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36847_ADDR[3:0]$36853
Creating decoders for process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36848'.

22.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36833_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36834_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36835_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.\i' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36836_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36831_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36845_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36841_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36840_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36839_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36846_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36837_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36842_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36843_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36844_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36838_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36832_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36847_ADDR' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36849'.
  created $dff cell `$procdff$36899' with positive edge clock.
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36847_DATA' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36849'.
  created $dff cell `$procdff$36900' with positive edge clock.
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36847_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36849'.
  created $dff cell `$procdff$36901' with positive edge clock.
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.\muxwre' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36848'.
  created direct connection (no actual register cell created).

22.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36873'.
Found and cleaned up 1 empty switch in `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36849'.
Removing empty process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36848'.
Cleaned up 1 empty switch.

22.42.10.12. Executing OPT_EXPR pass (perform const folding).

22.42.11. Executing PROC pass (convert processes to netlists).

22.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36919'.
Cleaned up 1 empty switch.

22.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36920 in module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.11.4. Executing PROC_INIT pass (extract init attributes).

22.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
Creating decoders for process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36920'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36918_EN[3:0]$36926
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36918_DATA[3:0]$36925
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36918_ADDR[3:0]$36924
Creating decoders for process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36919'.

22.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.\i' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36902_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36903_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36904_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36905_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36909_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36910_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36911_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36915_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36916_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36906_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36917_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36907_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36912_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36913_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36914_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36908_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36918_ADDR' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36920'.
  created $dff cell `$procdff$36970' with positive edge clock.
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36918_DATA' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36920'.
  created $dff cell `$procdff$36971' with positive edge clock.
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36918_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36920'.
  created $dff cell `$procdff$36972' with positive edge clock.
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.\muxwre' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36919'.
  created direct connection (no actual register cell created).

22.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36944'.
Found and cleaned up 1 empty switch in `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36920'.
Removing empty process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36919'.
Cleaned up 1 empty switch.

22.42.11.12. Executing OPT_EXPR pass (perform const folding).

22.42.12. Executing PROC pass (convert processes to netlists).

22.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36990'.
Cleaned up 1 empty switch.

22.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36991 in module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.12.4. Executing PROC_INIT pass (extract init attributes).

22.42.12.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.12.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
Creating decoders for process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36991'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36989_EN[3:0]$36995
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36989_DATA[3:0]$36997
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36989_ADDR[3:0]$36996
Creating decoders for process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36990'.

22.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.\i' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36973_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36974_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36975_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36979_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36980_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36982_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36981_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36977_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36985_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36987_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36976_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36986_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36983_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36988_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36984_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36978_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36989_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36991'.
  created $dff cell `$procdff$37041' with positive edge clock.
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36989_ADDR' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36991'.
  created $dff cell `$procdff$37042' with positive edge clock.
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36989_DATA' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36991'.
  created $dff cell `$procdff$37043' with positive edge clock.
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36990'.
  created direct connection (no actual register cell created).

22.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37015'.
Found and cleaned up 1 empty switch in `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36991'.
Removing empty process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36990'.
Cleaned up 1 empty switch.

22.42.12.12. Executing OPT_EXPR pass (perform const folding).

22.42.13. Executing PROC pass (convert processes to netlists).

22.42.13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37061'.
Cleaned up 1 empty switch.

22.42.13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37062 in module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.13.4. Executing PROC_INIT pass (extract init attributes).

22.42.13.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.13.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.13.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
Creating decoders for process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37062'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37060_EN[3:0]$37067
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37060_DATA[3:0]$37066
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37060_ADDR[3:0]$37068
Creating decoders for process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37061'.

22.42.13.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.13.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.\i' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37044_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37045_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37049_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37050_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37051_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37055_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37056_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37046_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37057_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37047_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37052_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37053_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37058_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37059_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37054_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37048_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37060_DATA' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37062'.
  created $dff cell `$procdff$37112' with positive edge clock.
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37060_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37062'.
  created $dff cell `$procdff$37113' with positive edge clock.
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37060_ADDR' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37062'.
  created $dff cell `$procdff$37114' with positive edge clock.
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37061'.
  created direct connection (no actual register cell created).

22.42.13.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37086'.
Found and cleaned up 1 empty switch in `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37062'.
Removing empty process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37061'.
Cleaned up 1 empty switch.

22.42.13.12. Executing OPT_EXPR pass (perform const folding).

22.42.14. Executing PROC pass (convert processes to netlists).

22.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37132'.
Cleaned up 1 empty switch.

22.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37133 in module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.14.4. Executing PROC_INIT pass (extract init attributes).

22.42.14.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.14.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
Creating decoders for process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37133'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37131_EN[3:0]$37139
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37131_DATA[3:0]$37138
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37131_ADDR[3:0]$37137
Creating decoders for process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37132'.

22.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.\i' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37115_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37119_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37120_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37121_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37125_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37126_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37116_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37127_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37117_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37122_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37123_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37128_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37129_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37130_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37124_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37118_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37131_ADDR' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37133'.
  created $dff cell `$procdff$37183' with positive edge clock.
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37131_DATA' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37133'.
  created $dff cell `$procdff$37184' with positive edge clock.
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37131_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37133'.
  created $dff cell `$procdff$37185' with positive edge clock.
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37132'.
  created direct connection (no actual register cell created).

22.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37157'.
Found and cleaned up 1 empty switch in `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37133'.
Removing empty process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37132'.
Cleaned up 1 empty switch.

22.42.14.12. Executing OPT_EXPR pass (perform const folding).

22.42.15. Executing PROC pass (convert processes to netlists).

22.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37203'.
Cleaned up 1 empty switch.

22.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37204 in module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.15.4. Executing PROC_INIT pass (extract init attributes).

22.42.15.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.15.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
Creating decoders for process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37204'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37202_EN[3:0]$37210
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37202_DATA[3:0]$37209
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37202_ADDR[3:0]$37208
Creating decoders for process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37203'.

22.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.\i' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37189_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37190_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37191_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37195_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37196_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37197_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37201_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37187_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37192_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37193_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37198_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37199_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37200_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37194_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37188_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37186_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37202_ADDR' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37204'.
  created $dff cell `$procdff$37254' with positive edge clock.
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37202_DATA' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37204'.
  created $dff cell `$procdff$37255' with positive edge clock.
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37202_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37204'.
  created $dff cell `$procdff$37256' with positive edge clock.
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37203'.
  created direct connection (no actual register cell created).

22.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37228'.
Found and cleaned up 1 empty switch in `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37204'.
Removing empty process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37203'.
Cleaned up 1 empty switch.

22.42.15.12. Executing OPT_EXPR pass (perform const folding).

22.42.16. Executing PROC pass (convert processes to netlists).

22.42.16.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37274'.
Cleaned up 1 empty switch.

22.42.16.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37275 in module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.16.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.16.4. Executing PROC_INIT pass (extract init attributes).

22.42.16.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.16.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.16.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
Creating decoders for process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37275'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37273_EN[3:0]$37281
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37273_DATA[3:0]$37280
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37273_ADDR[3:0]$37279
Creating decoders for process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37274'.

22.42.16.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.16.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.\i' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37257_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37259_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37260_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37261_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37265_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37266_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37267_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37271_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37272_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37262_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37263_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37268_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37269_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37270_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37264_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37258_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37273_ADDR' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37275'.
  created $dff cell `$procdff$37325' with positive edge clock.
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37273_DATA' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37275'.
  created $dff cell `$procdff$37326' with positive edge clock.
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37273_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37275'.
  created $dff cell `$procdff$37327' with positive edge clock.
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37274'.
  created direct connection (no actual register cell created).

22.42.16.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.16.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37299'.
Found and cleaned up 1 empty switch in `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37275'.
Removing empty process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37274'.
Cleaned up 1 empty switch.

22.42.16.12. Executing OPT_EXPR pass (perform const folding).

22.42.17. Executing PROC pass (convert processes to netlists).

22.42.17.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37345'.
Cleaned up 1 empty switch.

22.42.17.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37346 in module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.17.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.17.4. Executing PROC_INIT pass (extract init attributes).

22.42.17.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.17.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.17.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
Creating decoders for process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37346'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37344_EN[3:0]$37352
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37344_DATA[3:0]$37351
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37344_ADDR[3:0]$37350
Creating decoders for process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37345'.

22.42.17.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.17.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.\i' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37328_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37329_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37330_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37331_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37335_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37336_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37337_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37341_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37342_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37332_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37343_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37333_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37338_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37339_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37340_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37334_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37344_ADDR' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37346'.
  created $dff cell `$procdff$37396' with positive edge clock.
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37344_DATA' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37346'.
  created $dff cell `$procdff$37397' with positive edge clock.
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37344_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37346'.
  created $dff cell `$procdff$37398' with positive edge clock.
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.\muxwre' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37345'.
  created direct connection (no actual register cell created).

22.42.17.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.17.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37370'.
Found and cleaned up 1 empty switch in `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37346'.
Removing empty process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37345'.
Cleaned up 1 empty switch.

22.42.17.12. Executing OPT_EXPR pass (perform const folding).

22.42.18. Executing PROC pass (convert processes to netlists).

22.42.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37416'.
Cleaned up 1 empty switch.

22.42.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37417 in module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.18.4. Executing PROC_INIT pass (extract init attributes).

22.42.18.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.18.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
Creating decoders for process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37417'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37415_EN[3:0]$37421
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37415_DATA[3:0]$37423
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37415_ADDR[3:0]$37422
Creating decoders for process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37416'.

22.42.18.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.18.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.\i' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37399_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37400_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37401_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37405_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37411_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37407_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37406_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37412_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37402_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37413_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37403_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37408_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37409_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37414_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37410_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37404_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37415_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37417'.
  created $dff cell `$procdff$37467' with positive edge clock.
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37415_ADDR' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37417'.
  created $dff cell `$procdff$37468' with positive edge clock.
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37415_DATA' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37417'.
  created $dff cell `$procdff$37469' with positive edge clock.
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37416'.
  created direct connection (no actual register cell created).

22.42.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37441'.
Found and cleaned up 1 empty switch in `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37417'.
Removing empty process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37416'.
Cleaned up 1 empty switch.

22.42.18.12. Executing OPT_EXPR pass (perform const folding).

22.42.19. Executing PROC pass (convert processes to netlists).

22.42.19.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37487'.
Cleaned up 1 empty switch.

22.42.19.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37488 in module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.19.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.19.4. Executing PROC_INIT pass (extract init attributes).

22.42.19.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.19.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.19.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
Creating decoders for process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37488'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37486_EN[3:0]$37493
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37486_DATA[3:0]$37492
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37486_ADDR[3:0]$37494
Creating decoders for process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37487'.

22.42.19.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.19.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.\i' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37472_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37470_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37471_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37475_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37476_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37482_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37481_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37477_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37483_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37473_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37478_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37479_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37484_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37485_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37480_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37474_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37486_DATA' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37488'.
  created $dff cell `$procdff$37538' with positive edge clock.
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37486_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37488'.
  created $dff cell `$procdff$37539' with positive edge clock.
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37486_ADDR' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37488'.
  created $dff cell `$procdff$37540' with positive edge clock.
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.\muxwre' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37487'.
  created direct connection (no actual register cell created).

22.42.19.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.19.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37512'.
Found and cleaned up 1 empty switch in `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37488'.
Removing empty process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37487'.
Cleaned up 1 empty switch.

22.42.19.12. Executing OPT_EXPR pass (perform const folding).

22.42.20. Executing PROC pass (convert processes to netlists).

22.42.20.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37558'.
Cleaned up 1 empty switch.

22.42.20.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37559 in module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.20.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.20.4. Executing PROC_INIT pass (extract init attributes).

22.42.20.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.20.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.20.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
Creating decoders for process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37559'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37557_EN[3:0]$37565
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37557_DATA[3:0]$37564
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37557_ADDR[3:0]$37563
Creating decoders for process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37558'.

22.42.20.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.20.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.\i' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37541_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37545_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37546_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37547_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37551_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37552_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37542_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37553_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37543_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37548_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37549_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37554_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37555_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37556_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37550_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37544_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37557_ADDR' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37559'.
  created $dff cell `$procdff$37609' with positive edge clock.
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37557_DATA' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37559'.
  created $dff cell `$procdff$37610' with positive edge clock.
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37557_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37559'.
  created $dff cell `$procdff$37611' with positive edge clock.
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.\muxwre' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37558'.
  created direct connection (no actual register cell created).

22.42.20.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.20.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37583'.
Found and cleaned up 1 empty switch in `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37559'.
Removing empty process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37558'.
Cleaned up 1 empty switch.

22.42.20.12. Executing OPT_EXPR pass (perform const folding).

22.42.21. Executing PROC pass (convert processes to netlists).

22.42.21.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37629'.
Cleaned up 1 empty switch.

22.42.21.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37630 in module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.21.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.21.4. Executing PROC_INIT pass (extract init attributes).

22.42.21.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.21.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.21.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
Creating decoders for process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37630'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37628_EN[3:0]$37636
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37628_DATA[3:0]$37635
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37628_ADDR[3:0]$37634
Creating decoders for process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37629'.

22.42.21.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.21.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.\i' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37619_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37624_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37625_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37615_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37616_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37617_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37621_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37622_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37623_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37627_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37613_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37618_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37626_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37620_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37614_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37612_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37628_ADDR' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37630'.
  created $dff cell `$procdff$37680' with positive edge clock.
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37628_DATA' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37630'.
  created $dff cell `$procdff$37681' with positive edge clock.
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37628_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37630'.
  created $dff cell `$procdff$37682' with positive edge clock.
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37629'.
  created direct connection (no actual register cell created).

22.42.21.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.21.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37654'.
Found and cleaned up 1 empty switch in `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37630'.
Removing empty process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37629'.
Cleaned up 1 empty switch.

22.42.21.12. Executing OPT_EXPR pass (perform const folding).

22.42.22. Executing PROC pass (convert processes to netlists).

22.42.22.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37700'.
Cleaned up 1 empty switch.

22.42.22.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37701 in module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.22.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.22.4. Executing PROC_INIT pass (extract init attributes).

22.42.22.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.22.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.22.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
Creating decoders for process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37701'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37699_EN[3:0]$37707
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37699_DATA[3:0]$37706
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37699_ADDR[3:0]$37705
Creating decoders for process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37700'.

22.42.22.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.22.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.\i' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37683_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37685_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37686_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37687_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37691_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37692_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37693_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37697_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37698_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37688_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37689_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37694_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37695_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37696_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37690_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37684_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37699_ADDR' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37701'.
  created $dff cell `$procdff$37751' with positive edge clock.
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37699_DATA' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37701'.
  created $dff cell `$procdff$37752' with positive edge clock.
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37699_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37701'.
  created $dff cell `$procdff$37753' with positive edge clock.
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.\muxwre' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37700'.
  created direct connection (no actual register cell created).

22.42.22.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.22.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37725'.
Found and cleaned up 1 empty switch in `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37701'.
Removing empty process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37700'.
Cleaned up 1 empty switch.

22.42.22.12. Executing OPT_EXPR pass (perform const folding).

22.42.23. Executing PROC pass (convert processes to netlists).

22.42.23.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37771'.
Cleaned up 1 empty switch.

22.42.23.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37772 in module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.23.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.23.4. Executing PROC_INIT pass (extract init attributes).

22.42.23.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.23.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.23.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
Creating decoders for process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37772'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37770_EN[3:0]$37778
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37770_DATA[3:0]$37777
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37770_ADDR[3:0]$37776
Creating decoders for process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37771'.

22.42.23.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.23.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.\i' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37754_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37755_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37756_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37757_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37761_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37762_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37763_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37767_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37768_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37758_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37769_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37759_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37764_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37765_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37766_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37760_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37770_ADDR' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37772'.
  created $dff cell `$procdff$37822' with positive edge clock.
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37770_DATA' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37772'.
  created $dff cell `$procdff$37823' with positive edge clock.
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37770_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37772'.
  created $dff cell `$procdff$37824' with positive edge clock.
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.\muxwre' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37771'.
  created direct connection (no actual register cell created).

22.42.23.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.23.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37796'.
Found and cleaned up 1 empty switch in `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37772'.
Removing empty process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37771'.
Cleaned up 1 empty switch.

22.42.23.12. Executing OPT_EXPR pass (perform const folding).

22.42.24. Executing PROC pass (convert processes to netlists).

22.42.24.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37842'.
Cleaned up 1 empty switch.

22.42.24.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37843 in module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.24.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.24.4. Executing PROC_INIT pass (extract init attributes).

22.42.24.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.24.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.24.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
Creating decoders for process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37843'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37841_EN[3:0]$37847
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37841_DATA[3:0]$37849
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37841_ADDR[3:0]$37848
Creating decoders for process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37842'.

22.42.24.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.24.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.\i' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37831_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37833_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37825_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37826_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37827_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37832_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37837_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37838_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37828_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37839_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37829_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37834_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37835_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37840_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37836_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37830_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37841_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37843'.
  created $dff cell `$procdff$37893' with positive edge clock.
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37841_ADDR' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37843'.
  created $dff cell `$procdff$37894' with positive edge clock.
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37841_DATA' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37843'.
  created $dff cell `$procdff$37895' with positive edge clock.
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.\muxwre' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37842'.
  created direct connection (no actual register cell created).

22.42.24.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.24.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37867'.
Found and cleaned up 1 empty switch in `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37843'.
Removing empty process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37842'.
Cleaned up 1 empty switch.

22.42.24.12. Executing OPT_EXPR pass (perform const folding).

22.42.25. Executing PROC pass (convert processes to netlists).

22.42.25.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37913'.
Cleaned up 1 empty switch.

22.42.25.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37914 in module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.25.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.25.4. Executing PROC_INIT pass (extract init attributes).

22.42.25.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.25.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.25.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
Creating decoders for process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37914'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37912_EN[3:0]$37918
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37912_DATA[3:0]$37919
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37912_ADDR[3:0]$37920
Creating decoders for process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37913'.

22.42.25.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.25.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.\i' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37903_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37907_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37908_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37909_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37896_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37897_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37901_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37902_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37898_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37899_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37904_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37905_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37910_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37911_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37906_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37900_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37912_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37914'.
  created $dff cell `$procdff$37964' with positive edge clock.
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37912_DATA' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37914'.
  created $dff cell `$procdff$37965' with positive edge clock.
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37912_ADDR' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37914'.
  created $dff cell `$procdff$37966' with positive edge clock.
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.\muxwre' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37913'.
  created direct connection (no actual register cell created).

22.42.25.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.25.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37938'.
Found and cleaned up 1 empty switch in `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37914'.
Removing empty process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37913'.
Cleaned up 1 empty switch.

22.42.25.12. Executing OPT_EXPR pass (perform const folding).

22.42.26. Executing PROC pass (convert processes to netlists).

22.42.26.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37984'.
Cleaned up 1 empty switch.

22.42.26.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37985 in module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.26.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.26.4. Executing PROC_INIT pass (extract init attributes).

22.42.26.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.26.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.26.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
Creating decoders for process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37985'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37983_EN[3:0]$37991
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37983_DATA[3:0]$37990
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37983_ADDR[3:0]$37989
Creating decoders for process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37984'.

22.42.26.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.26.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.\i' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37978_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37982_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37976_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37970_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37967_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37971_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37977_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37972_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37973_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37968_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37979_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37969_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37974_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37975_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37980_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37981_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37983_ADDR' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37985'.
  created $dff cell `$procdff$38035' with positive edge clock.
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37983_DATA' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37985'.
  created $dff cell `$procdff$38036' with positive edge clock.
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37983_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37985'.
  created $dff cell `$procdff$38037' with positive edge clock.
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37984'.
  created direct connection (no actual register cell created).

22.42.26.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.26.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38009'.
Found and cleaned up 1 empty switch in `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37985'.
Removing empty process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37984'.
Cleaned up 1 empty switch.

22.42.26.12. Executing OPT_EXPR pass (perform const folding).

22.42.27. Executing PROC pass (convert processes to netlists).

22.42.27.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38055'.
Cleaned up 1 empty switch.

22.42.27.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38056 in module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.27.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.27.4. Executing PROC_INIT pass (extract init attributes).

22.42.27.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.27.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.27.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
Creating decoders for process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38056'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38054_EN[3:0]$38062
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38054_DATA[3:0]$38061
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38054_ADDR[3:0]$38060
Creating decoders for process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38055'.

22.42.27.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.27.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.\i' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38041_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38043_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38047_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38048_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38053_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38044_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38052_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38046_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38040_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38038_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38042_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38049_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38039_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38045_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38050_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38051_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38054_ADDR' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38056'.
  created $dff cell `$procdff$38106' with positive edge clock.
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38054_DATA' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38056'.
  created $dff cell `$procdff$38107' with positive edge clock.
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38054_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38056'.
  created $dff cell `$procdff$38108' with positive edge clock.
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.\muxwre' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38055'.
  created direct connection (no actual register cell created).

22.42.27.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.27.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38080'.
Found and cleaned up 1 empty switch in `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38056'.
Removing empty process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38055'.
Cleaned up 1 empty switch.

22.42.27.12. Executing OPT_EXPR pass (perform const folding).

22.42.28. Executing PROC pass (convert processes to netlists).

22.42.28.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38126'.
Cleaned up 1 empty switch.

22.42.28.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38127 in module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.28.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.28.4. Executing PROC_INIT pass (extract init attributes).

22.42.28.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.28.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.28.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
Creating decoders for process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38127'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38125_EN[3:0]$38133
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38125_DATA[3:0]$38132
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38125_ADDR[3:0]$38131
Creating decoders for process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38126'.

22.42.28.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.28.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.\i' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38111_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38113_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38118_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38123_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38122_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38116_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38110_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38109_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38112_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38117_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38119_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38124_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38114_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38115_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38120_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38121_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38125_ADDR' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38127'.
  created $dff cell `$procdff$38177' with positive edge clock.
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38125_DATA' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38127'.
  created $dff cell `$procdff$38178' with positive edge clock.
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38125_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38127'.
  created $dff cell `$procdff$38179' with positive edge clock.
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.\muxwre' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38126'.
  created direct connection (no actual register cell created).

22.42.28.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.28.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38151'.
Found and cleaned up 1 empty switch in `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38127'.
Removing empty process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38126'.
Cleaned up 1 empty switch.

22.42.28.12. Executing OPT_EXPR pass (perform const folding).

22.42.29. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$15403.$auto$simplemap.cc:267:simplemap_mux$36249
Found an SCC: $techmap$auto$ff.cc:266:slice$15402.$auto$simplemap.cc:267:simplemap_mux$36249
Found an SCC: $techmap$auto$ff.cc:266:slice$15401.$auto$simplemap.cc:267:simplemap_mux$36249
Found an SCC: $techmap$auto$ff.cc:266:slice$15400.$auto$simplemap.cc:267:simplemap_mux$36249
Found an SCC: $auto$ff.cc:266:slice$11966 $auto$ff.cc:266:slice$11965 $auto$simplemap.cc:126:simplemap_reduce$12174 $auto$simplemap.cc:126:simplemap_reduce$12159 $auto$opt_expr.cc:613:replace_const_cells$35316 $auto$ff.cc:266:slice$11964 $auto$simplemap.cc:126:simplemap_reduce$18848 $auto$simplemap.cc:126:simplemap_reduce$18845 $auto$simplemap.cc:75:simplemap_bitop$18831 $auto$simplemap.cc:267:simplemap_mux$12146 $auto$simplemap.cc:225:simplemap_logbin$12149 $auto$simplemap.cc:196:simplemap_lognot$12164 $auto$simplemap.cc:126:simplemap_reduce$12162 $auto$simplemap.cc:126:simplemap_reduce$12160 $auto$opt_expr.cc:613:replace_const_cells$34672 $auto$simplemap.cc:267:simplemap_mux$18829 $auto$simplemap.cc:126:simplemap_reduce$18843 $auto$simplemap.cc:126:simplemap_reduce$18840 $auto$simplemap.cc:75:simplemap_bitop$18833 $auto$simplemap.cc:196:simplemap_lognot$12179 $auto$simplemap.cc:126:simplemap_reduce$12177 $auto$simplemap.cc:126:simplemap_reduce$12175 $auto$opt_expr.cc:613:replace_const_cells$34660 $auto$ff.cc:266:slice$11967 $auto$simplemap.cc:126:simplemap_reduce$10977 $auto$simplemap.cc:126:simplemap_reduce$10975 $auto$simplemap.cc:225:simplemap_logbin$12105 $auto$simplemap.cc:196:simplemap_lognot$12115 $auto$simplemap.cc:126:simplemap_reduce$12113 $auto$opt_expr.cc:613:replace_const_cells$34670 $auto$simplemap.cc:267:simplemap_mux$18830
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$34794 $auto$ff.cc:266:slice$11804 $auto$simplemap.cc:126:simplemap_reduce$11942 $auto$simplemap.cc:126:simplemap_reduce$11915 $auto$ff.cc:266:slice$11805 $auto$simplemap.cc:126:simplemap_reduce$11947 $auto$simplemap.cc:126:simplemap_reduce$11943 $auto$simplemap.cc:38:simplemap_not$18851 $auto$ff.cc:266:slice$11806 $auto$simplemap.cc:38:simplemap_not$18855 $auto$ff.cc:266:slice$11810 $auto$simplemap.cc:126:simplemap_reduce$11918 $auto$simplemap.cc:126:simplemap_reduce$11945 $auto$simplemap.cc:38:simplemap_not$18856 $auto$ff.cc:266:slice$11811 $auto$ff.cc:266:slice$11812 $auto$simplemap.cc:38:simplemap_not$18854 $auto$ff.cc:266:slice$11809 $auto$simplemap.cc:126:simplemap_reduce$11921 $auto$simplemap.cc:126:simplemap_reduce$11917 $auto$simplemap.cc:196:simplemap_lognot$11954 $auto$simplemap.cc:126:simplemap_reduce$11952 $auto$simplemap.cc:126:simplemap_reduce$11950 $auto$simplemap.cc:126:simplemap_reduce$11948 $auto$simplemap.cc:126:simplemap_reduce$11944 $auto$simplemap.cc:38:simplemap_not$18853 $auto$ff.cc:266:slice$11808 $auto$ff.cc:266:slice$11807 $auto$simplemap.cc:167:logic_reduce$10956 $auto$simplemap.cc:225:simplemap_logbin$11899 $auto$simplemap.cc:225:simplemap_logbin$11900 $auto$simplemap.cc:196:simplemap_lognot$11927 $auto$simplemap.cc:126:simplemap_reduce$11925 $auto$simplemap.cc:126:simplemap_reduce$11923 $auto$simplemap.cc:126:simplemap_reduce$11920 $auto$simplemap.cc:126:simplemap_reduce$11916 $auto$simplemap.cc:38:simplemap_not$18852
Found an SCC: $auto$simplemap.cc:38:simplemap_not$18742 $auto$ff.cc:266:slice$14200 $auto$ff.cc:479:convert_ce_over_srst$35436 $auto$ff.cc:266:slice$14201 $auto$ff.cc:479:convert_ce_over_srst$35438 $auto$simplemap.cc:126:simplemap_reduce$6416 $auto$ff.cc:266:slice$14199 $auto$ff.cc:479:convert_ce_over_srst$35434 $auto$ff.cc:266:slice$14198 $auto$ff.cc:479:convert_ce_over_srst$35432 $auto$simplemap.cc:38:simplemap_not$18739 $auto$alumacc.cc:485:replace_alu$3451.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$3451.slice[0].ccu2c_i $auto$ff.cc:266:slice$14197 $auto$ff.cc:479:convert_ce_over_srst$35430 $auto$simplemap.cc:126:simplemap_reduce$11004 $auto$simplemap.cc:126:simplemap_reduce$11034 $auto$simplemap.cc:38:simplemap_not$6375 $auto$simplemap.cc:75:simplemap_bitop$6376 $auto$simplemap.cc:38:simplemap_not$6372 $auto$alumacc.cc:485:replace_alu$3451.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6417 $auto$simplemap.cc:38:simplemap_not$32901 $auto$ff.cc:266:slice$14202 $auto$ff.cc:479:convert_ce_over_srst$35440 $auto$simplemap.cc:126:simplemap_reduce$11017 $auto$simplemap.cc:126:simplemap_reduce$11015 $auto$simplemap.cc:126:simplemap_reduce$11036 $auto$simplemap.cc:126:simplemap_reduce$11033 $auto$simplemap.cc:126:simplemap_reduce$6421 $auto$simplemap.cc:126:simplemap_reduce$6419 $auto$simplemap.cc:126:simplemap_reduce$6415 $auto$simplemap.cc:38:simplemap_not$18740
Found an SCC: $auto$simplemap.cc:38:simplemap_not$18756 $auto$ff.cc:266:slice$11974 $auto$simplemap.cc:126:simplemap_reduce$12197 $auto$opt_expr.cc:613:replace_const_cells$34658 $auto$ff.cc:266:slice$11975 $auto$ff.cc:266:slice$11976 $auto$ff.cc:266:slice$11970 $auto$simplemap.cc:38:simplemap_not$18754 $auto$ff.cc:266:slice$11972 $auto$simplemap.cc:126:simplemap_reduce$12200 $auto$simplemap.cc:126:simplemap_reduce$12196 $auto$ff.cc:266:slice$11973 $auto$simplemap.cc:38:simplemap_not$18750 $auto$ff.cc:266:slice$11968 $auto$simplemap.cc:126:simplemap_reduce$12195 $auto$simplemap.cc:38:simplemap_not$18753 $auto$ff.cc:266:slice$11971 $auto$simplemap.cc:196:simplemap_lognot$12206 $auto$simplemap.cc:126:simplemap_reduce$12204 $auto$simplemap.cc:126:simplemap_reduce$12202 $auto$simplemap.cc:126:simplemap_reduce$12199 $auto$simplemap.cc:126:simplemap_reduce$12194 $auto$ff.cc:266:slice$11969 $auto$simplemap.cc:126:simplemap_reduce$11190
Found 8 SCCs in module top.
Found 8 SCCs.

22.42.30. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.31. Executing PROC pass (convert processes to netlists).

22.42.31.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

22.42.31.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

22.42.31.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

22.42.31.4. Executing PROC_INIT pass (extract init attributes).

22.42.31.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.31.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

22.42.31.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

22.42.31.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.31.9. Executing PROC_DFF pass (convert process syncs to FFs).

22.42.31.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.31.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

22.42.31.12. Executing OPT_EXPR pass (perform const folding).

22.42.32. Executing TECHMAP pass (map to technology primitives).

22.42.32.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.42.32.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~212 debug messages>

22.42.33. Executing OPT pass (performing simple optimizations).

22.42.33.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Optimizing module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Optimizing module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Optimizing module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Optimizing module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Optimizing module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Optimizing module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Optimizing module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
Optimizing module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Optimizing module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Optimizing module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Optimizing module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Optimizing module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Optimizing module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Optimizing module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Optimizing module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Optimizing module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Optimizing module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Optimizing module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Optimizing module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Optimizing module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Optimizing module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Optimizing module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Optimizing module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.

22.42.33.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

22.42.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Performed a total of 0 changes.

22.42.33.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

22.42.33.6. Executing OPT_DFF pass (perform DFF optimizations).

22.42.33.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4..

22.42.33.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Optimizing module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Optimizing module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Optimizing module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Optimizing module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Optimizing module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Optimizing module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Optimizing module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Optimizing module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Optimizing module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Optimizing module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Optimizing module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Optimizing module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Optimizing module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Optimizing module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Optimizing module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Optimizing module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Optimizing module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Optimizing module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Optimizing module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Optimizing module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Optimizing module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.

22.42.33.9. Finished OPT passes. (There is nothing left to do.)

22.42.34. Executing TECHMAP pass (map to technology primitives).

22.42.34.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

22.42.34.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4 for cells of type $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Using template $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4 for cells of type $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Using template $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4 for cells of type $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Using template $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4 for cells of type $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Using template $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4 for cells of type $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Using template $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4 for cells of type $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Using template $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4 for cells of type $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Using template $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4 for cells of type $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Using template $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4 for cells of type $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Using template $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4 for cells of type $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Using template $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4 for cells of type $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Using template $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4 for cells of type $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Using template $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4 for cells of type $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Using template $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4 for cells of type $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Using template $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4 for cells of type $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Using template $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4 for cells of type $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
Using template $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4 for cells of type $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Using template $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4 for cells of type $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Using template $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4 for cells of type $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Using template $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4 for cells of type $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Using template $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4 for cells of type $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Using template $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4 for cells of type $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Using template $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4 for cells of type $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Using template $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4 for cells of type $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1104 debug messages>

22.42.35. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

22.42.36. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

22.42.37. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.38. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

22.42.39. Executing TECHMAP pass (map to technology primitives).

22.42.39.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.42.39.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~251 debug messages>

22.42.40. Executing OPT pass (performing simple optimizations).

22.42.40.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

22.42.40.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

22.42.40.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.40.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.42.40.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.42.40.6. Executing OPT_DFF pass (perform DFF optimizations).

22.42.40.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

22.42.40.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.42.40.9. Rerunning OPT passes. (Maybe there is more to do..)

22.42.40.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.40.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.42.40.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.42.40.13. Executing OPT_DFF pass (perform DFF optimizations).

22.42.40.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.42.40.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.42.40.16. Finished OPT passes. (There is nothing left to do.)

22.42.41. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

22.42.42. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 7857 cells with 49080 new cells, skipped 5536 cells.
  replaced 3 cell types:
    1973 $_OR_
      96 $_XOR_
    5788 $_MUX_
  not replaced 59 cell types:
      30 $scopeinfo
     434 $_NOT_
    1727 $_AND_
       6 $_TBUF_
     800 TRELLIS_FF
       1 $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4
       1 $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4
       1 $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4
       1 $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4
     386 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4_$abc9_byp
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4
    1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
       1 $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4
       1 $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER
       1 $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4
       1 $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4
       1 $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4
       1 $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4
       1 $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4
       1 $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4
       1 $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4
       1 $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4
       1 $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4
       1 $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4
       1 $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4
       1 $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4
       1 $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4
       1 $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4
       1 $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4
       1 $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4
       1 $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4
       1 $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4
       1 $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4
       1 $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4_$abc9_byp
    1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4_$abc9_byp

22.42.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.42.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 21352 AND gates and 62548 wires from module `top' to a netlist network with 5121 inputs and 902 outputs.

22.42.42.4. Executing ABC9_EXE pass (technology mapping using ABC9).

22.42.42.5. Executing ABC9.
read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1274.699 ; gain = 10.930 ; free physical = 8549 ; free virtual = 29468
# read_verilog ../../debug/reset.v
# read_verilog ../../src/core/alu_control.v
# read_verilog ../../src/core/alu.v
# read_verilog ../../src/core/control_unit.v
# read_verilog ../../src/core/core.v
# read_verilog ../../src/core/immediate_generator.v
# read_verilog ../../src/core/mux.v
# read_verilog ../../src/core/pc.v
# read_verilog ../../src/core/registers.v
# read_verilog ../../src/core/csr_unit.v
# read_verilog ../../src/peripheral/bus.v
# read_verilog ../../src/peripheral/gpio.v
# read_verilog ../../src/peripheral/gpios.v
# read_verilog ../../src/peripheral/leds.v
# read_verilog ../../src/peripheral/memory.v
# read_verilog ../../src/peripheral/soc.v
# read_verilog ../../src/peripheral/uart_rx.v
# read_verilog ../../src/peripheral/uart_tx.v
# read_verilog ../../src/peripheral/uart.v
# read_verilog ../../src/peripheral/fifo.v
# read_xdc "digilent_nexys4_ddr.xdc"
# set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc]
# synth_design -top "top" -part "xc7a100tcsg324-1"
Command: synth_design -top top -part xc7a100tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 2744201
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5121/    902  and =   19763  lev =   52 (8.92)  mem = 0.59 MB  box = 1462  bb = 1076
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5121/    902  and =   25253  lev =   64 (5.35)  mem = 0.64 MB  ch = 2397  box = 1385  bb = 1076
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   60. Obj =  140. Set =  636. CutMin = no
ABC: Node =   25253.  Ch =  1725.  Total mem =    7.13 MB. Peak cut mem =    0.31 MB.
ABC: P:  Del = 7315.00.  Ar =   25323.0.  Edge =    28571.  Cut =   381046.  T =     0.10 sec
ABC: P:  Del = 7115.00.  Ar =   26910.0.  Edge =    29727.  Cut =   368670.  T =     0.10 sec
ABC: P:  Del = 7115.00.  Ar =   14390.0.  Edge =    24820.  Cut =   838935.  T =     0.21 sec
ABC: F:  Del = 7115.00.  Ar =    8441.0.  Edge =    21865.  Cut =   603531.  T =     0.16 sec
ABC: A:  Del = 7115.00.  Ar =    7684.0.  Edge =    20356.  Cut =   594246.  T =     0.26 sec
ABC: A:  Del = 7115.00.  Ar =    7567.0.  Edge =    20309.  Cut =   584598.  T =     0.25 sec
ABC: Total time =     1.08 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   5121/    902  and =   17148  lev =   40 (6.10)  mem = 0.54 MB  box = 1385  bb = 1076
ABC: Mapping (K=7)  :  lut =   4971  edge =   20219  lev =   14 (2.26)  levB =   42  mem = 0.27 MB
ABC: LUT = 4971 : 2=407 8.2 %  3=548 11.0 %  4=2794 56.2 %  5=929 18.7 %  6=111 2.2 %  7=182 3.7 %  Ave = 4.07
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 12.15 seconds, total: 12.15 seconds

22.42.42.6. Executing AIGER frontend.
<suppressed ~12135 debug messages>
Removed 22998 unused cells and 50315 unused wires.

22.42.42.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     4996
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      309
ABC RESULTS:   $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells:       24
ABC RESULTS:   $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1028
ABC RESULTS:   $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:           input signals:     1122
ABC RESULTS:          output signals:      136
Removing temp directory.

22.42.43. Executing TECHMAP pass (map to technology primitives).

22.42.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

22.42.43.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4 for cells of type $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Using template $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4 for cells of type $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Using template $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4 for cells of type $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Using template $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4 for cells of type $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Using template $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4 for cells of type $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Using template $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4 for cells of type $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Using template $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4 for cells of type $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Using template $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4 for cells of type $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Using template $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4 for cells of type $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Using template $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4 for cells of type $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Using template $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4 for cells of type $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Using template $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4 for cells of type $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Using template $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4 for cells of type $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Using template $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4 for cells of type $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Using template $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4 for cells of type $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Using template $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4 for cells of type $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Using template $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4 for cells of type $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
Using template $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4 for cells of type $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Using template $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4 for cells of type $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Using template $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4 for cells of type $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Using template $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4 for cells of type $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Using template $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4 for cells of type $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Using template $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4 for cells of type $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Using template $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4 for cells of type $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001000 for cells of type $__ABC9_SCC_BREAKER.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~2531 debug messages>
Removed 354 unused cells and 78785 unused wires.

22.43. Executing TECHMAP pass (map to technology primitives).

22.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

22.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$5bbc8d49c3fc31cf6661312d1516e2aaafe308a4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$2b8bc13233a581d3b3c6e6358acbd72bfc7b8b25\$lut for cells of type $lut.
Using template $paramod$b5c4ce1dfc3eb2407221852d859ebd8874869917\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$d06b369955969277cfa733ec12143dd8f89059cc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$f22dcb31891f0793d47958bb4a85a2603a9dfb1d\$lut for cells of type $lut.
Using template $paramod$00132373d2a5a8c35979cfb3023827eda2437a4d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$f20ce4917fd5b3c1bb5c623666c4e99ee36747d1\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$0f891ee84fac320f890afcf9c994c53a24cd31f9\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$16773ebb5e5d8dbce266b8a86bb4af4574d61ffd\$lut for cells of type $lut.
Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut.
Using template $paramod$0331e023d83b8009e60defb446ce9fa640b122c7\$lut for cells of type $lut.
Using template $paramod$83c1b6108170249166239e09804c5f4542556524\$lut for cells of type $lut.
Using template $paramod$32dee08328e8b29c9284c987432b771d306144c4\$lut for cells of type $lut.
Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut.
Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$b18a3edb490ff3a49fefc94182a05f36efbdbba2\$lut for cells of type $lut.
Using template $paramod$73168779d124d0e86f3f4da4f351086f6646bb40\$lut for cells of type $lut.
Using template $paramod$a191129d10a368b82781b98ff31865427345b51c\$lut for cells of type $lut.
Using template $paramod$877859204cc06b766f4cb38f89dea559af1e3734\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$05402c79be82cc63a2eaed19f98c2af9df54d241\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$4f6ef5838c139220e91b3d9534b74e9d61193cac\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$c9bbc504f0e0ccecc970ac10de814ea95d57ad51\$lut for cells of type $lut.
Using template $paramod$774a669204184147b38453b69c15da44a7cf748f\$lut for cells of type $lut.
Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut.
Using template $paramod$5c6d01824df27a97c3776b3694e8814e23c197cd\$lut for cells of type $lut.
Using template $paramod$71443dd9ce6d822783b911babf9e9dab228ad54a\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$861ac3ff29cc7d3d19e4b05ab3720afefb3e1bcb\$lut for cells of type $lut.
Using template $paramod$244d83ba2e7e81b167beb2b38995cd1740a1a017\$lut for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$1078665aa144cf7ff525a892db61e5cee078ce7c\$lut for cells of type $lut.
Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut.
Using template $paramod$e0de051551c157dae99fdcf91f38aa683ac43f13\$lut for cells of type $lut.
Using template $paramod$f22fbbe64634fad58d18ebc04b9b5bbccb1572c3\$lut for cells of type $lut.
Using template $paramod$811a39cc5365627b9ae26581054f3a4477281b93\$lut for cells of type $lut.
Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut.
Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut.
Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$6c51c1ba6c39f0c09b896d52432b366f116bd3c1\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$dc10581988ca640d0fb32ac47d12e56acfff793a\$lut for cells of type $lut.
Using template $paramod$ec4a21f896d8babdcea50998bb320a7741366e32\$lut for cells of type $lut.
Using template $paramod$8e1c82b304528085a78e4651c993ce9e1ef6b8a8\$lut for cells of type $lut.
Using template $paramod$8833253c105c1f3ff9a03a20302d6d0a2f4d9c5b\$lut for cells of type $lut.
Using template $paramod$117f0b2844161c8640d2bceb32ecb48229c7e92c\$lut for cells of type $lut.
Using template $paramod$49de9c6586d4afac9224520d21dca4266902474f\$lut for cells of type $lut.
Using template $paramod$2af133e21e62add83841f505920df583fd30936a\$lut for cells of type $lut.
Using template $paramod$7bdf4de455d69deb36afbbb09a259ada9973fb80\$lut for cells of type $lut.
Using template $paramod$240af9a1e3518839ea26843689dc51c451570852\$lut for cells of type $lut.
Using template $paramod$54f4aecb63963765ce18e3d670f7691ce16a22d5\$lut for cells of type $lut.
Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut.
Using template $paramod$2b47d6f0645f6c0eac4d0fed1097d370ff2ad02d\$lut for cells of type $lut.
Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut.
Using template $paramod$00da6ee835349555028231ae835c9b401a5c1dee\$lut for cells of type $lut.
Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$fdb7d2f78b1b1d86177579c82e917e4e8af6f77d\$lut for cells of type $lut.
Using template $paramod$7f1ac77c5d84ef62fa0ac317f9798af74d02a33d\$lut for cells of type $lut.
Using template $paramod$9e1755e3954600257bb9b9ab192e2c0243b0f35a\$lut for cells of type $lut.
Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$ee3ba3939f6ccdb74bf420a252d58cdb86511937\$lut for cells of type $lut.
Using template $paramod$14b3c5dcb0a224e08a070cce0e39de7b89ca2cf2\$lut for cells of type $lut.
Using template $paramod$c1b720ec874edd6fc39cce7310f3ee92d6e9d55e\$lut for cells of type $lut.
Using template $paramod$7a9287490ee0437f855a6093b620a7d106f771c3\$lut for cells of type $lut.
Using template $paramod$1221ecddf806ed98cf6cee2f2b5a80f38aeb4bee\$lut for cells of type $lut.
Using template $paramod$0b03320f3a1be2d98e6ed64b6a735e3177e9f6ab\$lut for cells of type $lut.
Using template $paramod$e58c69dce15c857d46f85efd346e67ebe4b9b02d\$lut for cells of type $lut.
Using template $paramod$fbee2e2a9861170f1cb68c75c8a3378effe59a9f\$lut for cells of type $lut.
Using template $paramod$d3d2b6a5ec102f3c610e97414cb3f20b0198988a\$lut for cells of type $lut.
Using template $paramod$b066d686934015d300d6a9122c972b59aea5921a\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$38400b76de2b00d7d5f8f09de118b82fd1b8be0a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut.
Using template $paramod$396fac99f0d3b6e6412076008a2622cbd8a2b71d\$lut for cells of type $lut.
Using template $paramod$af6bfc66edfa832be553173935a94fd15de7c168\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
Using template $paramod$489c9c73c2147b125c3fb354aeed1b94c93a65e8\$lut for cells of type $lut.
Using template $paramod$65bcb9b1ea0077bdc2e07ea1b7f347657f04171e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$ce15874c299a587dd16825ec2d2d2759b547554e\$lut for cells of type $lut.
Using template $paramod$75e719958ad1fc7c4b69ae772b613950795c3202\$lut for cells of type $lut.
Using template $paramod$2096e0f45e8a23f1611337525706192d6571e3bb\$lut for cells of type $lut.
Using template $paramod$cad8f5c808e91f937dcf797b89e646787b39867a\$lut for cells of type $lut.
Using template $paramod$5636998c7ce0b77a9e79012d4ef0c6d0a5a30e63\$lut for cells of type $lut.
Using template $paramod$bce98cbc4c7663d9534fcdf870483176065e0cfd\$lut for cells of type $lut.
Using template $paramod$03d0edf20ed1469b09ef5ea8e93986bf65c1867c\$lut for cells of type $lut.
Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$bca625691d7bbb6ae445e78d938b57fea486f242\$lut for cells of type $lut.
Using template $paramod$edb78bf6097bd1610bf429917d83de43c0242af1\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$169b0c252e5d2102076afbd91695fb8665a7b96e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
Using template $paramod$833582361e14b3ee2e66ad676022ab35d7aa7e28\$lut for cells of type $lut.
Using template $paramod$4dd4a9d54065b1696fc5e1c7ca18ff772310a315\$lut for cells of type $lut.
Using template $paramod$3430340b7b5842cb53598832e70c2030710c7529\$lut for cells of type $lut.
Using template $paramod$cc2a095eb455a4b3d2a771dcc8d049b19888952d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$bb31794edaeae40ebc8f25d406841d47c86ca072\$lut for cells of type $lut.
Using template $paramod$143e879a28fb21b6cc6d9d203db157624cb85d42\$lut for cells of type $lut.
Using template $paramod$9851cb11f88bbbf4a516c0595f3b0113b1f100c4\$lut for cells of type $lut.
Using template $paramod$1bf3509a544426de1daa8b6919ee1df60c7165ec\$lut for cells of type $lut.
Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037\$lut for cells of type $lut.
Using template $paramod$50c04e0d9d4d18fa1d48fde34511146cb9a57d39\$lut for cells of type $lut.
Using template $paramod$dd95acdea9c10e4d143ea0b05f5efd28d4461683\$lut for cells of type $lut.
Using template $paramod$b97dea647725901eed851280e5a3889ea3e50a3d\$lut for cells of type $lut.
Using template $paramod$6ca37c73b3119caca79a9c7c9bebf350eb4cc53c\$lut for cells of type $lut.
Using template $paramod$64c6c9e67a7feaf6c5c06265262acdb92ebad435\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011011 for cells of type $lut.
Using template $paramod$e4420625b391a0195a79d04f47b1caeead25e0b7\$lut for cells of type $lut.
Using template $paramod$c078756a5eee24746ec1cfb3824decc1ad0554b7\$lut for cells of type $lut.
Using template $paramod$a8b7516c4ccadf4ab65906113028f2819d14ea8b\$lut for cells of type $lut.
Using template $paramod$2f9a3db5232806b69e711d55bfd2a32512ed386e\$lut for cells of type $lut.
Using template $paramod$70f68cc10fbeada9b6fa90c3bb75475e348ca467\$lut for cells of type $lut.
Using template $paramod$a0aea495a7ec615204e185eb69340453c5633d1c\$lut for cells of type $lut.
Using template $paramod$d72b39aae547bf5473b4f5b33fc824040e0dc79c\$lut for cells of type $lut.
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut.
Using template $paramod$2fd3c42461376c704c07117e7368b2ed8179d1e0\$lut for cells of type $lut.
Using template $paramod$f520e14adfd7009a3da8e79e5c0cb74f90a918a1\$lut for cells of type $lut.
Using template $paramod$538b4ae25dc35aacd84b6990112000e5c658b51e\$lut for cells of type $lut.
Using template $paramod$788488865e8371d9a6bd254c976f73735a26824a\$lut for cells of type $lut.
Using template $paramod$b9b1dc0798e71069345a0685abb619f244ffaf14\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$d119410bab96963da0139669592048db2c09198b\$lut for cells of type $lut.
Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut.
Using template $paramod$1892d7a5a024228b11384475c0a06e07a94dcbb0\$lut for cells of type $lut.
Using template $paramod$b089060a61c5d29ddce66d73edb5ee493ec9de27\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut.
Using template $paramod$d39daf56a31b2e8ce06533aad96ed54894dfed59\$lut for cells of type $lut.
Using template $paramod$f9b715fbf1040e81e900b2461c2390d17ed5e988\$lut for cells of type $lut.
Using template $paramod$c1a909080ec76944fa258a19c3ca35c98563249f\$lut for cells of type $lut.
Using template $paramod$5bb4589aef4e67d4113ef14e01c5bb618a3e9139\$lut for cells of type $lut.
Using template $paramod$7c04463cc8d71ebeef84edd3cf051b6567f35f56\$lut for cells of type $lut.
Using template $paramod$e30837f3251cf5ee621b32eb98c906d24c84d91b\$lut for cells of type $lut.
Using template $paramod$88e557ff47f35512152dcd123e39a7dd2f3f82eb\$lut for cells of type $lut.
Using template $paramod$1406ef821901e69cdcc3bf52adc46d008cb82bb3\$lut for cells of type $lut.
Using template $paramod$2de8b2d0f6086e896d2b4145ba0913d9a18e16c8\$lut for cells of type $lut.
Using template $paramod$be95f3a2132281eadd1adcfe6229e43dbc3353c9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$cda390f4499f6e82413288e5fb16ee215978b6a5\$lut for cells of type $lut.
Using template $paramod$525425bfbe66d72ee88210d059d9a74f55ab8de8\$lut for cells of type $lut.
Using template $paramod$36721a88b9e65f8022498ef362296bed9a015337\$lut for cells of type $lut.
Using template $paramod$0af662e2f4838a57f45fc753edf2aa9f014fd124\$lut for cells of type $lut.
Using template $paramod$f9707a95fec0f0a61bfca4069af293624ad5af8d\$lut for cells of type $lut.
Using template $paramod$b8113752b08bd47f69a1c8c2bca1cfb157e800c9\$lut for cells of type $lut.
Using template $paramod$8f05b5f219ff034210d64bde08b0588cea0cb4fb\$lut for cells of type $lut.
Using template $paramod$07b1b12ce0305f55108770e958fd02caedfebdf8\$lut for cells of type $lut.
Using template $paramod$94e65f323749ab2f501acf5577af42456678fff9\$lut for cells of type $lut.
Using template $paramod$c38e1cd7940079658d63c78af084855b51b0a038\$lut for cells of type $lut.
Using template $paramod$998f0dd6d45c2b142a3e8905e916fbe6f599103e\$lut for cells of type $lut.
Using template $paramod$deb68ff2e8fd9ff8da03271d1a71173f689317cc\$lut for cells of type $lut.
Using template $paramod$51c4f8826f2e3956c2b9748e49d9b3cde37e475b\$lut for cells of type $lut.
Using template $paramod$4e9e23686d07a1fd91232ab07371e48a0e62a680\$lut for cells of type $lut.
Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut.
Using template $paramod$6ce2282a1c18d45df8d10664c7f353e468051fc4\$lut for cells of type $lut.
Using template $paramod$77b566652a2449bae604a937e67f0c9bd49bb4a7\$lut for cells of type $lut.
Using template $paramod$0c6dfa64f0b85c553a8953a6297c80f5dabecee4\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$d9e9a5f45b5e7a0e12caed755a01c3deef1c6e30\$lut for cells of type $lut.
Using template $paramod$5552b23a89809fed2b1588e8f91bb3893be2e6ce\$lut for cells of type $lut.
Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100110 for cells of type $lut.
Using template $paramod$aa569d89e9c8462354297a37f09bc519483c7133\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$655e7cdf1fce9923e771969f28446489197085e2\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$4637f78518a334255f9075a6f84bda1541a68aea\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$8d8d339c8977d202fee0f775efb849f965fcd468\$lut for cells of type $lut.
Using template $paramod$8ce3bb5281756031c29296f5408ac54526962f46\$lut for cells of type $lut.
Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut.
Using template $paramod$cedecb2dc344b1f4b6ec843a10088804c9fd9ffb\$lut for cells of type $lut.
Using template $paramod$d7856980c8e3df62f97c26ab34037f33a9e831b5\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$7f4670b933e9d0d313fe2dbe752fa82b1cf04d5c\$lut for cells of type $lut.
Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut.
Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut.
Using template $paramod$17fd36fab32bce162e5828682c2ba9fa7f9e273b\$lut for cells of type $lut.
Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e\$lut for cells of type $lut.
Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut.
Using template $paramod$68e1ef427c0ad0553e0e29800a596a6ae20aafdd\$lut for cells of type $lut.
Using template $paramod$218a3fe8c4166eaf50e73c4c04f9241cfc6f8f0e\$lut for cells of type $lut.
Using template $paramod$ea5280fce2698f0f291737e66fca69a1d9d058e1\$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut.
Using template $paramod$8b2d4da05a775f7705e7bcda27120d70b71d57db\$lut for cells of type $lut.
Using template $paramod$cffcdcfefee28cb7804202d59fcab831562282d3\$lut for cells of type $lut.
Using template $paramod$fd16523b66efc91890bfb23f6b1dcc83fa36d799\$lut for cells of type $lut.
Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut.
Using template $paramod$a27a31d814e3f8a1f076ac2d8bf60dd683109b16\$lut for cells of type $lut.
Using template $paramod$dae799e1fb7e48933e3e893f69e2fb8479219fd3\$lut for cells of type $lut.
Using template $paramod$4c0221505c29b55a66f4801128a7e9ab143964dc\$lut for cells of type $lut.
Using template $paramod$dd7c1583fe0ade167c7826c594e5d16b758a72fe\$lut for cells of type $lut.
Using template $paramod$d7c87e01028a8e76f94ba02b569a998b96e0a4a6\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$06acae0916e0847f0d4eddb6b590aec1ff6793d4\$lut for cells of type $lut.
Using template $paramod$63dfb5d507c3c0842cdb02014ffa50dbe5770b84\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod$8160052a731214203a3c5d85bb06f463e2e42187\$lut for cells of type $lut.
Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut.
Using template $paramod$8c511ecc39a73b7025cd36ecb3562498546aa7b3\$lut for cells of type $lut.
Using template $paramod$66bd7f404946a58f5e24d2699f556d4f34f04751\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod$c5e9409d868ac22b0d04fa66386bddf5c7c8858c\$lut for cells of type $lut.
Using template $paramod$398fcc1ecc97ca013ba65e3043889b8d700ceed0\$lut for cells of type $lut.
Using template $paramod$fb4ed309581bcd972f41afa8566ae8b9812c7f6c\$lut for cells of type $lut.
Using template $paramod$7eded28cf8cfe7a69014ba3ea568d667a5cb22d7\$lut for cells of type $lut.
Using template $paramod$ee700feb78d1f78a2275689013e0e783764ce7f3\$lut for cells of type $lut.
Using template $paramod$3f44941fc257f07863a23ce4464b5e4a473f3bb9\$lut for cells of type $lut.
Using template $paramod$221832ea6a41a3208cd6f3411a952b5811695f4c\$lut for cells of type $lut.
Using template $paramod$340bcf4f6509548dfdde6975ae539c92fc34792e\$lut for cells of type $lut.
Using template $paramod$0c8ca179830091c5e617fa87fec5eda52bbb802e\$lut for cells of type $lut.
Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut.
Using template $paramod$a2dd6f6d19909c1cb6464545f92856f797b2eb6a\$lut for cells of type $lut.
Using template $paramod$4bca1171aa1d05f7c91ec90c5872503990abebf3\$lut for cells of type $lut.
Using template $paramod$db0052e63506de7ad7fc8dcb58daadd8306f8d61\$lut for cells of type $lut.
Using template $paramod$47625e0d44d1185ccf6831eac035c8dd510efc5d\$lut for cells of type $lut.
Using template $paramod$8d64e576629e8d7c655e0c65958ea61e649cd93e\$lut for cells of type $lut.
Using template $paramod$b2153d8b4466d4a8f8649eafb88b32b9356a5968\$lut for cells of type $lut.
Using template $paramod$181e421b20ec7479164200eba514412f2f0279b5\$lut for cells of type $lut.
Using template $paramod$dc327062330ee79aecc5e2013660e3b5909921a1\$lut for cells of type $lut.
Using template $paramod$e1b5328949db147f340050f9739d344fc4f96215\$lut for cells of type $lut.
Using template $paramod$56c6fc98268f6966dd23dcb4af9b8f5298fa7ead\$lut for cells of type $lut.
Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut.
Using template $paramod$5be893296f99040a0c12a33fd8da07e2ba154a8a\$lut for cells of type $lut.
Using template $paramod$1b65934cc8069c7ec2b24b7e4127c823526615a1\$lut for cells of type $lut.
Using template $paramod$021fb2e8f7dd5aa1411ecfd3194d3937ed3bda9a\$lut for cells of type $lut.
Using template $paramod$acf008c194939dd533849530b1ab63c5c671b3d9\$lut for cells of type $lut.
Using template $paramod$695194503e1cce2a2c8d445594b4ad04da5e30b2\$lut for cells of type $lut.
Using template $paramod$886dca44cc44258465bb1de98ffe3cfee3cf6fe1\$lut for cells of type $lut.
Using template $paramod$9ae1405012c6b8d1193c8e0de268cb4b4e6e6829\$lut for cells of type $lut.
Using template $paramod$127d42c61791e2b6b8fd39133e126a67cbdb52bc\$lut for cells of type $lut.
Using template $paramod$fa325ba675c7860955a5e859771d65ebbba8cf28\$lut for cells of type $lut.
Using template $paramod$e8491fd794fc64e2b24d49525057b0b581d6aa03\$lut for cells of type $lut.
Using template $paramod$70ad22f9774513853615b7c5644bb9c3751e9f22\$lut for cells of type $lut.
Using template $paramod$df7e2609aa0ceb901b2015c43813cbbbdc1ff523\$lut for cells of type $lut.
Using template $paramod$9ae9e1f4da271cd4a323725803cc4c97e675ac36\$lut for cells of type $lut.
Using template $paramod$926eb7116de35e54f3bcf1601eb30848ef3d1049\$lut for cells of type $lut.
Using template $paramod$e38ea057065bc5329e397965a5aa51aade0aa21c\$lut for cells of type $lut.
Using template $paramod$f6a93e38958d5ac7952ef868422d86003dfcf62a\$lut for cells of type $lut.
Using template $paramod$68ac76aa2d27311266ae23d3016ed43d87015cde\$lut for cells of type $lut.
Using template $paramod$9754422de62e5f46b1224496b225c68aeb5874c2\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$0f16c62b8738e878436adfa3ab0e37ac74a0bc78\$lut for cells of type $lut.
Using template $paramod$d49280c3811eb269f1f902fb42b8a7d4eb74053f\$lut for cells of type $lut.
Using template $paramod$cc1a182f4298f403113e0d1e53767892703a980d\$lut for cells of type $lut.
Using template $paramod$4e3532f7916fee9e336ca3f21d0e994fa0943029\$lut for cells of type $lut.
Using template $paramod$73e41ba12bc174f688c4f10930e766aa158e80c4\$lut for cells of type $lut.
Using template $paramod$6069048ea7c45159713a0558424cdfb243a46dfe\$lut for cells of type $lut.
Using template $paramod$9becc6376cac3c55b34ebe436ca01b702d34d09e\$lut for cells of type $lut.
Using template $paramod$1430936d0a2fc19c4ebdd46ac8d26538a056a586\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$1d976bc954653b91c2dfa54d38dd9f92125922d7\$lut for cells of type $lut.
Using template $paramod$4db8e9f6768cc0f49eeabffd6db44f73af7ae008\$lut for cells of type $lut.
Using template $paramod$b2da4bcc6f0901db9afe29d02a8d3b70a560eae9\$lut for cells of type $lut.
Using template $paramod$dee640d16cce4eaffba139b741b984b4549f5ab6\$lut for cells of type $lut.
Using template $paramod$de157981d1ff0357ce91bae7484e1779e32fbafd\$lut for cells of type $lut.
Using template $paramod$8abb1a86348e9abacf6764ffafa33551d56623a6\$lut for cells of type $lut.
Using template $paramod$577acc3326fe1c16a2e650feed4598c9a3dd90e1\$lut for cells of type $lut.
Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut.
Using template $paramod$3c65b836b459497040ee21f130921801f05ef88b\$lut for cells of type $lut.
Using template $paramod$abdf863b488afc87659224c59e1124d22de72e7f\$lut for cells of type $lut.
Using template $paramod$2d2413a280e7b1addc7d01c2294edd09baa111cc\$lut for cells of type $lut.
Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67\$lut for cells of type $lut.
Using template $paramod$3ec5e45cb3e54de9dbe908707155b5f9917c9370\$lut for cells of type $lut.
Using template $paramod$ba4d4981c26643597e1c97e7f97940d34548a0eb\$lut for cells of type $lut.
Using template $paramod$de81bb4f24bddd9c01fb4a8d2c0db4e04ac2517e\$lut for cells of type $lut.
Using template $paramod$a60ff4c4762b9e3ac8586c0b4d313b5c731d1a2b\$lut for cells of type $lut.
Using template $paramod$75f4c6be45ca9adfac0da0e26fb10d166eed1312\$lut for cells of type $lut.
Using template $paramod$325bb4a8737975ab1a0980ac4dd3572231166eca\$lut for cells of type $lut.
Using template $paramod$3e14605ffdc6e1eed6147205c511e169125adea2\$lut for cells of type $lut.
Using template $paramod$47edd7b92975ce2a04ca54f405999abb73db2517\$lut for cells of type $lut.
Using template $paramod$8ceee21f996e743e737b7b749bf5b574a87fc38b\$lut for cells of type $lut.
Using template $paramod$f4ea155453aa14da0cad27929657427ad6fff43b\$lut for cells of type $lut.
Using template $paramod$e2d4399e1e149b2bd3c04b32fc0d847bb8cdd6d6\$lut for cells of type $lut.
Using template $paramod$ea09127a1b9c235edcadc5fc83c1f3153644ea43\$lut for cells of type $lut.
Using template $paramod$e66ddd071de3be1d112de63078d882cb12c0fbe3\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut.
Using template $paramod$55c459d0e02f18e159efd3c29a7808240c668886\$lut for cells of type $lut.
Using template $paramod$7e6ff6767275bfce613ba19d09b0f1d294f5dd16\$lut for cells of type $lut.
Using template $paramod$6b62468353a716e43972563d3074fa328b3ddcae\$lut for cells of type $lut.
Using template $paramod$b0cead1f76b95bf15933fb262b7a0b5c2f45d8d0\$lut for cells of type $lut.
Using template $paramod$fbd55d1b12935a22902cde46a0a7b6e309d6aa42\$lut for cells of type $lut.
Using template $paramod$c35ad3063d5038410210ddc72c1fd5fed46413b4\$lut for cells of type $lut.
Using template $paramod$f0b0cc300f60612a94b780d08f06dad711699364\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$8f363e35ec27116eb4ae4858a9e3379b4a295b98\$lut for cells of type $lut.
Using template $paramod$dd55606b5a4d51db4783efcd08c87f45964ade90\$lut for cells of type $lut.
Using template $paramod$aedd449f92e25b9b066b6eb8fb1f27f76b713182\$lut for cells of type $lut.
Using template $paramod$3a49482aafd00875f74e1a4436ca7c91eb0b637e\$lut for cells of type $lut.
Using template $paramod$5f3728701179f8bcb3202ed867ae0d71d4132336\$lut for cells of type $lut.
Using template $paramod$2e91260c662bedefee0c75d5d1389234e222db20\$lut for cells of type $lut.
Using template $paramod$5002424fb13e71fe3d63c5ae16358968d083bd9b\$lut for cells of type $lut.
Using template $paramod$c554b816101be4e9401218de04230036e0b14c79\$lut for cells of type $lut.
Using template $paramod$e6cfc2a250ad5b0b3da266fa46a057a6eca6e3d9\$lut for cells of type $lut.
Using template $paramod$03fbb0272fff4f0e2c1a09ad70295e9b3c8ffacd\$lut for cells of type $lut.
Using template $paramod$90d11c1f5ac9d86ae1ffcc5a58e39cded43e89a2\$lut for cells of type $lut.
Using template $paramod$dbd7752cebfffda2f7237bd51529740e7d59568b\$lut for cells of type $lut.
Using template $paramod$0728e7dbe7b3a97b28b83e30b63b347f7d0c8c96\$lut for cells of type $lut.
Using template $paramod$661726f60f0023120c09769d3c2322121177a4db\$lut for cells of type $lut.
Using template $paramod$ea2b11aca30aa162d3b93de07d97b9c1565643dd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$06752539d97bcc789b3775d5dee917a879cc7d3c\$lut for cells of type $lut.
Using template $paramod$7d00223d389375d8aa2a99b32820e4e78b59ba7e\$lut for cells of type $lut.
Using template $paramod$6c93f72df707851f26fa552be4f379d6cd1367df\$lut for cells of type $lut.
Using template $paramod$31d0fe9872e147e32329f1888afc564130486200\$lut for cells of type $lut.
Using template $paramod$8759174d270d551afcd4f083de21241c3714d122\$lut for cells of type $lut.
Using template $paramod$90a3c2c7e264e9cb46d5878b7789ce94ab4a122f\$lut for cells of type $lut.
Using template $paramod$faa7c68f188e2cd8e40ef18e7d59e64072c34025\$lut for cells of type $lut.
Using template $paramod$312c8bab003b975d614e2bfaf49ff0fa7926f2d1\$lut for cells of type $lut.
Using template $paramod$fdf66ab4b4b9acc27eb403bb38c9427ff18140b7\$lut for cells of type $lut.
Using template $paramod$86ff48d42597cede45cce84e2021269a23fae88f\$lut for cells of type $lut.
Using template $paramod$70942fc9a52cad5fbe9daa818decfcb21f9e4bf5\$lut for cells of type $lut.
Using template $paramod$61bc070da6097f9d2a93b5193ed8efc9cbdfb4fd\$lut for cells of type $lut.
Using template $paramod$50cb5344ddd0289e0c0223ac511861d335d47d06\$lut for cells of type $lut.
Using template $paramod$c3ea945b0597b01d0748529960aadb7b649fe6c4\$lut for cells of type $lut.
Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut.
Using template $paramod$5c36a508e8885449eeca65fa0c02b7154f6a3130\$lut for cells of type $lut.
Using template $paramod$734cd1512f671d92bc4f41153da0d9781801dd98\$lut for cells of type $lut.
Using template $paramod$f77583acb34df9d57ac9134750234d5941ef8946\$lut for cells of type $lut.
Using template $paramod$a75fe1683a97958e61513f004cf91c3458c2f88e\$lut for cells of type $lut.
Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut.
Using template $paramod$dff8e7e8854dc948604d9ed7dea9d198697a573d\$lut for cells of type $lut.
Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut.
Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut.
Using template $paramod$7ed3d685a887e531dc8f4f21b9907d4766cf861f\$lut for cells of type $lut.
Using template $paramod$f096cbf7810c657d1faa5ebcdd247974deedeea6\$lut for cells of type $lut.
Using template $paramod$70a934594406e8042bf2854c778fef542ef3ea5f\$lut for cells of type $lut.
Using template $paramod$97108e3cc0d0482a6e72e932e86430aa2177750b\$lut for cells of type $lut.
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut.
Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut.
Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut.
Using template $paramod$d6e6d411b16e057eae3ca70523bb1b2722704525\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$52b969f858b3742d4a1c5e2e1f7de6301b827ff4\$lut for cells of type $lut.
Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\$lut for cells of type $lut.
Using template $paramod$f5651ff2abca4d07e0dfb50ad5504abd96162cd4\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$68cb09a5d00037369a2af39e1778bf17484c020a\$lut for cells of type $lut.
Using template $paramod$27b9fef8ac0ecc4ceedd1c98c3d8cc78581f9415\$lut for cells of type $lut.
Using template $paramod$55f7d9850b8564509bff49b617d7ca817e320dc2\$lut for cells of type $lut.
Using template $paramod$240e171f8bae87a2fe4bee672a3055fa35afe320\$lut for cells of type $lut.
Using template $paramod$023d9d13c9ddd8e6cbda8fa49753038bbbacbfa4\$lut for cells of type $lut.
Using template $paramod$a5627e8ad36aa9b4fe2f6188097d151d45fefa8a\$lut for cells of type $lut.
Using template $paramod$1b292dfca1a62bf07c745cb22add5dcc3dce70dd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$729e309efb767462e04d0f5bc6a998dfe103a51f\$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$34e326867bb04eb7166eb385de03f3f07fdc4c23\$lut for cells of type $lut.
Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut.
Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut.
Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut.
Using template $paramod$6e424bd4a747f8421ac946af3d9bb3a47fd0b233\$lut for cells of type $lut.
Using template $paramod$ea0425fbeea043c32ca78abcc4d9b9648cd9f561\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$92b64c0757c39dc9911628339cd5109b3dd1f81b\$lut for cells of type $lut.
Using template $paramod$758d9e8729b283bb3651b0fa835584bea2e26299\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod$71039eaa750b63c13b47d102108a4d1b67d00b7c\$lut for cells of type $lut.
Using template $paramod$f03663c7f91be924d1e9df8220b895406b3f6489\$lut for cells of type $lut.
Using template $paramod$77c2a0573790d304ab2299da6d598e8d2e184867\$lut for cells of type $lut.
Using template $paramod$a5788e8bd3559e65ba7c6a1d93529c6fb76569b9\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$c07d61aaf1d93e15249de987e8fd0ca391dbd52a\$lut for cells of type $lut.
Using template $paramod$723be7177967d6866729df0ff463a602326a012e\$lut for cells of type $lut.
Using template $paramod$98da953dac84989c1dec711ba4d909885d65c4dd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$0d26e42822227428593a6f2ed183ae9b22d4b575\$lut for cells of type $lut.
Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut.
Using template $paramod$23ba03b3f106a8b0f20f18bfebd862b419996ddc\$lut for cells of type $lut.
Using template $paramod$4d044680cabd725df9bca7abd5e2203ef8b7c7ad\$lut for cells of type $lut.
Using template $paramod$b517d5becacef506fa9b592b09d13f7c0a2754bf\$lut for cells of type $lut.
Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut.
Using template $paramod$21a1ca6f9f5c15b304c8c46ce6cda8b91e063cf1\$lut for cells of type $lut.
Using template $paramod$49f93da3bc72e2487024a93848b25121b5791efb\$lut for cells of type $lut.
Using template $paramod$f1f54b3287ec9a624d0cbb8e3997d469beb86f0f\$lut for cells of type $lut.
Using template $paramod$7b733f5b3466ec911060896fccc5c2626cbe3d64\$lut for cells of type $lut.
Using template $paramod$3258fabf91107b4a007ae89b2246a16c31e8ae28\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$20f3f4b8e32f8a8b038b0056872dc94926194798\$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut.
Using template $paramod$00621a3c55d483214eef3eec42a14cc6a616135c\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$a648edd7290dbdc60b4277769ac1653dae6fd74c\$lut for cells of type $lut.
Using template $paramod$2f86c26b2c8a0cb4751dc6260dcddfa2da537ab0\$lut for cells of type $lut.
Using template $paramod$b455ae670d9c8dfd9a8351323c3c8064adab0ca3\$lut for cells of type $lut.
Using template $paramod$c3cf68e260edf996a3d46517803fea413208c69c\$lut for cells of type $lut.
Using template $paramod$5afe21d6fdc7c33aeb338fdb508ea02813207bfd\$lut for cells of type $lut.
Using template $paramod$3db826965e677cc72a454d5e910d68e35d246aa3\$lut for cells of type $lut.
Using template $paramod$82ed25b11a6a11eb861f4dd3d46f5fc9aa1eebaf\$lut for cells of type $lut.
Using template $paramod$1e3f8a5d31c944af2c420a98182bc898ab495e11\$lut for cells of type $lut.
Using template $paramod$7e3de18263fb7d0a2e12a4401120994e66bde6a4\$lut for cells of type $lut.
Using template $paramod$6de442abe246ff8c0692702d40d84ce1c07479d9\$lut for cells of type $lut.
Using template $paramod$18b66a2dc66be2a0d172c3d50ba03932f5924e22\$lut for cells of type $lut.
Using template $paramod$f405ee362848dd1a47c58160f854302f6ecf95ff\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut.
Using template $paramod$c87d6a2b89408860e522c19ca93ed82dd0442806\$lut for cells of type $lut.
Using template $paramod$4e0dac06d9d9602cfb659e01e0850b77eec5b798\$lut for cells of type $lut.
Using template $paramod$6e3a03c79073e44642e8ed2dab4ee82dfd40dfba\$lut for cells of type $lut.
Using template $paramod$031639056602a9dab4a0894878194a35372df974\$lut for cells of type $lut.
Using template $paramod$8c11a155773d2e4aba9b1022fc059160b55313e8\$lut for cells of type $lut.
Using template $paramod$7a9b7d7d96d5349b2a3f800b325795fd17e50692\$lut for cells of type $lut.
Using template $paramod$31e70b8536aa87f106b94ec7880c9a9ca5f7de5a\$lut for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$2357431a20f3891da5d1d21801bc815b057e2dac\$lut for cells of type $lut.
Using template $paramod$f25cfc29453e54091ece2586f82661c6c404bcba\$lut for cells of type $lut.
Using template $paramod$c63efa97e6cbc8132d15a22fbd0c7fc96068748a\$lut for cells of type $lut.
Using template $paramod$c6a0421f5b5114b68e9782f0585d571421cf8f01\$lut for cells of type $lut.
Using template $paramod$cf6ab2c0433b8f9b498807313fee7b7dc115199f\$lut for cells of type $lut.
Using template $paramod$e0e16f0e69ba9e6596b61d072bd230c598f46f32\$lut for cells of type $lut.
Using template $paramod$34d1852620b6a307d4fe69ec05837032ca143340\$lut for cells of type $lut.
Using template $paramod$fe1fadedaeb6156c0ee01cb7fe4cd32590d54069\$lut for cells of type $lut.
Using template $paramod$62008a5879a2c50141fb0d35185280c06907bf19\$lut for cells of type $lut.
Using template $paramod$5f753fbbf1458cba7f10d10853aae5cf8474c285\$lut for cells of type $lut.
Using template $paramod$aff93b4bd7772abb618131a95c4808b2f1f5179b\$lut for cells of type $lut.
Using template $paramod$c08a774c89ef1ea6ee2ef4d8c3b071eb141d4259\$lut for cells of type $lut.
Using template $paramod$1e3430f21d933e902e2b8cb9ab970ea8ccfc0991\$lut for cells of type $lut.
Using template $paramod$121ffce29421a03e2a005f5cf06cf5fa5b5174dd\$lut for cells of type $lut.
Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut.
Using template $paramod$099af7f70fcc70b41da4ec1f8df6dd0abf473cb5\$lut for cells of type $lut.
Using template $paramod$baed78cac43b96075e0d80f8b23efad1fa3ca0e1\$lut for cells of type $lut.
Using template $paramod$8ae5e24171bca0b8d12d43741a6723f274290f92\$lut for cells of type $lut.
Using template $paramod$b0360900b3f16f29c1c5ca7794cc3eb8479f1e74\$lut for cells of type $lut.
Using template $paramod$088042dd8e0ad793439016442fdb50dbe54f6e4a\$lut for cells of type $lut.
Using template $paramod$b8f75cf9c6c06c079da053f4aa60c4d5363c32b3\$lut for cells of type $lut.
Using template $paramod$3c17557fcd213346f7b38856ecb30fe49bafcccd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod$2a0e9830506418f5e4c5f66917d75cc61f44d1a8\$lut for cells of type $lut.
Using template $paramod$71b6d833a4170eede1dcc8409c3fc7460c2df8d9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut.
Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26\$lut for cells of type $lut.
Using template $paramod$1780b599fad82e57d6459b81ca42390759dd97e1\$lut for cells of type $lut.
Using template $paramod$6eaa285474ca0c16a33be004e48a6a32f35674a1\$lut for cells of type $lut.
Using template $paramod$ffa22ac2286a369e680058c3c7d0f6c7696aa08c\$lut for cells of type $lut.
Using template $paramod$4d673f44384ebded9d542bceabb0e9271e6f9336\$lut for cells of type $lut.
Using template $paramod$95e069858cb2e42f0b23620675213cfe73b02fff\$lut for cells of type $lut.
Using template $paramod$7c047b89d420b3ed2898ef0d740ba255e557620d\$lut for cells of type $lut.
Using template $paramod$263b613d26e59958a0d1e36903a2016b82f2f359\$lut for cells of type $lut.
Using template $paramod$561d2773f8d56e396c30ee941900c9935428585f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$39fecdaa624309b39c1f847c4e14205177fabf73\$lut for cells of type $lut.
Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$5c0eb292ef891be47277bee5c25eaa71b34b43e2\$lut for cells of type $lut.
Using template $paramod$d0cfbfa794431f7e2ccafbbeaaefbd5ed7deeac7\$lut for cells of type $lut.
Using template $paramod$505ca6f83efadae0442899a08af73f5288142a52\$lut for cells of type $lut.
Using template $paramod$44236511622e197854fa4814b088d63bb24df320\$lut for cells of type $lut.
Using template $paramod$4541c098116f7292d10d7d30a0922be20fa68a41\$lut for cells of type $lut.
Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$b18f60dfd13c21d3e472b89652353f3f5342b450\$lut for cells of type $lut.
Using template $paramod$aa9cf2f501984f3d23676491f808fe20bb38f6a7\$lut for cells of type $lut.
Using template $paramod$c1747c0c7cb4f86c4813433b4d41103fb3fe105a\$lut for cells of type $lut.
Using template $paramod$d01b12b2e3fe73c32cc2ed54e644a6c6afdf052a\$lut for cells of type $lut.
Using template $paramod$0b2a5aca2d15f20cd3deb7ba6729ef4965b3324b\$lut for cells of type $lut.
Using template $paramod$4976b94884fb984911ddd3ea3f74eb965ec3ed53\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~12297 debug messages>

22.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138293.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138025.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138285.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138286.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138287.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138291.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138299.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26385.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$25622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$25588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$25588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$25270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$24178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$23166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$23166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$21931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$21681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$21681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$21681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$21681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$21681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$21681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$19637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$17263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16831.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$16480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$16469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16277.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15469.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15223.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$13801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$13308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$13080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$13080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$13080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$13049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$13049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$12975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12491.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$12151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$11615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11467.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$10974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$11545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$11169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$10426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$10426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$10426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$10488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$10488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$10488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$10488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$10396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$10369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$25968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$25964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$10555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$21681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$26976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$10369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$10369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$10378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$10383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$10396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$10396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$10406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$10412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$10417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$10426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$10430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$10443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$10488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$10533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$10488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$10864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$10886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$10890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$10961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$10970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$10978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$11157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$11258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$11258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$11272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$11281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11345.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11419.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$11435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$11463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11479.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$11497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$11514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$11577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11603.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11640.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11919.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12069.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12257.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$12967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$13263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138305.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$13379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138301.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$13432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$13544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$13843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$13987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14008.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14299.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14484.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14523.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14591.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14695.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14715.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$14876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$14882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$14949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$14957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15419.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$15779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$15797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$15804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$15905.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$16329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$auto$fsm_map.cc:170:map_fsm$3097[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$16379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16391.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$16443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$16469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$16480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$16484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$16488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$16535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$16566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16763.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$16770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16835.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$16850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$16989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$17025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$17211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$17257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$17282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$17286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17548.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$17698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$17973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$17977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$17983.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18083.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18271.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$18330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$18418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18485.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18681.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18771.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$18946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$18959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$18980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19083.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19317.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$19362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$19565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$19641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$19645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$19671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$19698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$19940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$19989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$20091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20117.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20668.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$20712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$20989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$21050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$18935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$21111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$21162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$21315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21325.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$21387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21512.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$21547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$21687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$21706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$21712.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$21742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$21942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$21975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$22010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$22119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$22187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22403.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$22465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$22503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$22582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$22589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22719.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$22726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22788.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$22856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$22895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$22985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$23020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23081.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$23088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$23149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$23186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23273.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$23504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$23582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$23589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$23650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$23658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$23807.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$23842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$23876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$24061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$24129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$24195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$24422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$24513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$24558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24721.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24750.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$24757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$24920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$24965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$24990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25083.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$25100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$25205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$25442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$25995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$26002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$26116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$26340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$26389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$26405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$26506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$26542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26571.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$26598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$26659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$26289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$19702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$20020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$20682.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$21076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$auto$rtlil.cc:2582:Mux$3609[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$auto$rtlil.cc:2582:Mux$3609[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$19030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$19333.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut\SOC.Core.CSR_Unit.csr_write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$22385.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$24178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137956$lut$aiger137955$25266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137956$lut$aiger137955$26644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138309.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138029.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138041.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138311.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$23166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138083.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138075.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138089.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138100.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138107.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137956$lut$aiger137955$12733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137956$lut$aiger137955$11842.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 15198 unused wires.

22.45. Executing AUTONAME pass.
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2028.328 ; gain = 403.715 ; free physical = 7401 ; free virtual = 28319
---------------------------------------------------------------------------------
INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:139]
WARNING: [Synth 8-11065] parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:17]
WARNING: [Synth 8-11065] parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:18]
WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:40]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:17]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:16]
INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
	Parameter CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:22]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:22]
INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
	Parameter CLOCK_FREQ bound to: 100000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter MEMORY_SIZE bound to: 2048 - type: integer 
	Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string 
	Parameter GPIO_WIDHT bound to: 8 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1]
	Parameter BOOT_ADDRESS bound to: 0 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:15]
INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:145]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:276]
INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1]
WARNING: [Synth 8-7071] port 'response' of module 'Control_Unit' is unconnected for instance 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:167]
WARNING: [Synth 8-7023] instance 'Control_Unit' of module 'Control_Unit' has 29 connections declared, but only 28 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:167]
INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:33]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:10]
INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:132]
INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
WARNING: [Synth 8-7071] port 'save_pc' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:223]
WARNING: [Synth 8-7071] port 'interrupt_on_hold' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:223]
WARNING: [Synth 8-7023] instance 'CSR_Unit' of module 'CSR_Unit' has 15 connections declared, but only 13 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:223]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1]
WARNING: [Synth 8-7071] port 'instruction_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
WARNING: [Synth 8-7071] port 'instruction_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
WARNING: [Synth 8-7071] port 'instruction_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
WARNING: [Synth 8-7071] port 'instruction_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 12 connections declared, but only 8 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
	Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string 
	Parameter MEMORY_SIZE bound to: 2048 - type: integer 
INFO: [Synth 8-3876] $readmem data file '../../software/memory/fpga_test_3.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:29]
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
	Parameter CLOCK_FREQ bound to: 100000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
	Parameter DEPTH bound to: 8 - type: integer 
	Parameter WIDTH bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 100000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 100000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
	Parameter WIDHT bound to: 8 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
WARNING: [Synth 8-3848] Net interrupt_on_hold in module/entity CSR_Unit does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:20]
WARNING: [Synth 8-6014] Unused sequential element buffer_full_reg was removed.  [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:49]
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed.  [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:43]
WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[2] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module UART is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2116.266 ; gain = 491.652 ; free physical = 7271 ; free virtual = 28191
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2134.078 ; gain = 509.465 ; free physical = 7270 ; free virtual = 28190
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2134.078 ; gain = 509.465 ; free physical = 7270 ; free virtual = 28190
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2134.078 ; gain = 0.000 ; free physical = 7267 ; free virtual = 28187
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Renamed 772600 objects in module top (432 iterations).
<suppressed ~20645 debug messages>

22.46. Executing HIERARCHY pass (managing design hierarchy).

22.46.1. Analyzing design hierarchy..
Top module:  \top

22.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

22.47. Printing statistics.

=== top ===

   Number of wires:               9713
   Number of wire bits:          25679
   Number of public wires:        9713
   Number of public wire bits:   25679
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              12290
     $_TBUF_                         6
     $scopeinfo                     30
     CCU2C                         309
     L6MUX21                       657
     LUT4                         7533
     PFUMX                        1879
     TRELLIS_DPR16X4              1076
     TRELLIS_FF                    800

22.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

22.49. Executing JSON backend.
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2284.828 ; gain = 0.000 ; free physical = 7225 ; free virtual = 28153
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2284.863 ; gain = 0.000 ; free physical = 7223 ; free virtual = 28153

Warnings: 21 unique messages, 22 total
End of script. Logfile hash: 97e2e8a8f3, CPU: user 14.89s system 0.16s, MEM: 307.29 MB peak
Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
Time spent: 44% 1x abc9_exe (12 sec), 12% 1x autoname (3 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:     14607/43848    33%
Info:         logic LUTs:   7533/43848    17%
Info:         carry LUTs:    618/43848     1%
Info:           RAM LUTs:   4304/ 5481    78%
Info:          RAMW LUTs:   2152/10962    19%

Info:      Total DFFs:       800/43848     1%

Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     323 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xc3c2923b

Info: Device utilisation:
Info: 	          TRELLIS_IO:    18/  245     7%
Info: 	                DCCA:     1/   56     1%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:   800/43848     1%
Info: 	        TRELLIS_COMB: 14695/43848    33%
Info: 	        TRELLIS_RAMW:  1076/ 5481    19%

Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 6578 cells, random placement wirelen = 610494.
Info:     at initial placer iter 0, wirelen = 2233
Info:     at initial placer iter 1, wirelen = 1981
Info:     at initial placer iter 2, wirelen = 1933
Info:     at initial placer iter 3, wirelen = 1901
Info: Running main analytical placer, max placement attempts per cell = 34403512.
Info:     at iteration #1, type ALL: wirelen solved = 1968, spread = 105700, legal = 106868; time = 0.51s
Info:     at iteration #2, type ALL: wirelen solved = 7118, spread = 80768, legal = 82108; time = 0.47s
Info:     at iteration #3, type ALL: wirelen solved = 13194, spread = 74058, legal = 75808; time = 0.51s
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 7157 ; free virtual = 28089
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 7157 ; free virtual = 28089
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 7157 ; free virtual = 28089
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
           RESET_COUNTER |                               00 |                               01
                    IDLE |                               01 |                               10
                    INIT |                               10 |                               00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                   FETCH | 0000000000000000000000000000000000000000000001 |                           000000
                  DECODE | 0000000000000000000000000000000000000000000010 |                           000001
                  MEMADR | 0000000000000000000000000000000000000000000100 |                           000010
       MEMREAD_UNALIGNED | 0000000000000000000000000000000000000000001000 |                           010110
        LOAD_FIRST_BLOCK | 0000000000000000000000000000000000000000010000 |                           010000
        SAVE_FIRST_BLOCK | 0000000000000000000000000000000000000000100000 |                           010001
       CALC_NEXT_ADDRESS | 0000000000000000000000000000000000000001000000 |                           010010
       READ_SECOND_BLOCK | 0000000000000000000000000000000000000010000000 |                           010011
       LOAD_SECOND_BLOCK | 0000000000000000000000000000000000000100000000 |                           010100
            MERGE_BLOCKS | 0000000000000000000000000000000000001000000000 |                           010101
           FILTER_ALU_WB | 0000000000000000000000000000000000010000000000 |                           010111
                 MEMREAD | 0000000000000000000000000000000000100000000000 |                           000011
                   MEMWB | 0000000000000000000000000000000001000000000000 |                           000100
      MEMWRITE_UNALIGNED | 0000000000000000000000000000000010000000000000 |                           011000
  GEN_FIRST_BLOCK_PART_1 | 0000000000000000000000000000000100000000000000 |                           011001
  GEN_FIRST_BLOCK_PART_2 | 0000000000000000000000000000001000000000000000 |                           011010
 GEN_SECOND_BLOCK_PART_1 | 0000000000000000000000000000010000000000000000 |                           011011
 GEN_SECOND_BLOCK_PART_2 | 0000000000000000000000000000100000000000000000 |                           011100
      MERGE_WRITE_BLOCKS | 0000000000000000000000000001000000000000000000 |                           011101
    SWAP_VALUE_DIRECTION | 0000000000000000000000000010000000000000000000 |                           011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 0000000000000000000000000100000000000000000000 |                           100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 0000000000000000000000001000000000000000000000 |                           100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 0000000000000000000000010000000000000000000000 |                           100100
             CLEAR_VALUE | 0000000000000000000000100000000000000000000000 |                           011111
     MERGE_WRITE_VALUE_1 | 0000000000000000000001000000000000000000000000 |                           100000
           WRITE_VALUE_1 | 0000000000000000000010000000000000000000000000 |                           100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 0000000000000000000100000000000000000000000000 |                           100101
READ_SECOND_BLOCK_TO_WRITE | 0000000000000000001000000000000000000000000000 |                           100110
LOAD_SECOND_BLOCK_TO_WRITE | 0000000000000000010000000000000000000000000000 |                           100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 0000000000000000100000000000000000000000000000 |                           101000
  SWAP_VALUE_DIRECTION_2 | 0000000000000001000000000000000000000000000000 |                           101001
      CLEAR_VALUE_PART_2 | 0000000000000010000000000000000000000000000000 |                           101010
    CLEAR_VALUE_PART_2_1 | 0000000000000100000000000000000000000000000000 |                           101011
     MERGE_WRITE_VALUE_2 | 0000000000001000000000000000000000000000000000 |                           101100
           WRITE_VALUE_2 | 0000000000010000000000000000000000000000000000 |                           101101
                MEMWRITE | 0000000000100000000000000000000000000000000000 |                           000101
                EXECUTER | 0000000001000000000000000000000000000000000000 |                           000110
                EXECUTEI | 0000000010000000000000000000000000000000000000 |                           001000
                     JAL | 0000000100000000000000000000000000000000000000 |                           001001
                     BEQ | 0000001000000000000000000000000000000000000000 |                           001010
                   AUIPC | 0000010000000000000000000000000000000000000000 |                           001100
                     LUI | 0000100000000000000000000000000000000000000000 |                           001101
                 JALR_PC | 0001000000000000000000000000000000000000000000 |                           001110
                    JALR | 0010000000000000000000000000000000000000000000 |                           001011
                   ALUWB | 0100000000000000000000000000000000000000000000 |                           000111
              EXECUTECSR | 1000000000000000000000000000000000000000000000 |                           001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_RECV |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_SEND |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 7150 ; free virtual = 28084
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input   32 Bit       Adders := 1     
	   3 Input   32 Bit       Adders := 1     
	   2 Input   11 Bit       Adders := 2     
	   2 Input    6 Bit       Adders := 4     
	   2 Input    5 Bit       Adders := 1     
	   2 Input    4 Bit       Adders := 2     
	   2 Input    3 Bit       Adders := 1     
	   2 Input    2 Bit       Adders := 1     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
+---XORs : 
	                2 Bit    Wide XORs := 1     
+---Registers : 
	               33 Bit    Registers := 1     
	               32 Bit    Registers := 47    
	               16 Bit    Registers := 2     
	               11 Bit    Registers := 2     
	                8 Bit    Registers := 8     
	                6 Bit    Registers := 1     
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 18    
+---RAMs : 
	              16K Bit	(512 X 32 bit)          RAMs := 1     
	               64 Bit	(8 X 8 bit)          RAMs := 2     
+---Muxes : 
	  46 Input   46 Bit        Muxes := 1     
	  11 Input   46 Bit        Muxes := 1     
	   2 Input   46 Bit        Muxes := 8     
	   3 Input   33 Bit        Muxes := 1     
	   2 Input   32 Bit        Muxes := 35    
	   8 Input   32 Bit        Muxes := 1     
	   4 Input   32 Bit        Muxes := 13    
	  16 Input   32 Bit        Muxes := 1     
	   6 Input   32 Bit        Muxes := 1     
	   2 Input    8 Bit        Muxes := 3     
	   5 Input    8 Bit        Muxes := 1     
	   3 Input    6 Bit        Muxes := 1     
	   2 Input    6 Bit        Muxes := 4     
	   2 Input    5 Bit        Muxes := 1     
	  46 Input    4 Bit        Muxes := 1     
	  10 Input    4 Bit        Muxes := 1     
	   8 Input    4 Bit        Muxes := 1     
	  23 Input    4 Bit        Muxes := 1     
	   2 Input    4 Bit        Muxes := 1     
	   5 Input    3 Bit        Muxes := 1     
	   2 Input    3 Bit        Muxes := 3     
	   4 Input    3 Bit        Muxes := 2     
	  46 Input    3 Bit        Muxes := 3     
	  10 Input    3 Bit        Muxes := 1     
	   3 Input    2 Bit        Muxes := 1     
	   2 Input    2 Bit        Muxes := 14    
	  46 Input    2 Bit        Muxes := 2     
	   4 Input    2 Bit        Muxes := 4     
	   3 Input    1 Bit        Muxes := 6     
	   2 Input    1 Bit        Muxes := 49    
	  46 Input    1 Bit        Muxes := 11    
	   4 Input    1 Bit        Muxes := 2     
	  13 Input    1 Bit        Muxes := 2     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Info:     at iteration #4, type ALL: wirelen solved = 17530, spread = 68351, legal = 69955; time = 0.60s
Info:     at iteration #5, type ALL: wirelen solved = 21848, spread = 65546, legal = 67062; time = 0.49s
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
Info:     at iteration #6, type ALL: wirelen solved = 25295, spread = 67040, legal = 68165; time = 0.43s
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template. 
Info:     at iteration #7, type ALL: wirelen solved = 29799, spread = 62035, legal = 63223; time = 0.45s
Info:     at iteration #8, type ALL: wirelen solved = 31090, spread = 65681, legal = 66599; time = 0.50s
Info:     at iteration #9, type ALL: wirelen solved = 33815, spread = 65153, legal = 66144; time = 0.52s
Info:     at iteration #10, type ALL: wirelen solved = 34809, spread = 64111, legal = 64973; time = 0.42s
Info:     at iteration #11, type ALL: wirelen solved = 36683, spread = 63381, legal = 64501; time = 0.42s
Info:     at iteration #12, type ALL: wirelen solved = 36611, spread = 64613, legal = 65711; time = 0.43s
Info: HeAP Placer Time: 9.81s
Info:   of which solving equations: 6.15s
Info:   of which spreading cells: 0.68s
Info:   of which strict legalisation: 0.19s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 15234, wirelen = 63223
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN  (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":221)
WARN  (NL0002) : The module "MUX" instantiated to "MemoryAddressMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":97)
WARN  (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":149)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
Info:   at iteration #5: temp = 0.000000, timing cost = 18164, wirelen = 51878
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6948 ; free virtual = 27891
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object                  | Inference | Size (Depth x Width) | Primitives      | 
+------------+-----------------------------+-----------+----------------------+-----------------+
|top         | SOC/Memory/memory_reg       | Implied   | 512 x 32             | RAM256X1S x 64  | 
|top         | SOC/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
|top         | SOC/Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
+------------+-----------------------------+-----------+----------------------+-----------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6945 ; free virtual = 27888
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6868 ; free virtual = 27812
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object                  | Inference | Size (Depth x Width) | Primitives      | 
+------------+-----------------------------+-----------+----------------------+-----------------+
|top         | SOC/Memory/memory_reg       | Implied   | 512 x 32             | RAM256X1S x 64  | 
|top         | SOC/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
|top         | SOC/Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
+------------+-----------------------------+-----------+----------------------+-----------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27806
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
Info:   at iteration #10: temp = 0.000000, timing cost = 16569, wirelen = 49303
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+----------+------+
|      |Cell      |Count |
+------+----------+------+
|1     |BUFG      |     2|
|2     |CARRY4    |    55|
|3     |LUT1      |    15|
|4     |LUT2      |   161|
|5     |LUT3      |   254|
|6     |LUT4      |   283|
|7     |LUT5      |   454|
|8     |LUT6      |  1494|
|9     |MUXF7     |   406|
|10    |MUXF8     |     2|
|11    |RAM256X1S |    64|
|12    |RAM32M    |     2|
|13    |RAM32X1D  |     4|
|14    |FDRE      |  1838|
|15    |FDSE      |     5|
|16    |LD        |     4|
|17    |IBUF      |     2|
|18    |OBUF      |     9|
|19    |OBUFT     |     8|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 44 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2284.863 ; gain = 509.465 ; free physical = 6862 ; free virtual = 27805
Synthesis Optimization Complete : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2284.863 ; gain = 0.000 ; free physical = 7135 ; free virtual = 28079
INFO: [Netlist 29-17] Analyzing 537 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2356.859 ; gain = 0.000 ; free physical = 7132 ; free virtual = 28075
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 74 instances were transformed.
  LD => LDCE: 4 instances
  RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances

Synth Design complete | Checksum: 1fbd9dc9
INFO: [Common 17-83] Releasing license: Synthesis
75 Infos, 122 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:53 . Memory (MB): peak = 2356.895 ; gain = 1082.195 ; free physical = 7132 ; free virtual = 28075
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2020.194; main = 1749.812; forked = 422.373
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3222.469; main = 2356.863; forked = 969.652
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors, 8 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.83 . Memory (MB): peak = 2420.891 ; gain = 63.996 ; free physical = 7132 ; free virtual = 28075

Starting Cache Timing Information Task
[30%] Placement Phase 2 completed
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1d73e3ebe

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2521.703 ; gain = 100.812 ; free physical = 7037 ; free virtual = 27980

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 1d73e3ebe

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6738 ; free virtual = 27681

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1d73e3ebe

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6738 ; free virtual = 27681
Phase 1 Initialization | Checksum: 1d73e3ebe

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6738 ; free virtual = 27681

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1d73e3ebe

Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6738 ; free virtual = 27681

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1d73e3ebe

Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6738 ; free virtual = 27681
Phase 2 Timer Update And Timing Data Collection | Checksum: 1d73e3ebe

Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6738 ; free virtual = 27681

Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 4 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 15607f865

Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27681
Retarget | Checksum: 15607f865
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 9 cells

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 15607f865

Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27681
Constant propagation | Checksum: 15607f865
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
Phase 5 Sweep | Checksum: 1b6112749

Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27681
Sweep | Checksum: 1b6112749
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 1 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 1b6112749

Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
BUFG optimization | Checksum: 1b6112749
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 1b6112749

Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
Shift Register Optimization | Checksum: 1b6112749
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1ccd9a113

Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
Post Processing Netlist | Checksum: 1ccd9a113
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1efa19506

Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.656 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27680
Phase 9.2 Verifying Netlist Connectivity | Checksum: 1efa19506

Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
Phase 9 Finalization | Checksum: 1efa19506

Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               9  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               8  |               1  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 1efa19506

Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.656 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27680

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1efa19506

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.656 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27680

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1efa19506

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.656 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27680

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.656 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27680
Ending Netlist Obfuscation Task | Checksum: 1efa19506

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.656 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27680
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2800.656 ; gain = 443.762 ; free physical = 6737 ; free virtual = 27680
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 8 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2832.672 ; gain = 0.000 ; free physical = 6734 ; free virtual = 27678
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 132263025

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2832.672 ; gain = 0.000 ; free physical = 6734 ; free virtual = 27678
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2832.672 ; gain = 0.000 ; free physical = 6734 ; free virtual = 27678

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Info:   at iteration #15: temp = 0.000000, timing cost = 18910, wirelen = 48148
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b12bef1e

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.87 . Memory (MB): peak = 2832.672 ; gain = 0.000 ; free physical = 6724 ; free virtual = 27667

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 13cc38048

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6725 ; free virtual = 27669

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 13cc38048

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6725 ; free virtual = 27669
Phase 1 Placer Initialization | Checksum: 13cc38048

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6725 ; free virtual = 27668

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 139701cf3

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6720 ; free virtual = 27664

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 18743fd81

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6720 ; free virtual = 27663

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 18743fd81

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6720 ; free virtual = 27663

Phase 2.4 Global Placement Core

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 17e84a9bc

Time (s): cpu = 00:00:14 ; elapsed = 00:00:04 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 83 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 26 nets or LUTs. Breaked 0 LUT, combined 26 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6721 ; free virtual = 27664

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |             26  |                    26  |           0  |           1  |  00:00:00  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            0  |             26  |                    26  |           0  |           4  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 86ea0019

Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664
Phase 2.4 Global Placement Core | Checksum: abf8aa4d

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664
Phase 2 Global Placement | Checksum: abf8aa4d

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: e52860bd

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b5dca078

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1953c58cd

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1758fd30f

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1eec441e6

Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6712 ; free virtual = 27656

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 18edbde39

Time (s): cpu = 00:00:21 ; elapsed = 00:00:08 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6712 ; free virtual = 27656

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 16f2f197b

Time (s): cpu = 00:00:21 ; elapsed = 00:00:08 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6712 ; free virtual = 27656
Phase 3 Detail Placement | Checksum: 16f2f197b

Time (s): cpu = 00:00:21 ; elapsed = 00:00:08 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6712 ; free virtual = 27656

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1b1e6ae87

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.882 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1f2328228

Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6711 ; free virtual = 27654
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1f2328228

Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6711 ; free virtual = 27654
Phase 4.1.1.1 BUFG Insertion | Checksum: 1b1e6ae87

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6711 ; free virtual = 27654

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1b09166ae

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6711 ; free virtual = 27654

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6711 ; free virtual = 27654
Phase 4.1 Post Commit Optimization | Checksum: 1b09166ae

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6710 ; free virtual = 27653

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1b09166ae

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6708 ; free virtual = 27651

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                2x2|
|___________|___________________|___________________|
|      South|                1x1|                1x1|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 1b09166ae

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6706 ; free virtual = 27650
Phase 4.3 Placer Reporting | Checksum: 1b09166ae

Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6702 ; free virtual = 27646

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6702 ; free virtual = 27645

Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6702 ; free virtual = 27645
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d0de6698

Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6712 ; free virtual = 27656
Ending Placer Task | Checksum: 155041d31

Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6712 ; free virtual = 27656
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 39.043 ; free physical = 6712 ; free virtual = 27656
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6711 ; free virtual = 27655
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6711 ; free virtual = 27655
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
Info:   at iteration #20: temp = 0.000000, timing cost = 20598, wirelen = 47178
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: 71c0046d ConstDB: 0 ShapeSum: e34418c4 RouteDB: 0
Info:   at iteration #25: temp = 0.000000, timing cost = 18894, wirelen = 46974
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
Info:   at iteration #30: temp = 0.000000, timing cost = 18441, wirelen = 46887
[70%] Routing Phase 1 completed
Info:   at iteration #32: temp = 0.000000, timing cost = 18377, wirelen = 46879 
Info: SA placement time 66.26s

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 28.96 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.44 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 9.24 ns

Info: Slack histogram:
Info:  legend: * represents 164 endpoint(s)
Info:          + represents [1,164) endpoint(s)
Info: [  5473,   7162) |+
Info: [  7162,   8851) |+
Info: [  8851,  10540) |******+
Info: [ 10540,  12229) |***+
Info: [ 12229,  13918) |**+
Info: [ 13918,  15607) |*+
Info: [ 15607,  17296) |***********+
Info: [ 17296,  18985) |************+
Info: [ 18985,  20674) |****************************+
Info: [ 20674,  22363) |************************************************************ 
Info: [ 22363,  24052) |***************************+
Info: [ 24052,  25741) |**+
Info: [ 25741,  27430) |****+
Info: [ 27430,  29119) |+
Info: [ 29119,  30808) |+
Info: [ 30808,  32497) |*+
Info: [ 32497,  34186) |**+
Info: [ 34186,  35875) |*+
Info: [ 35875,  37564) |+
Info: [ 37564,  39253) |*+
Info: Checksum: 0xa1b43a26
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 72221 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      173        826 |  173   826 |     71684|       1.28       1.28|
Info:       2000 |      305       1694 |  132   868 |     71199|       0.35       1.63|
Info:       3000 |      430       2569 |  125   875 |     70739|       0.36       1.99|
Info:       4000 |      551       3448 |  121   879 |     70013|       0.33       2.32|
Info:       5000 |      660       4339 |  109   891 |     69363|       0.34       2.66|
Info:       6000 |      763       5236 |  103   897 |     68943|       0.32       2.98|
Info:       7000 |      876       6123 |  113   887 |     68841|       0.51       3.49|
Info:       8000 |     1010       6989 |  134   866 |     68602|       0.48       3.97|
Info:       9000 |     1234       7765 |  224   776 |     68947|       0.48       4.45|
Info:      10000 |     1347       8652 |  113   887 |     68405|       0.44       4.89|
Info:      11000 |     1442       9557 |   95   905 |     68661|       0.51       5.40|
Info:      12000 |     1541      10458 |   99   901 |     68061|       0.49       5.89|
Info:      13000 |     1714      11285 |  173   827 |     67813|       0.47       6.37|
Info:      14000 |     1865      12134 |  151   849 |     67293|       0.47       6.84|
Info:      15000 |     1976      13023 |  111   889 |     67233|       0.37       7.21|
Info:      16000 |     2122      13877 |  146   854 |     66832|       0.47       7.68|
Post Restoration Checksum: NetGraph: 595bdcac | NumContArr: 3460bb3c | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2130e8d22

Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6636 ; free virtual = 27580

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2130e8d22

Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6636 ; free virtual = 27580

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2130e8d22

Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6636 ; free virtual = 27580
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2c7699a10

Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6609 ; free virtual = 27553
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797  | TNS=0.000  | WHS=0.008  | THS=0.000  |


Router Utilization Summary
  Global Vertical Routing Utilization    = 0.000217609 %
  Global Horizontal Routing Utilization  = 0.000213129 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 3787
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 3783
  Number of Partially Routed Nets     = 4
  Number of Node Overlaps             = 3

Phase 2 Router Initialization | Checksum: 2e7974fc7

Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6606 ; free virtual = 27550

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2e7974fc7

Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6606 ; free virtual = 27550

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 2a5c8a85e

Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6610 ; free virtual = 27554
Phase 3 Initial Routing | Checksum: 2a5c8a85e

Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6610 ; free virtual = 27554

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 506
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.540  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 167a082ba

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6594 ; free virtual = 27538
Phase 4 Rip-up And Reroute | Checksum: 167a082ba

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6594 ; free virtual = 27538

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 167a082ba

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6594 ; free virtual = 27538

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 167a082ba

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6593 ; free virtual = 27537
Phase 5 Delay and Skew Optimization | Checksum: 167a082ba

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6593 ; free virtual = 27537

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1a3a3d9e6

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6589 ; free virtual = 27533
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.636  | TNS=0.000  | WHS=0.364  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 1a3a3d9e6

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6589 ; free virtual = 27533
Phase 6 Post Hold Fix | Checksum: 1a3a3d9e6

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6589 ; free virtual = 27533

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.789442 %
  Global Horizontal Routing Utilization  = 0.955456 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 1a3a3d9e6

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6585 ; free virtual = 27529

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1a3a3d9e6

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6593 ; free virtual = 27537

Phase 9 Depositing Routes
Info:      17000 |     2284      14715 |  162   838 |     66178|       0.40       8.08|
Phase 9 Depositing Routes | Checksum: 12d123f57

Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6595 ; free virtual = 27539

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.636  | TNS=0.000  | WHS=0.364  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 12d123f57

Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6595 ; free virtual = 27539
INFO: [Route 35-16] Router Completed Successfully

Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 25faab08e

Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6595 ; free virtual = 27539
Info:      18000 |     2428      15571 |  144   856 |     65672|       0.38       8.46|
Ending Routing Task | Checksum: 25faab08e

Time (s): cpu = 00:00:48 ; elapsed = 00:00:33 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6595 ; free virtual = 27539

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:33 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6595 ; free virtual = 27539
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Info:      19000 |     2598      16401 |  170   830 |     65186|       0.45       8.91|
Info:      20000 |     2781      17218 |  183   817 |     64618|       0.36       9.27|
[80%] Routing Phase 2 completed
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (2142)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (6934)
5. checking no_input_delay (1)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (2142)
---------------------------
 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[36]/Q (HIGH)

 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[37]/Q (HIGH)

 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[39]/Q (HIGH)

 There are 2130 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (6934)
---------------------------------------------------
 There are 6934 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (1)
------------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (9)
-------------------------------
 There are 9 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      8.661        0.000                      0                    1        0.380        0.000                      0                    1        4.500        0.000                       0                     2  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock        Waveform(ns)       Period(ns)      Frequency(MHz)
-----        ------------       ----------      --------------
sys_clk_pin  {0.000 5.000}      10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
sys_clk_pin         8.661        0.000                      0                    1        0.380        0.000                      0                    1        4.500        0.000                       0                     2  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
Info:      21000 |     2963      18036 |  182   818 |     64336|       0.40       9.68|
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
Info:      22000 |     3105      18894 |  142   858 |     63956|       0.33      10.01|
INFO: [DRC 23-27] Running DRC with 8 threads
Info:      23000 |     3249      19750 |  144   856 |     63437|       0.48      10.50|
Info:      24000 |     3424      20575 |  175   825 |     65074|       0.44      10.94|
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Info:      25000 |     3576      21423 |  152   848 |     64802|       0.47      11.41|
Running Vector-less Activity Propagation...
Info:      26000 |     3697      22302 |  121   879 |     64160|       0.49      11.89|

Finished Running Vector-less Activity Propagation
Info:      27000 |     3796      23203 |   99   901 |     63377|       0.42      12.31|
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
Info:      28000 |     3917      24082 |  121   879 |     62856|       0.38      12.69|
Info:      29000 |     4130      24869 |  213   787 |     62505|       0.36      13.04|
Info:      30000 |     4295      25704 |  165   835 |     61996|       0.37      13.41|
Info:      31000 |     4484      26515 |  189   811 |     61560|       0.39      13.80|
Info:      32000 |     4644      27355 |  160   840 |     60892|       0.36      14.16|
Info:      33000 |     4843      28156 |  199   801 |     60353|       0.35      14.51|
Info:      34000 |     4988      29011 |  145   855 |     59907|       0.36      14.87|
Info:      35000 |     5161      29838 |  173   827 |     61697|       0.41      15.28|
Info:      36000 |     5291      30708 |  130   870 |     61053|       0.51      15.79|
Info:      37000 |     5397      31602 |  106   894 |     60279|       0.45      16.25|
Info:      38000 |     5511      32488 |  114   886 |     59483|       0.38      16.63|
Info:      39000 |     5704      33295 |  193   807 |     58968|       0.32      16.95|
Info:      40000 |     5853      34146 |  149   851 |     58560|       0.35      17.30|
Info:      41000 |     6016      34983 |  163   837 |     57998|       0.32      17.63|
Info:      42000 |     6162      35837 |  146   854 |     57641|       0.35      17.98|
Info:      43000 |     6308      36691 |  146   854 |     57009|       0.38      18.35|
Info:      44000 |     6457      37542 |  149   851 |     56568|       0.40      18.75|
Info:      45000 |     6698      38301 |  241   759 |     56360|       0.40      19.15|
Info:      46000 |     6854      39145 |  156   844 |     55722|       0.34      19.48|
Info:      47000 |     6984      40015 |  130   870 |     55136|       0.40      19.88|
Info:      48000 |     7167      40832 |  183   817 |     54574|       0.38      20.27|
Info:      49000 |     7285      41714 |  118   882 |     53969|       0.30      20.57|
Info:      50000 |     7427      42572 |  142   858 |     53343|       0.33      20.90|
Info:      51000 |     7555      43444 |  128   872 |     53354|       0.39      21.28|
WARN  (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
Info:      52000 |     7706      44293 |  151   849 |     52812|       0.36      21.65|
[90%] Routing Phase 3 completed
Info:      53000 |     7831      45168 |  125   875 |     52286|       0.35      22.00|
Info:      54000 |     7996      46003 |  165   835 |     51683|       0.37      22.38|
Running timing analysis......
Info:      55000 |     8113      46886 |  117   883 |     52034|       0.56      22.93|
Info:      56000 |     8201      47798 |   88   912 |     51390|       0.46      23.39|
Info:      57000 |     8336      48663 |  135   865 |     50739|       0.36      23.75|
Info:      58000 |     8513      49486 |  177   823 |     50223|       0.39      24.14|
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Info:      59000 |     8691      50308 |  178   822 |     49739|       0.37      24.51|
Info:      60000 |     8862      51137 |  171   829 |     49529|       0.31      24.82|
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[39]_0[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Info:      61000 |     9019      51980 |  157   843 |     49038|       0.39      25.21|
Info:      62000 |     9154      52845 |  135   865 |     48574|       0.39      25.60|
Info:      63000 |     9318      53681 |  164   836 |     48123|       0.37      25.97|
Info:      64000 |     9453      54546 |  135   865 |     47873|       0.41      26.38|
Info:      65000 |     9602      55397 |  149   851 |     47237|       0.37      26.75|
Info:      66000 |     9737      56262 |  135   865 |     46644|       0.36      27.11|
Loading site data...
Info:      67000 |     9915      57084 |  178   822 |     46007|       0.43      27.55|
Info:      68000 |    10085      57914 |  170   830 |     45526|       0.52      28.07|
Info:      69000 |    10257      58742 |  172   828 |     44881|       0.45      28.51|
Loading route data...
Processing options...
Creating bitmap...
Info:      70000 |    10429      59570 |  172   828 |     44456|       0.58      29.09|
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Info:      71000 |    10591      60408 |  162   838 |     44232|       0.76      29.85|
Info:      72000 |    10716      61283 |  125   875 |     43880|       0.46      30.32|
Info:      73000 |    10873      62126 |  157   843 |     43655|       0.45      30.77|
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Tue Apr 16 02:07:27 2024

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Info:      74000 |    11033      62966 |  160   840 |     43149|       0.40      31.16|
Creating bitstream...
Info:      75000 |    11208      63791 |  175   825 |     42501|       0.34      31.50|
Writing bitstream ./build/out.bit...
Info:      76000 |    11341      64658 |  133   867 |     42417|       0.43      31.93|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 3155.754 ; gain = 246.238 ; free physical = 6567 ; free virtual = 27524
INFO: [Common 17-206] Exiting Vivado at Tue Apr 16 02:07:28 2024...
Info:      77000 |    11524      65475 |  183   817 |     42042|       0.52      32.45|
[Pipeline] }
Info:      78000 |    11684      66315 |  160   840 |     41559|       0.36      32.80|
[Pipeline] // stage
[Pipeline] }
Info:      79000 |    11849      67150 |  165   835 |     41515|       0.43      33.23|
Info:      80000 |    12025      67974 |  176   824 |     41087|       0.42      33.65|
Info:      81000 |    12183      68816 |  158   842 |     40349|       0.33      33.98|
Info:      82000 |    12346      69653 |  163   837 |     40120|       0.33      34.31|
Info:      83000 |    12498      70501 |  152   848 |     39417|       0.32      34.63|
Info:      84000 |    12702      71297 |  204   796 |     38819|       0.39      35.02|
Info:      85000 |    12891      72108 |  189   811 |     38285|       0.40      35.42|
Info:      86000 |    13034      72965 |  143   857 |     37884|       0.40      35.82|
Info:      87000 |    13294      73705 |  260   740 |     37386|       0.35      36.17|
Info:      88000 |    13446      74553 |  152   848 |     36936|       0.35      36.52|
Info:      89000 |    13652      75347 |  206   794 |     36585|       0.48      37.00|
Info:      90000 |    13880      76119 |  228   772 |     36009|       0.36      37.36|
Info:      91000 |    14078      76921 |  198   802 |     36009|       0.42      37.78|
Info:      92000 |    14119      77880 |   41   959 |     37126|       0.58      38.36|
Info:      93000 |    14138      78861 |   19   981 |     36160|       0.50      38.87|
Info:      94000 |    14216      79783 |   78   922 |     35949|       0.43      39.29|
Info:      95000 |    14370      80629 |  154   846 |     35583|       0.43      39.73|
Info:      96000 |    14635      81364 |  265   735 |     35070|       0.37      40.09|
Info:      97000 |    14845      82154 |  210   790 |     34729|       0.42      40.51|
Info:      98000 |    15049      82950 |  204   796 |     34288|       0.45      40.96|
Info:      99000 |    15335      83664 |  286   714 |     33778|       0.40      41.36|
Info:     100000 |    15598      84401 |  263   737 |     33359|       0.39      41.74|
Info:     101000 |    15924      85075 |  326   674 |     32825|       0.41      42.16|
Info:     102000 |    16304      85695 |  380   620 |     32398|       0.43      42.59|
Info:     103000 |    16664      86335 |  360   640 |     34048|       0.42      43.01|
Info:     104000 |    16735      87264 |   71   929 |     33362|       0.48      43.50|
Info:     105000 |    16791      88208 |   56   944 |     32779|       0.37      43.87|
Info:     106000 |    16920      89079 |  129   871 |     32396|       0.39      44.26|
Info:     107000 |    17075      89924 |  155   845 |     31941|       0.37      44.63|
Info:     108000 |    17435      90564 |  360   640 |     31520|       0.48      45.11|
Info:     109000 |    17824      91175 |  389   611 |     31121|       0.44      45.55|
Info:     110000 |    18244      91755 |  420   580 |     30733|       0.44      45.99|
Info:     111000 |    18574      92425 |  330   670 |     30642|       0.44      46.43|
Info:     112000 |    18960      93039 |  386   614 |     30432|       0.42      46.85|
Info:     113000 |    19337      93662 |  377   623 |     30072|       0.45      47.30|
Info:     114000 |    19730      94269 |  393   607 |     29705|       0.43      47.73|
Info:     115000 |    20109      94890 |  379   621 |     29367|       0.44      48.17|
Info:     116000 |    20518      95481 |  409   591 |     29042|       0.45      48.62|
Info:     117000 |    20934      96065 |  416   584 |     28732|       0.49      49.11|
Info:     118000 |    21365      96634 |  431   569 |     28414|       0.47      49.58|
Info:     119000 |    21646      97353 |  281   719 |     29412|       0.48      50.05|
Info:     120000 |    21778      98221 |  132   868 |     29020|       0.48      50.54|
Info:     121000 |    21881      99118 |  103   897 |     28365|       0.57      51.10|
Info:     122000 |    22270      99729 |  389   611 |     28218|       0.51      51.61|
Info:     123000 |    22626     100373 |  356   644 |     27838|       0.43      52.04|
Info:     124000 |    23029     100970 |  403   597 |     27618|       0.47      52.51|
Info:     125000 |    23521     101478 |  492   508 |     27422|       0.46      52.97|
Info:     126000 |    23956     102043 |  435   565 |     27335|       0.48      53.45|
Info:     127000 |    24343     102656 |  387   613 |     27109|       0.47      53.92|
Info:     128000 |    24834     103165 |  491   509 |     26868|       0.47      54.40|
Info:     129000 |    25337     103662 |  503   497 |     26556|       0.47      54.87|
Info:     130000 |    25830     104169 |  493   507 |     26272|       0.45      55.32|
Info:     131000 |    26227     104772 |  397   603 |     26006|       0.43      55.75|
Info:     132000 |    26715     105284 |  488   512 |     25656|       0.42      56.17|
Info:     133000 |    27248     105751 |  533   467 |     25347|       0.47      56.64|
Info:     134000 |    27750     106249 |  502   498 |     25043|       0.46      57.10|
Info:     135000 |    28232     106767 |  482   518 |     24757|       0.46      57.56|
Info:     136000 |    28750     107249 |  518   482 |     24402|       0.44      58.00|
Info:     137000 |    29227     107772 |  477   523 |     24038|       0.43      58.42|
Info:     138000 |    29700     108286 |  473   514 |     23682|       0.49      58.91|
Info:     139000 |    30119     108836 |  419   550 |     23306|       0.44      59.36|
Info:     140000 |    30575     109362 |  456   526 |     22994|       0.48      59.84|
Info:     141000 |    30953     109933 |  378   571 |     22497|       0.36      60.20|
Info:     142000 |    31210     110640 |  257   707 |     26270|       0.35      60.54|
Info:     143000 |    31378     111472 |  168   832 |     26378|       0.50      61.04|
Info:     144000 |    31571     112279 |  193   807 |     26262|       0.56      61.61|
Info:     145000 |    31757     113093 |  186   814 |     25967|       0.63      62.23|
Info:     146000 |    31965     113885 |  208   792 |     25748|       0.59      62.82|
Info:     147000 |    32079     114771 |  114   886 |     25560|       0.50      63.32|
Info:     148000 |    32255     115595 |  176   824 |     25373|       0.60      63.92|
Info:     149000 |    32389     116461 |  134   866 |     24881|       0.62      64.54|
Info:     150000 |    32556     117294 |  167   833 |     24372|       0.49      65.03|
Info:     151000 |    32713     118137 |  157   843 |     24601|       0.53      65.55|
Info:     152000 |    32839     119011 |  126   874 |     24199|       0.50      66.06|
Info:     153000 |    32975     119875 |  136   864 |     23679|       0.48      66.54|
Info:     154000 |    33105     120745 |  130   870 |     22990|       0.49      67.03|
Info:     155000 |    33336     121514 |  231   769 |     22396|       0.63      67.66|
Info:     156000 |    33610     122240 |  274   726 |     22304|       0.54      68.20|
Info:     157000 |    33953     122897 |  343   657 |     22251|       0.50      68.70|
Info:     158000 |    34205     123630 |  252   733 |     21717|       0.40      69.11|
Info:     159000 |    34482     124299 |  277   669 |     21149|       0.32      69.42|
Info:     160000 |    34769     124922 |  287   623 |     20563|       0.35      69.77|
Info:     161000 |    35059     125541 |  290   619 |     19932|       0.31      70.08|
Info:     162000 |    35430     126060 |  371   519 |     19378|       0.36      70.44|
Info:     163000 |    35806     126579 |  376   519 |     18852|       0.36      70.79|
Info:     164000 |    36191     127087 |  385   508 |     18311|       0.36      71.16|
Info:     165000 |    36596     127602 |  405   515 |     17809|       0.39      71.55|
Info:     166000 |    37013     128078 |  417   476 |     17287|       0.40      71.94|
Info:     167000 |    37449     128534 |  436   456 |     16782|       0.41      72.35|
Info:     168000 |    37885     128978 |  436   444 |     16286|       0.43      72.78|
Info:     169000 |    38260     129523 |  375   545 |     15983|       0.48      73.26|
Info:     170000 |    38675     130060 |  415   537 |     15748|       0.55      73.80|
Info:     171000 |    39048     130572 |  373   512 |     15161|       0.38      74.18|
Info:     172000 |    39341     131146 |  293   574 |     14491|       0.34      74.52|
Info:     173000 |    39464     131953 |  123   807 |     13622|       0.23      74.76|
Info:     174000 |    39487     132918 |   23   965 |     12646|       0.17      74.93|
Info:     175000 |    39504     133898 |   17   980 |     11663|       0.16      75.08|
Info:     176000 |    39520     134880 |   16   982 |     10680|       0.15      75.23|
Info:     177000 |    39531     135868 |   11   988 |      9691|       0.16      75.39|
Info:     178000 |    39534     136864 |    3   996 |      8696|       0.16      75.56|
Info:     179000 |    39556     137841 |   22   977 |      7721|       0.18      75.74|
Info:     180000 |    39567     138828 |   11   987 |      6733|       0.18      75.91|
Info:     181000 |    39594     139801 |   27   973 |      5773|       0.19      76.11|
Info:     182000 |    39605     140788 |   11   987 |      4784|       0.16      76.27|
Info:     183000 |    39634     141752 |   29   964 |      3816|       0.17      76.44|
Info:     184000 |    39711     142635 |   77   883 |      2906|       0.24      76.68|
Info:     185000 |    39842     143484 |  131   849 |      2054|       0.33      77.01|
Info:     186000 |    40013     144206 |  171   722 |      1285|       0.39      77.40|
Info:     187000 |    40110     144892 |   97   686 |       429|       0.35      77.75|
Info:     187503 |    40136     145139 |   26   247 |         0|       0.28      78.03|
Info: Routing complete.
Info: Router1 time 78.03s
Info: Checksum: 0x3901d9ae

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q.Q
Info:  0.9  1.4    Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_B_LUT4_Z_1_C_LUT4_C_Z_LUT4_Z_1_C_LUT4_Z_D[0] (22,6) -> (23,5)
Info:                Sink SOC.Core.Control_Unit.save_address_LUT4_Z_D_LUT4_Z_B_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  1.7  Source SOC.Core.Control_Unit.save_address_LUT4_Z_D_LUT4_Z_B_LUT4_Z.F
Info:  1.6  3.2    Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_A_LUT4_C_Z_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z[1] (23,5) -> (28,9)
Info:                Sink SOC.Core.Control_Unit.save_address_LUT4_Z_D_LUT4_Z_B_PFUMX_C0_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3  3.5  Source SOC.Core.Control_Unit.save_address_LUT4_Z_D_LUT4_Z_B_PFUMX_C0_BLUT_LUT4_Z.OFX
Info:  2.5  6.0    Net SOC.Core.read_data_PFUMX_Z_13_C0[2] (28,9) -> (40,30)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3  6.2  Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  1.2  7.4    Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (40,30) -> (41,26)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.B
Info:  0.4  7.8  Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  7.8    Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (41,26) -> (41,26)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.9  Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  7.9    Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (41,26) -> (41,26)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  7.9  Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  7.9    Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (41,26) -> (41,26)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.0  Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  8.0    Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (41,26) -> (41,26)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  8.0  Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  8.0    Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (41,26) -> (42,26)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.1  Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  8.1    Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (42,26) -> (42,26)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  8.1  Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  8.1    Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1_CIN (42,26) -> (42,26)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.1  Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  8.1    Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (42,26) -> (42,26)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  8.1  Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  8.1    Net $nextpnr_CCU2C_7$CIN (42,26) -> (42,26)
Info:                Sink $nextpnr_CCU2C_7$CCU2_COMB0.FCI
Info:  0.4  8.6  Source $nextpnr_CCU2C_7$CCU2_COMB0.F
Info:  1.1  9.7    Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1_COUT (42,26) -> (41,30)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B1_LUT4_C.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  9.9  Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B1_LUT4_C.F
Info:  1.6 11.5    Net SOC.Memory.address_LUT4_Z_1_C[1] (41,30) -> (21,31)
Info:                Sink SOC.Memory.address_LUT4_Z_2.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 11.7  Source SOC.Memory.address_LUT4_Z_2.F
Info:  3.8 15.5    Net SOC.slave_address[3] (21,31) -> (64,40)
Info:                Sink SOC.Memory.memory.0.831$DPRAM_COMB3.B
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:22.5-22.18
Info:  0.2 15.7  Source SOC.Memory.memory.0.831$DPRAM_COMB3.F
Info:  1.1 16.9    Net SOC.Memory.memory.0.815_DO[2] (64,40) -> (63,41)
Info:                Sink SOC.Memory.memory.0.775_DO_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 17.1  Source SOC.Memory.memory.0.775_DO_LUT4_Z.F
Info:  0.7 17.8    Net SOC.Memory.memory.0.775_DO[4] (63,41) -> (65,41)
Info:                Sink SOC.Memory.memory.0.799_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 18.0  Source SOC.Memory.memory.0.799_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.2 18.2    Net SOC.Memory.memory.0.799_DO_LUT4_A_Z[3] (65,41) -> (65,41)
Info:                Sink SOC.Memory.memory.0.799_DO_LUT4_A_Z_LUT4_B.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 18.4  Source SOC.Memory.memory.0.799_DO_LUT4_A_Z_LUT4_B.F
Info:  1.3 19.8    Net SOC.Memory.memory.0.799_DO_LUT4_A_Z_LUT4_B_Z[2] (65,41) -> (60,37)
Info:                Sink SOC.Memory.memory.0.839_DO_LUT4_B_Z_LUT4_B_Z_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 20.0  Source SOC.Memory.memory.0.839_DO_LUT4_B_Z_LUT4_B_Z_LUT4_Z.F
Info:  0.6 20.6    Net SOC.Memory.memory.0.839_DO_LUT4_B_Z_LUT4_B_Z[3] (60,37) -> (58,37)
Info:                Sink SOC.Memory.memory.0.839_DO_LUT4_B_Z_LUT4_B_Z_LUT4_B.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 20.8  Source SOC.Memory.memory.0.839_DO_LUT4_B_Z_LUT4_B_Z_LUT4_B.F
Info:  1.1 21.9    Net SOC.Memory.memory.0.79_DO_LUT4_C_Z_LUT4_B_Z_LUT4_B_Z[4] (58,37) -> (56,33)
Info:                Sink SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 22.2  Source SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.0 22.2    Net SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 (56,33) -> (56,33)
Info:                Sink SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64
Info:  0.2 22.4  Source SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  0.0 22.4    Net SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1 (56,33) -> (56,33)
Info:                Sink SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info:  0.2 22.7  Source SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  1.9 24.6    Net SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z[4] (56,33) -> (29,33)
Info:                Sink SOC.Core.read_data_PFUMX_Z_20_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 24.8  Source SOC.Core.read_data_PFUMX_Z_20_BLUT_LUT4_Z.OFX
Info:  1.9 26.7    Net SOC.read_data[31] (29,33) -> (29,12)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q.M
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:21.34-21.43
Info:  0.0 26.7  Setup SOC.Core.instruction_register_TRELLIS_FF_Q.M
Info: 5.4 ns logic, 21.4 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source rx$tr_io.O
Info:  2.3  2.3    Net rx$TRELLIS_IO_IN (90,20) -> (66,16)
Info:                Sink SOC.Uart.i_uart_rx.rxd_reg_0_TRELLIS_FF_Q.M
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:4.16-4.18
Info:  0.0  2.3  Setup SOC.Uart.i_uart_rx.rxd_reg_0_TRELLIS_FF_Q.M
Info: 0.0 ns logic, 2.3 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info:  1.7  2.3    Net SOC.Core.read_data_LUT4_Z_2_C[0] (48,7) -> (70,7)
Info:                Sink led_LUT4_Z_5.D
Info:                Defined in:
Info:                  Risco-5/src/peripheral/leds.v:15.12-15.16
Info:  0.2  2.5  Source led_LUT4_Z_5.F
Info:  3.8  6.3    Net led[2]$TRELLIS_IO_OUT (70,7) -> (90,44)
Info:                Sink led[2]$tr_io.I
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.5 ns routing

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 37.40 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 2.27 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 6.31 ns

Info: Slack histogram:
Info:  legend: * represents 174 endpoint(s)
Info:          + represents [1,174) endpoint(s)
Info: [ 13260,  14550) |+
Info: [ 14550,  15840) |**+
Info: [ 15840,  17130) |*****+
Info: [ 17130,  18420) |****+
Info: [ 18420,  19710) |+
Info: [ 19710,  21000) |+
Info: [ 21000,  22290) |********+
Info: [ 22290,  23580) |*************+
Info: [ 23580,  24870) |****************+
Info: [ 24870,  26160) |************************************************************ 
Info: [ 26160,  27450) |*********************************+
Info: [ 27450,  28740) |**+
Info: [ 28740,  30030) |****+
Info: [ 30030,  31320) |+
Info: [ 31320,  32610) |+
Info: [ 32610,  33900) |+
Info: [ 33900,  35190) |**+
Info: [ 35190,  36480) |*+
Info: [ 36480,  37770) |+
Info: [ 37770,  39060) |*+

Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
FPGA TangNano Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
[Pipeline] }
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Open file DONE
Parse file DONE
load program
Lock released on resource [tangnano20k]
[Pipeline] // lock

Loading: [====                                              ] 7.59%[Pipeline] }
[Pipeline] // script
[Pipeline] }

Load SRAM: [=========                                         ] 18.00%[Pipeline] // stage
[Pipeline] }

Loading: [========                                          ] 15.19%
Load SRAM: [===================                               ] 38.00%
Loading: [============                                      ] 22.78%
Load SRAM: [=============================                     ] 58.00%
Loading: [================                                  ] 30.38%
Load SRAM: [=======================================           ] 78.00%
Loading: [===================                               ] 37.97%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
[Pipeline] }

Loading: [=======================                           ] 45.56%Lock released on resource [nexys4]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }

Loading: [===========================                       ] 53.16%
Loading: [===============================                   ] 60.75%
Loading: [===================================               ] 68.35%
Loading: [======================================            ] 75.94%
Loading: [==========================================        ] 83.53%
Loading: [==============================================    ] 91.13%
Loading: [==================================================] 98.72%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
[Pipeline] }
+ echo testando na tang nano
testando na tang nano
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS