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Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 800/43848 1%
Info: TRELLIS_COMB: 14695/43848 33%
Info: TRELLIS_RAMW: 1076/ 5481 19%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 6578 cells, random placement wirelen = 610494.
Info: at initial placer iter 0, wirelen = 2233
Info: at initial placer iter 1, wirelen = 1981
Info: at initial placer iter 2, wirelen = 1933
Info: at initial placer iter 3, wirelen = 1901
Info: Running main analytical placer, max placement attempts per cell = 34403512.
Info: at iteration #1, type ALL: wirelen solved = 1968, spread = 105700, legal = 106868; time = 0.51s
Info: at iteration #2, type ALL: wirelen solved = 7118, spread = 80768, legal = 82108; time = 0.47s
Info: at iteration #3, type ALL: wirelen solved = 13194, spread = 74058, legal = 75808; time = 0.51s
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 7157 ; free virtual = 28089
---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 7157 ; free virtual = 28089
---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 7157 ; free virtual = 28089
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 0000000000000000000000000000000000000000000001 | 000000
DECODE | 0000000000000000000000000000000000000000000010 | 000001
MEMADR | 0000000000000000000000000000000000000000000100 | 000010
MEMREAD_UNALIGNED | 0000000000000000000000000000000000000000001000 | 010110
LOAD_FIRST_BLOCK | 0000000000000000000000000000000000000000010000 | 010000
SAVE_FIRST_BLOCK | 0000000000000000000000000000000000000000100000 | 010001
CALC_NEXT_ADDRESS | 0000000000000000000000000000000000000001000000 | 010010
READ_SECOND_BLOCK | 0000000000000000000000000000000000000010000000 | 010011
LOAD_SECOND_BLOCK | 0000000000000000000000000000000000000100000000 | 010100
MERGE_BLOCKS | 0000000000000000000000000000000000001000000000 | 010101
FILTER_ALU_WB | 0000000000000000000000000000000000010000000000 | 010111
MEMREAD | 0000000000000000000000000000000000100000000000 | 000011
MEMWB | 0000000000000000000000000000000001000000000000 | 000100
MEMWRITE_UNALIGNED | 0000000000000000000000000000000010000000000000 | 011000
GEN_FIRST_BLOCK_PART_1 | 0000000000000000000000000000000100000000000000 | 011001
GEN_FIRST_BLOCK_PART_2 | 0000000000000000000000000000001000000000000000 | 011010
GEN_SECOND_BLOCK_PART_1 | 0000000000000000000000000000010000000000000000 | 011011
GEN_SECOND_BLOCK_PART_2 | 0000000000000000000000000000100000000000000000 | 011100
MERGE_WRITE_BLOCKS | 0000000000000000000000000001000000000000000000 | 011101
SWAP_VALUE_DIRECTION | 0000000000000000000000000010000000000000000000 | 011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 0000000000000000000000000100000000000000000000 | 100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 0000000000000000000000001000000000000000000000 | 100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 0000000000000000000000010000000000000000000000 | 100100
CLEAR_VALUE | 0000000000000000000000100000000000000000000000 | 011111
MERGE_WRITE_VALUE_1 | 0000000000000000000001000000000000000000000000 | 100000
WRITE_VALUE_1 | 0000000000000000000010000000000000000000000000 | 100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 0000000000000000000100000000000000000000000000 | 100101
READ_SECOND_BLOCK_TO_WRITE | 0000000000000000001000000000000000000000000000 | 100110
LOAD_SECOND_BLOCK_TO_WRITE | 0000000000000000010000000000000000000000000000 | 100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 0000000000000000100000000000000000000000000000 | 101000
SWAP_VALUE_DIRECTION_2 | 0000000000000001000000000000000000000000000000 | 101001
CLEAR_VALUE_PART_2 | 0000000000000010000000000000000000000000000000 | 101010
CLEAR_VALUE_PART_2_1 | 0000000000000100000000000000000000000000000000 | 101011
MERGE_WRITE_VALUE_2 | 0000000000001000000000000000000000000000000000 | 101100
WRITE_VALUE_2 | 0000000000010000000000000000000000000000000000 | 101101
MEMWRITE | 0000000000100000000000000000000000000000000000 | 000101
EXECUTER | 0000000001000000000000000000000000000000000000 | 000110
EXECUTEI | 0000000010000000000000000000000000000000000000 | 001000
JAL | 0000000100000000000000000000000000000000000000 | 001001
BEQ | 0000001000000000000000000000000000000000000000 | 001010
AUIPC | 0000010000000000000000000000000000000000000000 | 001100
LUI | 0000100000000000000000000000000000000000000000 | 001101
JALR_PC | 0001000000000000000000000000000000000000000000 | 001110
JALR | 0010000000000000000000000000000000000000000000 | 001011
ALUWB | 0100000000000000000000000000000000000000000000 | 000111
EXECUTECSR | 1000000000000000000000000000000000000000000000 | 001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 7150 ; free virtual = 28084
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
3 Input 32 Bit Adders := 1
2 Input 11 Bit Adders := 2
2 Input 6 Bit Adders := 4
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
+---XORs :
2 Bit Wide XORs := 1
+---Registers :
33 Bit Registers := 1
32 Bit Registers := 47
16 Bit Registers := 2
11 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 1
4 Bit Registers := 2
1 Bit Registers := 18
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
46 Input 46 Bit Muxes := 1
11 Input 46 Bit Muxes := 1
2 Input 46 Bit Muxes := 8
3 Input 33 Bit Muxes := 1
2 Input 32 Bit Muxes := 35
8 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 13
16 Input 32 Bit Muxes := 1
6 Input 32 Bit Muxes := 1
2 Input 8 Bit Muxes := 3
5 Input 8 Bit Muxes := 1
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
46 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 1
8 Input 4 Bit Muxes := 1
23 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
4 Input 3 Bit Muxes := 2
46 Input 3 Bit Muxes := 3
10 Input 3 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 14
46 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 4
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 49
46 Input 1 Bit Muxes := 11
4 Input 1 Bit Muxes := 2
13 Input 1 Bit Muxes := 2
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Info: at iteration #4, type ALL: wirelen solved = 17530, spread = 68351, legal = 69955; time = 0.60s
Info: at iteration #5, type ALL: wirelen solved = 21848, spread = 65546, legal = 67062; time = 0.49s
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
Info: at iteration #6, type ALL: wirelen solved = 25295, spread = 67040, legal = 68165; time = 0.43s
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
Info: at iteration #7, type ALL: wirelen solved = 29799, spread = 62035, legal = 63223; time = 0.45s
Info: at iteration #8, type ALL: wirelen solved = 31090, spread = 65681, legal = 66599; time = 0.50s
Info: at iteration #9, type ALL: wirelen solved = 33815, spread = 65153, legal = 66144; time = 0.52s
Info: at iteration #10, type ALL: wirelen solved = 34809, spread = 64111, legal = 64973; time = 0.42s
Info: at iteration #11, type ALL: wirelen solved = 36683, spread = 63381, legal = 64501; time = 0.42s
Info: at iteration #12, type ALL: wirelen solved = 36611, spread = 64613, legal = 65711; time = 0.43s
Info: HeAP Placer Time: 9.81s
Info: of which solving equations: 6.15s
Info: of which spreading cells: 0.68s
Info: of which strict legalisation: 0.19s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 15234, wirelen = 63223
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":221)
WARN (NL0002) : The module "MUX" instantiated to "MemoryAddressMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":97)
WARN (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":149)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
Info: at iteration #5: temp = 0.000000, timing cost = 18164, wirelen = 51878
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6948 ; free virtual = 27891
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6945 ; free virtual = 27888
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6868 ; free virtual = 27812
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27806
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
Info: at iteration #10: temp = 0.000000, timing cost = 16569, wirelen = 49303
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 55|
|3 |LUT1 | 15|
|4 |LUT2 | 161|
|5 |LUT3 | 254|
|6 |LUT4 | 283|
|7 |LUT5 | 454|
|8 |LUT6 | 1494|
|9 |MUXF7 | 406|
|10 |MUXF8 | 2|
|11 |RAM256X1S | 64|
|12 |RAM32M | 2|
|13 |RAM32X1D | 4|
|14 |FDRE | 1838|
|15 |FDSE | 5|
|16 |LD | 4|
|17 |IBUF | 2|
|18 |OBUF | 9|
|19 |OBUFT | 8|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 44 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2284.863 ; gain = 509.465 ; free physical = 6862 ; free virtual = 27805
Synthesis Optimization Complete : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2284.863 ; gain = 660.250 ; free physical = 6862 ; free virtual = 27805
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2284.863 ; gain = 0.000 ; free physical = 7135 ; free virtual = 28079
INFO: [Netlist 29-17] Analyzing 537 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2356.859 ; gain = 0.000 ; free physical = 7132 ; free virtual = 28075
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 74 instances were transformed.
LD => LDCE: 4 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 1fbd9dc9
INFO: [Common 17-83] Releasing license: Synthesis
75 Infos, 122 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:53 . Memory (MB): peak = 2356.895 ; gain = 1082.195 ; free physical = 7132 ; free virtual = 28075
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2020.194; main = 1749.812; forked = 422.373
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3222.469; main = 2356.863; forked = 969.652
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors, 8 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.83 . Memory (MB): peak = 2420.891 ; gain = 63.996 ; free physical = 7132 ; free virtual = 28075
Starting Cache Timing Information Task
[30%] Placement Phase 2 completed
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1d73e3ebe
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2521.703 ; gain = 100.812 ; free physical = 7037 ; free virtual = 27980
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 1d73e3ebe
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6738 ; free virtual = 27681
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1d73e3ebe
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6738 ; free virtual = 27681
Phase 1 Initialization | Checksum: 1d73e3ebe
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6738 ; free virtual = 27681
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1d73e3ebe
Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6738 ; free virtual = 27681
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1d73e3ebe
Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6738 ; free virtual = 27681
Phase 2 Timer Update And Timing Data Collection | Checksum: 1d73e3ebe
Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6738 ; free virtual = 27681
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 4 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 15607f865
Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27681
Retarget | Checksum: 15607f865
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 9 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 15607f865
Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27681
Constant propagation | Checksum: 15607f865
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 1b6112749
Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2768.641 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27681
Sweep | Checksum: 1b6112749
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 1 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 1b6112749
Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
BUFG optimization | Checksum: 1b6112749
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 1b6112749
Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
Shift Register Optimization | Checksum: 1b6112749
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1ccd9a113
Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
Post Processing Netlist | Checksum: 1ccd9a113
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1efa19506
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.656 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27680
Phase 9.2 Verifying Netlist Connectivity | Checksum: 1efa19506
Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
Phase 9 Finalization | Checksum: 1efa19506
Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 9 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 8 | 1 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 1efa19506
Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2800.656 ; gain = 32.016 ; free physical = 6737 ; free virtual = 27680
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.656 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27680
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1efa19506
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.656 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27680
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1efa19506
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.656 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27680
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.656 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27680
Ending Netlist Obfuscation Task | Checksum: 1efa19506
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.656 ; gain = 0.000 ; free physical = 6737 ; free virtual = 27680
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2800.656 ; gain = 443.762 ; free physical = 6737 ; free virtual = 27680
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 8 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2832.672 ; gain = 0.000 ; free physical = 6734 ; free virtual = 27678
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 132263025
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2832.672 ; gain = 0.000 ; free physical = 6734 ; free virtual = 27678
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2832.672 ; gain = 0.000 ; free physical = 6734 ; free virtual = 27678
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Info: at iteration #15: temp = 0.000000, timing cost = 18910, wirelen = 48148
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b12bef1e
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.87 . Memory (MB): peak = 2832.672 ; gain = 0.000 ; free physical = 6724 ; free virtual = 27667
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 13cc38048
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6725 ; free virtual = 27669
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 13cc38048
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6725 ; free virtual = 27669
Phase 1 Placer Initialization | Checksum: 13cc38048
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6725 ; free virtual = 27668
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 139701cf3
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6720 ; free virtual = 27664
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 18743fd81
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6720 ; free virtual = 27663
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 18743fd81
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6720 ; free virtual = 27663
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 17e84a9bc
Time (s): cpu = 00:00:14 ; elapsed = 00:00:04 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 83 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 26 nets or LUTs. Breaked 0 LUT, combined 26 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6721 ; free virtual = 27664
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 26 | 26 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 26 | 26 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 86ea0019
Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664
Phase 2.4 Global Placement Core | Checksum: abf8aa4d
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664
Phase 2 Global Placement | Checksum: abf8aa4d
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: e52860bd
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b5dca078
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1953c58cd
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1758fd30f
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6721 ; free virtual = 27664
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1eec441e6
Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6712 ; free virtual = 27656
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 18edbde39
Time (s): cpu = 00:00:21 ; elapsed = 00:00:08 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6712 ; free virtual = 27656
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 16f2f197b
Time (s): cpu = 00:00:21 ; elapsed = 00:00:08 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6712 ; free virtual = 27656
Phase 3 Detail Placement | Checksum: 16f2f197b
Time (s): cpu = 00:00:21 ; elapsed = 00:00:08 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6712 ; free virtual = 27656
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1b1e6ae87
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.882 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1f2328228
Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6711 ; free virtual = 27654
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1f2328228
Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6711 ; free virtual = 27654
Phase 4.1.1.1 BUFG Insertion | Checksum: 1b1e6ae87
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6711 ; free virtual = 27654
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1b09166ae
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6711 ; free virtual = 27654
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6711 ; free virtual = 27654
Phase 4.1 Post Commit Optimization | Checksum: 1b09166ae
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6710 ; free virtual = 27653
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1b09166ae
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6708 ; free virtual = 27651
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 2x2|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1b09166ae
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6706 ; free virtual = 27650
Phase 4.3 Placer Reporting | Checksum: 1b09166ae
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6702 ; free virtual = 27646
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6702 ; free virtual = 27645
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6702 ; free virtual = 27645
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d0de6698
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6712 ; free virtual = 27656
Ending Placer Task | Checksum: 155041d31
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 7.027 ; free physical = 6712 ; free virtual = 27656
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.699 ; gain = 39.043 ; free physical = 6712 ; free virtual = 27656
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6711 ; free virtual = 27655
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6711 ; free virtual = 27655
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
Info: at iteration #20: temp = 0.000000, timing cost = 20598, wirelen = 47178
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 71c0046d ConstDB: 0 ShapeSum: e34418c4 RouteDB: 0
Info: at iteration #25: temp = 0.000000, timing cost = 18894, wirelen = 46974
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
Info: at iteration #30: temp = 0.000000, timing cost = 18441, wirelen = 46887
[70%] Routing Phase 1 completed
Info: at iteration #32: temp = 0.000000, timing cost = 18377, wirelen = 46879
Info: SA placement time 66.26s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 28.96 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.44 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 9.24 ns
Info: Slack histogram:
Info: legend: * represents 164 endpoint(s)
Info: + represents [1,164) endpoint(s)
Info: [ 5473, 7162) |+
Info: [ 7162, 8851) |+
Info: [ 8851, 10540) |******+
Info: [ 10540, 12229) |***+
Info: [ 12229, 13918) |**+
Info: [ 13918, 15607) |*+
Info: [ 15607, 17296) |***********+
Info: [ 17296, 18985) |************+
Info: [ 18985, 20674) |****************************+
Info: [ 20674, 22363) |************************************************************
Info: [ 22363, 24052) |***************************+
Info: [ 24052, 25741) |**+
Info: [ 25741, 27430) |****+
Info: [ 27430, 29119) |+
Info: [ 29119, 30808) |+
Info: [ 30808, 32497) |*+
Info: [ 32497, 34186) |**+
Info: [ 34186, 35875) |*+
Info: [ 35875, 37564) |+
Info: [ 37564, 39253) |*+
Info: Checksum: 0xa1b43a26
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 72221 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 173 826 | 173 826 | 71684| 1.28 1.28|
Info: 2000 | 305 1694 | 132 868 | 71199| 0.35 1.63|
Info: 3000 | 430 2569 | 125 875 | 70739| 0.36 1.99|
Info: 4000 | 551 3448 | 121 879 | 70013| 0.33 2.32|
Info: 5000 | 660 4339 | 109 891 | 69363| 0.34 2.66|
Info: 6000 | 763 5236 | 103 897 | 68943| 0.32 2.98|
Info: 7000 | 876 6123 | 113 887 | 68841| 0.51 3.49|
Info: 8000 | 1010 6989 | 134 866 | 68602| 0.48 3.97|
Info: 9000 | 1234 7765 | 224 776 | 68947| 0.48 4.45|
Info: 10000 | 1347 8652 | 113 887 | 68405| 0.44 4.89|
Info: 11000 | 1442 9557 | 95 905 | 68661| 0.51 5.40|
Info: 12000 | 1541 10458 | 99 901 | 68061| 0.49 5.89|
Info: 13000 | 1714 11285 | 173 827 | 67813| 0.47 6.37|
Info: 14000 | 1865 12134 | 151 849 | 67293| 0.47 6.84|
Info: 15000 | 1976 13023 | 111 889 | 67233| 0.37 7.21|
Info: 16000 | 2122 13877 | 146 854 | 66832| 0.47 7.68|
Post Restoration Checksum: NetGraph: 595bdcac | NumContArr: 3460bb3c | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2130e8d22
Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6636 ; free virtual = 27580
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2130e8d22
Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6636 ; free virtual = 27580
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2130e8d22
Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6636 ; free virtual = 27580
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2c7699a10
Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6609 ; free virtual = 27553
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 |
Router Utilization Summary
Global Vertical Routing Utilization = 0.000217609 %
Global Horizontal Routing Utilization = 0.000213129 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 3787
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 3783
Number of Partially Routed Nets = 4
Number of Node Overlaps = 3
Phase 2 Router Initialization | Checksum: 2e7974fc7
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6606 ; free virtual = 27550
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2e7974fc7
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6606 ; free virtual = 27550
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 2a5c8a85e
Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6610 ; free virtual = 27554
Phase 3 Initial Routing | Checksum: 2a5c8a85e
Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6610 ; free virtual = 27554
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 506
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.540 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 167a082ba
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6594 ; free virtual = 27538
Phase 4 Rip-up And Reroute | Checksum: 167a082ba
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6594 ; free virtual = 27538
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 167a082ba
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6594 ; free virtual = 27538
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 167a082ba
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6593 ; free virtual = 27537
Phase 5 Delay and Skew Optimization | Checksum: 167a082ba
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6593 ; free virtual = 27537
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1a3a3d9e6
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6589 ; free virtual = 27533
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 1a3a3d9e6
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6589 ; free virtual = 27533
Phase 6 Post Hold Fix | Checksum: 1a3a3d9e6
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6589 ; free virtual = 27533
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.789442 %
Global Horizontal Routing Utilization = 0.955456 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1a3a3d9e6
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6585 ; free virtual = 27529
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1a3a3d9e6
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6593 ; free virtual = 27537
Phase 9 Depositing Routes
Info: 17000 | 2284 14715 | 162 838 | 66178| 0.40 8.08|
Phase 9 Depositing Routes | Checksum: 12d123f57
Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6595 ; free virtual = 27539
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 12d123f57
Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6595 ; free virtual = 27539
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 25faab08e
Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6595 ; free virtual = 27539
Info: 18000 | 2428 15571 | 144 856 | 65672| 0.38 8.46|
Ending Routing Task | Checksum: 25faab08e
Time (s): cpu = 00:00:48 ; elapsed = 00:00:33 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6595 ; free virtual = 27539
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:33 . Memory (MB): peak = 2839.699 ; gain = 0.000 ; free physical = 6595 ; free virtual = 27539
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Info: 19000 | 2598 16401 | 170 830 | 65186| 0.45 8.91|
Info: 20000 | 2781 17218 | 183 817 | 64618| 0.36 9.27|
[80%] Routing Phase 2 completed
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (2142)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (6934)
5. checking no_input_delay (1)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (2142)
---------------------------
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[36]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[37]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[39]/Q (HIGH)
There are 2130 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (6934)
---------------------------------------------------
There are 6934 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (9)
-------------------------------
There are 9 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
Info: 21000 | 2963 18036 | 182 818 | 64336| 0.40 9.68|
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
Info: 22000 | 3105 18894 | 142 858 | 63956| 0.33 10.01|
INFO: [DRC 23-27] Running DRC with 8 threads
Info: 23000 | 3249 19750 | 144 856 | 63437| 0.48 10.50|
Info: 24000 | 3424 20575 | 175 825 | 65074| 0.44 10.94|
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Info: 25000 | 3576 21423 | 152 848 | 64802| 0.47 11.41|
Running Vector-less Activity Propagation...
Info: 26000 | 3697 22302 | 121 879 | 64160| 0.49 11.89|
Finished Running Vector-less Activity Propagation
Info: 27000 | 3796 23203 | 99 901 | 63377| 0.42 12.31|
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
Info: 28000 | 3917 24082 | 121 879 | 62856| 0.38 12.69|
Info: 29000 | 4130 24869 | 213 787 | 62505| 0.36 13.04|
Info: 30000 | 4295 25704 | 165 835 | 61996| 0.37 13.41|
Info: 31000 | 4484 26515 | 189 811 | 61560| 0.39 13.80|
Info: 32000 | 4644 27355 | 160 840 | 60892| 0.36 14.16|
Info: 33000 | 4843 28156 | 199 801 | 60353| 0.35 14.51|
Info: 34000 | 4988 29011 | 145 855 | 59907| 0.36 14.87|
Info: 35000 | 5161 29838 | 173 827 | 61697| 0.41 15.28|
Info: 36000 | 5291 30708 | 130 870 | 61053| 0.51 15.79|
Info: 37000 | 5397 31602 | 106 894 | 60279| 0.45 16.25|
Info: 38000 | 5511 32488 | 114 886 | 59483| 0.38 16.63|
Info: 39000 | 5704 33295 | 193 807 | 58968| 0.32 16.95|
Info: 40000 | 5853 34146 | 149 851 | 58560| 0.35 17.30|
Info: 41000 | 6016 34983 | 163 837 | 57998| 0.32 17.63|
Info: 42000 | 6162 35837 | 146 854 | 57641| 0.35 17.98|
Info: 43000 | 6308 36691 | 146 854 | 57009| 0.38 18.35|
Info: 44000 | 6457 37542 | 149 851 | 56568| 0.40 18.75|
Info: 45000 | 6698 38301 | 241 759 | 56360| 0.40 19.15|
Info: 46000 | 6854 39145 | 156 844 | 55722| 0.34 19.48|
Info: 47000 | 6984 40015 | 130 870 | 55136| 0.40 19.88|
Info: 48000 | 7167 40832 | 183 817 | 54574| 0.38 20.27|
Info: 49000 | 7285 41714 | 118 882 | 53969| 0.30 20.57|
Info: 50000 | 7427 42572 | 142 858 | 53343| 0.33 20.90|
Info: 51000 | 7555 43444 | 128 872 | 53354| 0.39 21.28|
WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
Info: 52000 | 7706 44293 | 151 849 | 52812| 0.36 21.65|
[90%] Routing Phase 3 completed
Info: 53000 | 7831 45168 | 125 875 | 52286| 0.35 22.00|
Info: 54000 | 7996 46003 | 165 835 | 51683| 0.37 22.38|
Running timing analysis......
Info: 55000 | 8113 46886 | 117 883 | 52034| 0.56 22.93|
Info: 56000 | 8201 47798 | 88 912 | 51390| 0.46 23.39|
Info: 57000 | 8336 48663 | 135 865 | 50739| 0.36 23.75|
Info: 58000 | 8513 49486 | 177 823 | 50223| 0.39 24.14|
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Info: 59000 | 8691 50308 | 178 822 | 49739| 0.37 24.51|
Info: 60000 | 8862 51137 | 171 829 | 49529| 0.31 24.82|
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[39]_0[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Info: 61000 | 9019 51980 | 157 843 | 49038| 0.39 25.21|
Info: 62000 | 9154 52845 | 135 865 | 48574| 0.39 25.60|
Info: 63000 | 9318 53681 | 164 836 | 48123| 0.37 25.97|
Info: 64000 | 9453 54546 | 135 865 | 47873| 0.41 26.38|
Info: 65000 | 9602 55397 | 149 851 | 47237| 0.37 26.75|
Info: 66000 | 9737 56262 | 135 865 | 46644| 0.36 27.11|
Loading site data...
Info: 67000 | 9915 57084 | 178 822 | 46007| 0.43 27.55|
Info: 68000 | 10085 57914 | 170 830 | 45526| 0.52 28.07|
Info: 69000 | 10257 58742 | 172 828 | 44881| 0.45 28.51|
Loading route data...
Processing options...
Creating bitmap...
Info: 70000 | 10429 59570 | 172 828 | 44456| 0.58 29.09|
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Info: 71000 | 10591 60408 | 162 838 | 44232| 0.76 29.85|
Info: 72000 | 10716 61283 | 125 875 | 43880| 0.46 30.32|
Info: 73000 | 10873 62126 | 157 843 | 43655| 0.45 30.77|
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Tue Apr 16 02:07:27 2024
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Info: 74000 | 11033 62966 | 160 840 | 43149| 0.40 31.16|
Creating bitstream...
Info: 75000 | 11208 63791 | 175 825 | 42501| 0.34 31.50|
Writing bitstream ./build/out.bit...
Info: 76000 | 11341 64658 | 133 867 | 42417| 0.43 31.93|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 3155.754 ; gain = 246.238 ; free physical = 6567 ; free virtual = 27524
INFO: [Common 17-206] Exiting Vivado at Tue Apr 16 02:07:28 2024...
Info: 77000 | 11524 65475 | 183 817 | 42042| 0.52 32.45|
[Pipeline] }
Info: 78000 | 11684 66315 | 160 840 | 41559| 0.36 32.80|
[Pipeline] // stage
[Pipeline] }
Info: 79000 | 11849 67150 | 165 835 | 41515| 0.43 33.23|
Info: 80000 | 12025 67974 | 176 824 | 41087| 0.42 33.65|
Info: 81000 | 12183 68816 | 158 842 | 40349| 0.33 33.98|
Info: 82000 | 12346 69653 | 163 837 | 40120| 0.33 34.31|
Info: 83000 | 12498 70501 | 152 848 | 39417| 0.32 34.63|
Info: 84000 | 12702 71297 | 204 796 | 38819| 0.39 35.02|
Info: 85000 | 12891 72108 | 189 811 | 38285| 0.40 35.42|
Info: 86000 | 13034 72965 | 143 857 | 37884| 0.40 35.82|
Info: 87000 | 13294 73705 | 260 740 | 37386| 0.35 36.17|
Info: 88000 | 13446 74553 | 152 848 | 36936| 0.35 36.52|
Info: 89000 | 13652 75347 | 206 794 | 36585| 0.48 37.00|
Info: 90000 | 13880 76119 | 228 772 | 36009| 0.36 37.36|
Info: 91000 | 14078 76921 | 198 802 | 36009| 0.42 37.78|
Info: 92000 | 14119 77880 | 41 959 | 37126| 0.58 38.36|
Info: 93000 | 14138 78861 | 19 981 | 36160| 0.50 38.87|
Info: 94000 | 14216 79783 | 78 922 | 35949| 0.43 39.29|
Info: 95000 | 14370 80629 | 154 846 | 35583| 0.43 39.73|
Info: 96000 | 14635 81364 | 265 735 | 35070| 0.37 40.09|
Info: 97000 | 14845 82154 | 210 790 | 34729| 0.42 40.51|
Info: 98000 | 15049 82950 | 204 796 | 34288| 0.45 40.96|
Info: 99000 | 15335 83664 | 286 714 | 33778| 0.40 41.36|
Info: 100000 | 15598 84401 | 263 737 | 33359| 0.39 41.74|
Info: 101000 | 15924 85075 | 326 674 | 32825| 0.41 42.16|
Info: 102000 | 16304 85695 | 380 620 | 32398| 0.43 42.59|
Info: 103000 | 16664 86335 | 360 640 | 34048| 0.42 43.01|
Info: 104000 | 16735 87264 | 71 929 | 33362| 0.48 43.50|
Info: 105000 | 16791 88208 | 56 944 | 32779| 0.37 43.87|
Info: 106000 | 16920 89079 | 129 871 | 32396| 0.39 44.26|
Info: 107000 | 17075 89924 | 155 845 | 31941| 0.37 44.63|
Info: 108000 | 17435 90564 | 360 640 | 31520| 0.48 45.11|
Info: 109000 | 17824 91175 | 389 611 | 31121| 0.44 45.55|
Info: 110000 | 18244 91755 | 420 580 | 30733| 0.44 45.99|
Info: 111000 | 18574 92425 | 330 670 | 30642| 0.44 46.43|
Info: 112000 | 18960 93039 | 386 614 | 30432| 0.42 46.85|
Info: 113000 | 19337 93662 | 377 623 | 30072| 0.45 47.30|
Info: 114000 | 19730 94269 | 393 607 | 29705| 0.43 47.73|
Info: 115000 | 20109 94890 | 379 621 | 29367| 0.44 48.17|
Info: 116000 | 20518 95481 | 409 591 | 29042| 0.45 48.62|
Info: 117000 | 20934 96065 | 416 584 | 28732| 0.49 49.11|
Info: 118000 | 21365 96634 | 431 569 | 28414| 0.47 49.58|
Info: 119000 | 21646 97353 | 281 719 | 29412| 0.48 50.05|
Info: 120000 | 21778 98221 | 132 868 | 29020| 0.48 50.54|
Info: 121000 | 21881 99118 | 103 897 | 28365| 0.57 51.10|
Info: 122000 | 22270 99729 | 389 611 | 28218| 0.51 51.61|
Info: 123000 | 22626 100373 | 356 644 | 27838| 0.43 52.04|
Info: 124000 | 23029 100970 | 403 597 | 27618| 0.47 52.51|
Info: 125000 | 23521 101478 | 492 508 | 27422| 0.46 52.97|
Info: 126000 | 23956 102043 | 435 565 | 27335| 0.48 53.45|
Info: 127000 | 24343 102656 | 387 613 | 27109| 0.47 53.92|
Info: 128000 | 24834 103165 | 491 509 | 26868| 0.47 54.40|
Info: 129000 | 25337 103662 | 503 497 | 26556| 0.47 54.87|
Info: 130000 | 25830 104169 | 493 507 | 26272| 0.45 55.32|
Info: 131000 | 26227 104772 | 397 603 | 26006| 0.43 55.75|
Info: 132000 | 26715 105284 | 488 512 | 25656| 0.42 56.17|
Info: 133000 | 27248 105751 | 533 467 | 25347| 0.47 56.64|
Info: 134000 | 27750 106249 | 502 498 | 25043| 0.46 57.10|
Info: 135000 | 28232 106767 | 482 518 | 24757| 0.46 57.56|
Info: 136000 | 28750 107249 | 518 482 | 24402| 0.44 58.00|
Info: 137000 | 29227 107772 | 477 523 | 24038| 0.43 58.42|
Info: 138000 | 29700 108286 | 473 514 | 23682| 0.49 58.91|
Info: 139000 | 30119 108836 | 419 550 | 23306| 0.44 59.36|
Info: 140000 | 30575 109362 | 456 526 | 22994| 0.48 59.84|
Info: 141000 | 30953 109933 | 378 571 | 22497| 0.36 60.20|
Info: 142000 | 31210 110640 | 257 707 | 26270| 0.35 60.54|
Info: 143000 | 31378 111472 | 168 832 | 26378| 0.50 61.04|
Info: 144000 | 31571 112279 | 193 807 | 26262| 0.56 61.61|
Info: 145000 | 31757 113093 | 186 814 | 25967| 0.63 62.23|
Info: 146000 | 31965 113885 | 208 792 | 25748| 0.59 62.82|
Info: 147000 | 32079 114771 | 114 886 | 25560| 0.50 63.32|
Info: 148000 | 32255 115595 | 176 824 | 25373| 0.60 63.92|
Info: 149000 | 32389 116461 | 134 866 | 24881| 0.62 64.54|
Info: 150000 | 32556 117294 | 167 833 | 24372| 0.49 65.03|
Info: 151000 | 32713 118137 | 157 843 | 24601| 0.53 65.55|
Info: 152000 | 32839 119011 | 126 874 | 24199| 0.50 66.06|
Info: 153000 | 32975 119875 | 136 864 | 23679| 0.48 66.54|
Info: 154000 | 33105 120745 | 130 870 | 22990| 0.49 67.03|
Info: 155000 | 33336 121514 | 231 769 | 22396| 0.63 67.66|
Info: 156000 | 33610 122240 | 274 726 | 22304| 0.54 68.20|
Info: 157000 | 33953 122897 | 343 657 | 22251| 0.50 68.70|
Info: 158000 | 34205 123630 | 252 733 | 21717| 0.40 69.11|
Info: 159000 | 34482 124299 | 277 669 | 21149| 0.32 69.42|
Info: 160000 | 34769 124922 | 287 623 | 20563| 0.35 69.77|
Info: 161000 | 35059 125541 | 290 619 | 19932| 0.31 70.08|
Info: 162000 | 35430 126060 | 371 519 | 19378| 0.36 70.44|
Info: 163000 | 35806 126579 | 376 519 | 18852| 0.36 70.79|
Info: 164000 | 36191 127087 | 385 508 | 18311| 0.36 71.16|
Info: 165000 | 36596 127602 | 405 515 | 17809| 0.39 71.55|
Info: 166000 | 37013 128078 | 417 476 | 17287| 0.40 71.94|
Info: 167000 | 37449 128534 | 436 456 | 16782| 0.41 72.35|
Info: 168000 | 37885 128978 | 436 444 | 16286| 0.43 72.78|
Info: 169000 | 38260 129523 | 375 545 | 15983| 0.48 73.26|
Info: 170000 | 38675 130060 | 415 537 | 15748| 0.55 73.80|
Info: 171000 | 39048 130572 | 373 512 | 15161| 0.38 74.18|
Info: 172000 | 39341 131146 | 293 574 | 14491| 0.34 74.52|
Info: 173000 | 39464 131953 | 123 807 | 13622| 0.23 74.76|
Info: 174000 | 39487 132918 | 23 965 | 12646| 0.17 74.93|
Info: 175000 | 39504 133898 | 17 980 | 11663| 0.16 75.08|
Info: 176000 | 39520 134880 | 16 982 | 10680| 0.15 75.23|
Info: 177000 | 39531 135868 | 11 988 | 9691| 0.16 75.39|
Info: 178000 | 39534 136864 | 3 996 | 8696| 0.16 75.56|
Info: 179000 | 39556 137841 | 22 977 | 7721| 0.18 75.74|
Info: 180000 | 39567 138828 | 11 987 | 6733| 0.18 75.91|
Info: 181000 | 39594 139801 | 27 973 | 5773| 0.19 76.11|
Info: 182000 | 39605 140788 | 11 987 | 4784| 0.16 76.27|
Info: 183000 | 39634 141752 | 29 964 | 3816| 0.17 76.44|
Info: 184000 | 39711 142635 | 77 883 | 2906| 0.24 76.68|
Info: 185000 | 39842 143484 | 131 849 | 2054| 0.33 77.01|
Info: 186000 | 40013 144206 | 171 722 | 1285| 0.39 77.40|
Info: 187000 | 40110 144892 | 97 686 | 429| 0.35 77.75|
Info: 187503 | 40136 145139 | 26 247 | 0| 0.28 78.03|
Info: Routing complete.
Info: Router1 time 78.03s
Info: Checksum: 0x3901d9ae
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q.Q
Info: 0.9 1.4 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_B_LUT4_Z_1_C_LUT4_C_Z_LUT4_Z_1_C_LUT4_Z_D[0] (22,6) -> (23,5)
Info: Sink SOC.Core.Control_Unit.save_address_LUT4_Z_D_LUT4_Z_B_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 1.7 Source SOC.Core.Control_Unit.save_address_LUT4_Z_D_LUT4_Z_B_LUT4_Z.F
Info: 1.6 3.2 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_A_LUT4_C_Z_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z[1] (23,5) -> (28,9)
Info: Sink SOC.Core.Control_Unit.save_address_LUT4_Z_D_LUT4_Z_B_PFUMX_C0_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 3.5 Source SOC.Core.Control_Unit.save_address_LUT4_Z_D_LUT4_Z_B_PFUMX_C0_BLUT_LUT4_Z.OFX
Info: 2.5 6.0 Net SOC.Core.read_data_PFUMX_Z_13_C0[2] (28,9) -> (40,30)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 6.2 Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 1.2 7.4 Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (40,30) -> (41,26)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.B
Info: 0.4 7.8 Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 7.8 Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (41,26) -> (41,26)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.9 Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 7.9 Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (41,26) -> (41,26)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 7.9 Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 7.9 Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (41,26) -> (41,26)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.0 Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 8.0 Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (41,26) -> (41,26)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 8.0 Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 8.0 Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (41,26) -> (42,26)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.1 Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 8.1 Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (42,26) -> (42,26)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 8.1 Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 8.1 Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1_CIN (42,26) -> (42,26)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.1 Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 8.1 Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (42,26) -> (42,26)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 8.1 Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 8.1 Net $nextpnr_CCU2C_7$CIN (42,26) -> (42,26)
Info: Sink $nextpnr_CCU2C_7$CCU2_COMB0.FCI
Info: 0.4 8.6 Source $nextpnr_CCU2C_7$CCU2_COMB0.F
Info: 1.1 9.7 Net SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1_COUT (42,26) -> (41,30)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B1_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 9.9 Source SOC.Uart.RX_FIFO.memory.0.0_DO_2_LUT4_Z_2_D_CCU2C_COUT_B1_LUT4_C.F
Info: 1.6 11.5 Net SOC.Memory.address_LUT4_Z_1_C[1] (41,30) -> (21,31)
Info: Sink SOC.Memory.address_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 11.7 Source SOC.Memory.address_LUT4_Z_2.F
Info: 3.8 15.5 Net SOC.slave_address[3] (21,31) -> (64,40)
Info: Sink SOC.Memory.memory.0.831$DPRAM_COMB3.B
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.5-22.18
Info: 0.2 15.7 Source SOC.Memory.memory.0.831$DPRAM_COMB3.F
Info: 1.1 16.9 Net SOC.Memory.memory.0.815_DO[2] (64,40) -> (63,41)
Info: Sink SOC.Memory.memory.0.775_DO_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 17.1 Source SOC.Memory.memory.0.775_DO_LUT4_Z.F
Info: 0.7 17.8 Net SOC.Memory.memory.0.775_DO[4] (63,41) -> (65,41)
Info: Sink SOC.Memory.memory.0.799_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 18.0 Source SOC.Memory.memory.0.799_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.2 18.2 Net SOC.Memory.memory.0.799_DO_LUT4_A_Z[3] (65,41) -> (65,41)
Info: Sink SOC.Memory.memory.0.799_DO_LUT4_A_Z_LUT4_B.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 18.4 Source SOC.Memory.memory.0.799_DO_LUT4_A_Z_LUT4_B.F
Info: 1.3 19.8 Net SOC.Memory.memory.0.799_DO_LUT4_A_Z_LUT4_B_Z[2] (65,41) -> (60,37)
Info: Sink SOC.Memory.memory.0.839_DO_LUT4_B_Z_LUT4_B_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 20.0 Source SOC.Memory.memory.0.839_DO_LUT4_B_Z_LUT4_B_Z_LUT4_Z.F
Info: 0.6 20.6 Net SOC.Memory.memory.0.839_DO_LUT4_B_Z_LUT4_B_Z[3] (60,37) -> (58,37)
Info: Sink SOC.Memory.memory.0.839_DO_LUT4_B_Z_LUT4_B_Z_LUT4_B.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 20.8 Source SOC.Memory.memory.0.839_DO_LUT4_B_Z_LUT4_B_Z_LUT4_B.F
Info: 1.1 21.9 Net SOC.Memory.memory.0.79_DO_LUT4_C_Z_LUT4_B_Z_LUT4_B_Z[4] (58,37) -> (56,33)
Info: Sink SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 22.2 Source SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 22.2 Net SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 (56,33) -> (56,33)
Info: Sink SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64
Info: 0.2 22.4 Source SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 22.4 Net SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1 (56,33) -> (56,33)
Info: Sink SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 22.7 Source SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.9 24.6 Net SOC.Memory.memory.0.595_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B_Z_LUT4_B_Z[4] (56,33) -> (29,33)
Info: Sink SOC.Core.read_data_PFUMX_Z_20_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 24.8 Source SOC.Core.read_data_PFUMX_Z_20_BLUT_LUT4_Z.OFX
Info: 1.9 26.7 Net SOC.read_data[31] (29,33) -> (29,12)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:21.34-21.43
Info: 0.0 26.7 Setup SOC.Core.instruction_register_TRELLIS_FF_Q.M
Info: 5.4 ns logic, 21.4 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source rx$tr_io.O
Info: 2.3 2.3 Net rx$TRELLIS_IO_IN (90,20) -> (66,16)
Info: Sink SOC.Uart.i_uart_rx.rxd_reg_0_TRELLIS_FF_Q.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:4.16-4.18
Info: 0.0 2.3 Setup SOC.Uart.i_uart_rx.rxd_reg_0_TRELLIS_FF_Q.M
Info: 0.0 ns logic, 2.3 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info: 1.7 2.3 Net SOC.Core.read_data_LUT4_Z_2_C[0] (48,7) -> (70,7)
Info: Sink led_LUT4_Z_5.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: 0.2 2.5 Source led_LUT4_Z_5.F
Info: 3.8 6.3 Net led[2]$TRELLIS_IO_OUT (70,7) -> (90,44)
Info: Sink led[2]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.5 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 37.40 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 2.27 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.31 ns
Info: Slack histogram:
Info: legend: * represents 174 endpoint(s)
Info: + represents [1,174) endpoint(s)
Info: [ 13260, 14550) |+
Info: [ 14550, 15840) |**+
Info: [ 15840, 17130) |*****+
Info: [ 17130, 18420) |****+
Info: [ 18420, 19710) |+
Info: [ 19710, 21000) |+
Info: [ 21000, 22290) |********+
Info: [ 22290, 23580) |*************+
Info: [ 23580, 24870) |****************+
Info: [ 24870, 26160) |************************************************************
Info: [ 26160, 27450) |*********************************+
Info: [ 27450, 28740) |**+
Info: [ 28740, 30030) |****+
Info: [ 30030, 31320) |+
Info: [ 31320, 32610) |+
Info: [ 32610, 33900) |+
Info: [ 33900, 35190) |**+
Info: [ 35190, 36480) |*+
Info: [ 36480, 37770) |+
Info: [ 37770, 39060) |*+
Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
FPGA TangNano Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
[Pipeline] }
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Open file DONE
Parse file DONE
load program
Lock released on resource [tangnano20k]
[Pipeline] // lock
Loading: [==== ] 7.59%[Pipeline] }
[Pipeline] // script
[Pipeline] }
Load SRAM: [========= ] 18.00%[Pipeline] // stage
[Pipeline] }
Loading: [======== ] 15.19%
Load SRAM: [=================== ] 38.00%
Loading: [============ ] 22.78%
Load SRAM: [============================= ] 58.00%
Loading: [================ ] 30.38%
Load SRAM: [======================================= ] 78.00%
Loading: [=================== ] 37.97%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
[Pipeline] }
Loading: [======================= ] 45.56%Lock released on resource [nexys4]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Loading: [=========================== ] 53.16%
Loading: [=============================== ] 60.75%
Loading: [=================================== ] 68.35%
Loading: [====================================== ] 75.94%
Loading: [========================================== ] 83.53%
Loading: [============================================== ] 91.13%
Loading: [==================================================] 98.72%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
[Pipeline] }
+ echo testando na tang nano
testando na tang nano
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
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