Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1454:
Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1454_Y
New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1454_Y [0]
New connections: $flatten\SOC.\Memory.$procmux$1454_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] }
Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1481:
Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1481_Y
New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1481_Y [0]
New connections: $flatten\SOC.\Memory.$procmux$1481_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] }
Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1508:
Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1508_Y
New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1508_Y [0]
New connections: $flatten\SOC.\Memory.$procmux$1508_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] }
New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2030: { $flatten\SOC.\Core.\Control_Unit.$procmux$2027_CMP $auto$opt_reduce.cc:134:opt_pmux$3560 }
Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y
New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0]
New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] }
Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y
New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0]
New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] }
Optimizing cells in module \top.
Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1684:
Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$160, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149
New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0]
New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] }
Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1687:
Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$159, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148
New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0]
New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] }
Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1526:
Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$976, B=0, Y=$flatten\SOC.\Memory.$procmux$1526_Y
New ports: A=$flatten\SOC.\Memory.$procmux$1481_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1526_Y [0]
New connections: $flatten\SOC.\Memory.$procmux$1526_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] }
Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1544:
Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$973, B=0, Y=$flatten\SOC.\Memory.$procmux$1544_Y
New ports: A=$flatten\SOC.\Memory.$procmux$1454_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1544_Y [0]
New connections: $flatten\SOC.\Memory.$procmux$1544_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] }
Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1579:
Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$963, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943
New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1508_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0]
New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] }
Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1117:
Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$902, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893
New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0]
New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] }
Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1117:
Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$902, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893
New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0]
New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] }
Optimizing cells in module \top.
Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1561:
Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$969, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949
New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1526_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0]
New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] }
Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1570:
Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$966, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946
New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1544_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0]
New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] }
Optimizing cells in module \top.
Performed a total of 44 changes.
22.11.5. Executing OPT_MERGE pass (detect identical cells).
+ mkdir -p Risco-5/impl/pnr
[Pipeline] sh
Finding identical cells in module `\top'.
<suppressed ~21 debug messages>
Removed a total of 7 cells.
22.11.6. Executing OPT_DFF pass (perform DFF optimizations).
22.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 366 unused wires.
<suppressed ~3 debug messages>
22.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
22.11.9. Rerunning OPT passes. (Maybe there is more to do..)
22.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~145 debug messages>
22.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2268: { $flatten\SOC.\Core.\Control_Unit.$procmux$2261_CMP $auto$opt_reduce.cc:134:opt_pmux$3520 $auto$opt_reduce.cc:134:opt_pmux$3518 $auto$opt_reduce.cc:134:opt_pmux$3516 $flatten\SOC.\Core.\Control_Unit.$procmux$2183_CMP $auto$opt_reduce.cc:134:opt_pmux$3514 $auto$opt_reduce.cc:134:opt_pmux$3564 $auto$opt_reduce.cc:134:opt_pmux$3562 $auto$opt_reduce.cc:134:opt_pmux$3512 $auto$opt_reduce.cc:134:opt_pmux$3510 $auto$opt_reduce.cc:134:opt_pmux$3508 }
Optimizing cells in module \top.
Performed a total of 1 changes.
22.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
22.11.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 1-bit at position 0 on $flatten\SOC.\Core.\Control_Unit.$auto$proc_dlatch.cc:433:proc_dlatch$3301 ($dlatch) from module top.
22.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Warning: Driver-driver conflict for \SOC.Core.Control_Unit.pc_write between cell $flatten\SOC.\Core.\Control_Unit.$procmux$3192.Y and constant 1'1 in top: Resolved using constant.
Removed 5 unused cells and 4 unused wires.
<suppressed ~6 debug messages>
22.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~4 debug messages>
22.11.16. Rerunning OPT passes. (Maybe there is more to do..)
22.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~144 debug messages>
22.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
22.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.
22.11.20. Executing OPT_DFF pass (perform DFF optimizations).
22.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 4 unused cells and 10 unused wires.
<suppressed ~10 debug messages>
22.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
22.11.23. Rerunning OPT passes. (Maybe there is more to do..)
22.11.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~141 debug messages>
22.11.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
22.11.26. Executing OPT_MERGE pass (detect identical cells).
+ cd Risco-5/fpga/tangnano20k/
+ /eda/gowin/IDE/bin/gw_sh run.tcl
*** GOWIN Tcl Command Line Console ***
current device: GW2AR-18C GW2AR-LV18QN88C8/I7
add new file: "pinout.cst"
add new file: "top.sdc"
add new file: "main.v"
add new file: "../../debug/reset.v"
add new file: "../../src/core/alu_control.v"
add new file: "../../src/core/alu.v"
add new file: "../../src/core/control_unit.v"
add new file: "../../src/core/core.v"
add new file: "../../src/core/immediate_generator.v"
add new file: "../../src/core/mux.v"
add new file: "../../src/core/pc.v"
add new file: "../../src/core/registers.v"
add new file: "../../src/core/csr_unit.v"
add new file: "../../src/peripheral/bus.v"
add new file: "../../src/peripheral/gpio.v"
add new file: "../../src/peripheral/gpios.v"
add new file: "../../src/peripheral/leds.v"
add new file: "../../src/peripheral/memory.v"
add new file: "../../src/peripheral/soc.v"
add new file: "../../src/peripheral/uart_rx.v"
add new file: "../../src/peripheral/uart_tx.v"
add new file: "../../src/peripheral/uart.v"
add new file: "../../src/peripheral/fifo.v"
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v'
Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":142)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v'
WARN (EX3801) : Parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":17)
WARN (EX3801) : Parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":18)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v'
WARN (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":40)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v'
WARN (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18)
Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1)
Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1)
WARN (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37)
Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/fpga_test_3.hex")'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1)
WARN (EX3073) : Port 'interrupt_on_hold' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":242)
Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":1)
Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1)
Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1)
Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1)
Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1)
WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":511)
WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":518)
WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":531)
WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":538)
WARN (EX2420) : Latch inferred for net 'pc_write'; We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":620)
ERROR (EX2000) : Net 'pc_write' is constantly driven from multiple places("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":620)
ERROR (EX1999) : Found another driver here("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":304)
Module 'Control_Unit' remains a black box due to errors in its contents("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1)
Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1)
WARN (EX2420) : Latch inferred for net 'aluop_out[3]'; We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":57)
Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1)
Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1)
Compiling module 'CSR_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1)
WARN (EX3780) : Using initial value of 'csr_utime' since it is never assigned("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":114)
WARN (EX2565) : Input 'save_pc' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":242)
Compiling module 'Memory(MEMORY_FILE="../../software/memory/fpga_test_3.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":15)
Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1)
Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1)
WARN (EX3791) : Expression size 33 truncated to fit in target size 32("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":21)
Compiling module 'UART(CLOCK_FREQ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1)
Finding identical cells in module `\top'.
Removed a total of 0 cells.
22.11.27. Executing OPT_DFF pass (perform DFF optimizations).
22.11.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
22.11.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
22.11.30. Finished OPT passes. (There is nothing left to do.)
22.12. Executing FSM pass (extract and optimize FSM).
22.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
Register has an initialization value.
Circuit seems to be self-resetting.
Not marking top.SOC.Core.CSR_Unit.csr_mip_mfip as FSM state register:
Users of register don't seem to benefit from recoding.
Register has an initialization value.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state.
Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register:
Users of register don't seem to benefit from recoding.
22.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'.
found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$3355
root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0]
found reset state: 3'000 (guessed from mux tree)
found ctrl input: \ResetBootSystem.reset_o
found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1036_Y
found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1051_Y
found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1064_Y
found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1050_Y
found state code: 3'000
found ctrl input: \SOC.Uart.i_uart_rx.next_bit
found state code: 3'011
found ctrl input: \SOC.Uart.i_uart_rx.payload_done
found state code: 3'010
found state code: 3'001
found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg
found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1064_Y
found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$1055_Y
found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1051_Y
found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1050_Y
found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1036_Y
ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o }
ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1036_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1050_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1051_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$1055_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1064_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
transition: 3'000 4'0--0 -> 3'001 8'01010001
transition: 3'000 4'1--0 -> 3'000 8'01010000
transition: 3'000 4'---1 -> 3'000 8'01010000
transition: 3'010 4'--00 -> 3'010 8'00100010
transition: 3'010 4'--10 -> 3'011 8'00100011
transition: 3'010 4'---1 -> 3'000 8'00100000
transition: 3'001 4'-0-0 -> 3'001 8'00011001
transition: 3'001 4'-1-0 -> 3'010 8'00011010
transition: 3'001 4'---1 -> 3'000 8'00011000
transition: 3'011 4'-0-0 -> 3'011 8'10010011
transition: 3'011 4'-1-0 -> 3'000 8'10010000
transition: 3'011 4'---1 -> 3'000 8'10010000
22.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3565' from module `\top'.
22.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 7 unused cells and 7 unused wires.
<suppressed ~8 debug messages>
22.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3565' from module `\top'.
Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].
22.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3565' from module `\top' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
000 -> ---1
010 -> --1-
001 -> -1--
011 -> 1---
22.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3565' from module `top':
-------------------------------------
Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$3565 (\SOC.Uart.i_uart_rx.fsm_state):
Number of input signals: 4
Number of output signals: 5
Number of state bits: 4
Input signals:
0: \ResetBootSystem.reset_o
1: \SOC.Uart.i_uart_rx.payload_done
2: \SOC.Uart.i_uart_rx.next_bit
3: \SOC.Uart.i_uart_rx.rxd_reg
Output signals:
0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1064_Y
1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$1055_Y
2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1051_Y
3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1050_Y
4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1036_Y
State encoding:
0: 4'---1 <RESET STATE>
1: 4'--1-
2: 4'-1--
3: 4'1---
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 4'1--0 -> 0 5'01010
1: 0 4'---1 -> 0 5'01010
2: 0 4'0--0 -> 2 5'01010
3: 1 4'---1 -> 0 5'00100
4: 1 4'--00 -> 1 5'00100
5: 1 4'--10 -> 3 5'00100
6: 2 4'---1 -> 0 5'00011
7: 2 4'-1-0 -> 1 5'00011
8: 2 4'-0-0 -> 2 5'00011
9: 3 4'-1-0 -> 0 5'10010
10: 3 4'---1 -> 0 5'10010
11: 3 4'-0-0 -> 3 5'10010
-------------------------------------
22.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3565' from module `\top'.
22.13. Executing OPT pass (performing simple optimizations).
22.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>
22.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.
22.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~140 debug messages>
22.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
22.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
22.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3367 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1383_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1377_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1368_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1359_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1350_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1341_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1323_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1332_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3615 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$3615 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1377_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1368_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1359_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1350_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1341_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1323_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1332_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3365 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1299_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3620 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1299_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3364 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1288_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3626 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1018_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3363 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3362 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1277_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$3631 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1277_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3361 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1266_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3637 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3360 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1243_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1234_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1225_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1216_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1207_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1198_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1180_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1189_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3639 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3358 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1162_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3643 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1058_Y, Q = \SOC.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3357 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1157_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3647 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3356 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1149_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3649 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1069_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3354 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3353 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3349 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1126_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3655 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$905_Y, Q = \SOC.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3348 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1131_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3657 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$910_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3349 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1126_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3659 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$905_Y, Q = \SOC.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3348 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1131_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3661 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$910_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3396 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1622_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3663 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3395 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1627_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3665 ($sdff) from module top (D = \SOC.Uart.write_data [7:0], Q = \SOC.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3394 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1632_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3667 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3392 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1597_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3391 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1602_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3390 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1607_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3388 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1612_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$3387 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1587_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3673 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3398 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1643_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3675 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3397 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1651_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3679 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$3404 ($dff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$3425 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 6'000000).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3421 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1803_Y, Q = \SOC.Core.CSR_Unit.csr_mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3687 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mtval).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3420 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 1'0 \SOC.Core.CSR_Unit.csr_write_data [0] }, Q = \SOC.Core.CSR_Unit.csr_mtvec).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3419 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1829_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$3696 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3418 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1846_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3700 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mstatus_mie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3417 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1862_Y, Q = \SOC.Core.CSR_Unit.csr_mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3704 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mscratch).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3416 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1875_Y, Q = \SOC.Core.CSR_Unit.csr_minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3708 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1875_Y, Q = \SOC.Core.CSR_Unit.csr_minstret).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3415 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1893_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mtie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3712 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mie_mtie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3414 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1911_Y, Q = \SOC.Core.CSR_Unit.csr_mie_msie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3716 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mie_msie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3413 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1929_Y, Q = \SOC.Core.CSR_Unit.csr_mie_meie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3720 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [11], Q = \SOC.Core.CSR_Unit.csr_mie_meie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3412 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1947_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mfie, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3724 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [31:16], Q = \SOC.Core.CSR_Unit.csr_mie_mfie).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3411 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.csr_mepc).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3410 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1970_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3733 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1970_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3409 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1981_Y, Q = \SOC.Core.CSR_Unit.csr_mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3737 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mcause).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3408 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_software, Q = \SOC.Core.CSR_Unit.csr_mip_msip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3407 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_timer, Q = \SOC.Core.CSR_Unit.csr_mip_mtip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3406 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_external, Q = \SOC.Core.CSR_Unit.csr_mip_meip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3405 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_fast, Q = \SOC.Core.CSR_Unit.csr_mip_mfip, rval = 16'0000000000000000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3377 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1415_Y, Q = \SOC.Core.temp_write_value, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3745 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_write_value).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3376 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1420_Y, Q = \SOC.Core.temp_reg3, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3747 ($sdff) from module top (D = \SOC.Core.alu_out_register, Q = \SOC.Core.temp_reg3).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3375 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1425_Y, Q = \SOC.Core.temp_reg2, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3749 ($sdff) from module top (D = \SOC.Core.instruction_register, Q = \SOC.Core.temp_reg2).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3374 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1430_Y, Q = \SOC.Core.temp_address, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3751 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_address).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3373 ($dff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3372 ($dff) from module top (D = \SOC.Core.register_data_2_out, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3371 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3370 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3368 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3424 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3423 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3422 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3728 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3728 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3691 ($dffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$3674 ($sdffe) from module top.
22.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 134 unused cells and 130 unused wires.
<suppressed ~135 debug messages>
22.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>
22.13.9. Rerunning OPT passes. (Maybe there is more to do..)
22.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~96 debug messages>
22.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$3645: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o }
Optimizing cells in module \top.
Performed a total of 1 changes.
22.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.
22.13.13. Executing OPT_DFF pass (perform DFF optimizations).
Compiling module 'FIFO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":15)
WARN (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":35)
Compiling module 'uart_tool_rx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":10)
Compiling module 'uart_tool_tx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":10)
Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1)
Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1)
WARN (EX2565) : Input 'halt' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN (EX2565) : Input 'instruction_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
GowinSynthesis finish
while executing
"run all"
(file "run.tcl" line 30)
22.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 6 unused wires.
<suppressed ~2 debug messages>
22.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
22.13.16. Rerunning OPT passes. (Maybe there is more to do..)
22.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~96 debug messages>
22.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
22.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
22.13.20. Executing OPT_DFF pass (perform DFF optimizations).
22.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
22.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
22.13.23. Finished OPT passes. (There is nothing left to do.)
22.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3430 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3432 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:17$161 (SOC.Core.RegisterBank.registers).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3427 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3428 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3429 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$978 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$938 (SOC.Memory.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3426 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$889 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3426 (SOC.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$889 (SOC.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1998_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$682 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$681 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$681 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$680 ($lt).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3769 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3764 ($ne).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$913 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1594_CMP0 ($eq).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$procmux$1593 ($pmux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1123 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1111 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$910 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$903 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$885 ($eq).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1123 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1111 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$910 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$903 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$885 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$1047 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$1046 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$1045 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$1044 ($mux).
Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:111$1039 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:109$1037 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$1013 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$1005 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$1003 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$1000 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$999 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$995 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$990 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$989 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$988 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$987 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$983 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$981 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$285 ($mux).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$165 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$168 ($ge).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$169 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$172 ($ge).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$173 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$176 ($ge).
Removed top 22 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$177 ($le).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:75$207 ($mux).
Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:84$223 ($mux).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$237 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Memory.$procmux$1450_CMP0 ($eq).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1567 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1576 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1585 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1707_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1707_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1706_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1705_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1707_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1706_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1705_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1707_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1706_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1705_CMP0 ($eq).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2997 ($mux).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2946_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2945_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2944_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2941_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2940_CMP0 ($eq).
Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2937 ($pmux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2836 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2783 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2734 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2686 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2639 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2594 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2561 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2531 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2504 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2458 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2407 ($mux).
Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2357_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2333_CMP0 ($eq).
Removed top 5 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2266_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2261_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2256_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2242_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2240_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2239_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2238_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2236_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2235_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2232_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2231_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2230_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2229_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2226_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2225_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2220_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2190_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2189_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2185_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2184_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2162_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2161_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2139_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2138_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2137_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2121_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2088_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2087_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2086_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2030 ($pmux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2028_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2027_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:531$75 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:511$69 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:242$48 ($eq).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:170$35 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:101$32 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3286_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3268_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3267_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3266_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3254 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3299_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3298_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3297_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3296_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1785_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1772_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1771_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1770_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1769_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1768_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1767_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1766_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1765_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1764_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$121 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$119 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$118 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$164 ($ge).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1520 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1538 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1556 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1472 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1499 ($mux).
Removed top 19 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$215 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$681_Y.
Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$237_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25_Y.
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$11\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$12\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$13\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0].
Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$6\nextstate[5:0].
Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$7\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0].
Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$9\nextstate[5:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:511$69_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:531$75_Y.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_ADDR[31:0]$941.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_ADDR[31:0]$944.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_ADDR[31:0]$947.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_ADDR[31:0]$961.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_ADDR[31:0]$964.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_ADDR[31:0]$967.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_ADDR[31:0]$971.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_ADDR[31:0]$974.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_ADDR[5:0]$891.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_ADDR[5:0]$900.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$910_Y.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_ADDR[5:0]$891.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_ADDR[5:0]$900.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$910_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$1044_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$1045_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$1046_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$1047_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$987_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$988_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$989_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$990_Y.
22.15. Executing PEEPOPT pass (run peephole optimizers).
22.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 46 unused wires.
<suppressed ~1 debug messages>
22.17. Executing SHARE pass (SAT-based resource sharing).
Found 5 cells in module top that may be considered for resource sharing.
Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$889 ($memrd):
Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:57$174_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:55$170_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$166_Y $flatten\SOC.\Uart.$procmux$1596_CMP $flatten\SOC.\Uart.$procmux$1595_CMP $flatten\SOC.\Uart.$procmux$1594_CMP }.
No candidates found.
Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$938 ($memrd):
Found 7 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1451_CMP $flatten\SOC.\Memory.$procmux$1450_CMP $flatten\SOC.\Memory.$procmux$1449_CMP $flatten\SOC.\Memory.$procmux$1448_CMP \SOC.Memory.option [1:0] $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$166_Y \SOC.Bus.slave_0_write \SOC.Bus.slave_0_read }.
No candidates found.
Analyzing resource sharing options for $flatten\SOC.\Core.\RegisterBank.$memrd$\registers$Risco-5/src/core/registers.v:22$143 ($memrd):
Found 11 activation_patterns using ctrl signal { $flatten\SOC.\Core.\Alu.$procmux$3290_CMP $flatten\SOC.\Core.\Alu.$procmux$3291_CMP $flatten\SOC.\Core.\Alu.$procmux$3292_CMP $flatten\SOC.\Core.\Alu.$procmux$3293_CMP $flatten\SOC.\Core.\Alu.$procmux$3294_CMP $flatten\SOC.\Core.\Alu.$procmux$3295_CMP $flatten\SOC.\Core.\Alu.$procmux$3296_CMP $flatten\SOC.\Core.\Alu.$procmux$3297_CMP $flatten\SOC.\Core.\Alu.$procmux$3298_CMP $flatten\SOC.\Core.\Alu.$procmux$3299_CMP $flatten\SOC.\Core.\Alu.$procmux$3300_CMP $flatten\SOC.\Core.\AluInputBMUX.$procmux$1705_CMP }.
No candidates found.
Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:44$23 ($shr):
Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3291_CMP.
No candidates found.
Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:42$22 ($shl):
Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3292_CMP.
No candidates found.
22.18. Executing TECHMAP pass (map to technology primitives).
22.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
22.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~296 debug messages>
22.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
22.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
22.21. Executing TECHMAP pass (map to technology primitives).
22.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.
22.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.
22.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>
22.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$681 ($add).
creating $macc model for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$766 ($add).
creating $macc model for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$765 ($sub).
creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14 ($add).
creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15 ($sub).
creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$116 ($add).
creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$117 ($add).
creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$118 ($add).
creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$119 ($add).
creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$120 ($add).
creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$121 ($add).
creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$882 ($add).
creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$904 ($add).
creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909 ($add).
creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$882 ($add).
creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$904 ($add).
creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909 ($add).
creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1058 ($add).
creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1069 ($add).
creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$1007 ($add).
creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1018 ($add).
creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1018.
creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$1007.
creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1069.
creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1058.
creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909.
creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$904.
creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$882.
creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909.
creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$904.
creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$882.
creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$121.
creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$120.
creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$119.
creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$118.
creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$117.
creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$116.
creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14.
creating $alu model for $macc $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$765.
creating $alu model for $macc $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$766.
creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$681.
creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$680 ($lt): new $alu
creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$164 ($ge): new $alu
creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$168 ($ge): new $alu
creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$172 ($ge): new $alu
creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$176 ($ge): new $alu
creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$165 ($le): new $alu
creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$169 ($le): new $alu
creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$173 ($le): new $alu
creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$177 ($le): new $alu
creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$682 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$680.
creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$177: $auto$alumacc.cc:485:replace_alu$3839
creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$173: $auto$alumacc.cc:485:replace_alu$3852
creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$169: $auto$alumacc.cc:485:replace_alu$3865
creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$165: $auto$alumacc.cc:485:replace_alu$3878
creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$176: $auto$alumacc.cc:485:replace_alu$3891
creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$172: $auto$alumacc.cc:485:replace_alu$3900
creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$168: $auto$alumacc.cc:485:replace_alu$3909
creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$164: $auto$alumacc.cc:485:replace_alu$3918
creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$680, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$682: $auto$alumacc.cc:485:replace_alu$3927
creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$681: $auto$alumacc.cc:485:replace_alu$3938
creating $alu cell for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$766: $auto$alumacc.cc:485:replace_alu$3941
creating $alu cell for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$765: $auto$alumacc.cc:485:replace_alu$3944
creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14: $auto$alumacc.cc:485:replace_alu$3947
creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21: $auto$alumacc.cc:485:replace_alu$3950
creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$116: $auto$alumacc.cc:485:replace_alu$3963
creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$117: $auto$alumacc.cc:485:replace_alu$3966
creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$118: $auto$alumacc.cc:485:replace_alu$3969
creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$119: $auto$alumacc.cc:485:replace_alu$3972
creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$120: $auto$alumacc.cc:485:replace_alu$3975
creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$121: $auto$alumacc.cc:485:replace_alu$3978
creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$904: $auto$alumacc.cc:485:replace_alu$3981
creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$882: $auto$alumacc.cc:485:replace_alu$3984
creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909: $auto$alumacc.cc:485:replace_alu$3987
creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$904: $auto$alumacc.cc:485:replace_alu$3990
creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$882: $auto$alumacc.cc:485:replace_alu$3993
creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909: $auto$alumacc.cc:485:replace_alu$3996
creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1058: $auto$alumacc.cc:485:replace_alu$3999
creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1069: $auto$alumacc.cc:485:replace_alu$4002
creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$1007: $auto$alumacc.cc:485:replace_alu$4005
creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1018: $auto$alumacc.cc:485:replace_alu$4008
created 30 $alu and 0 $macc cells.
22.23. Executing OPT pass (performing simple optimizations).
22.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>
22.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~10 debug messages>
Removed a total of 2 cells.
22.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~96 debug messages>
22.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
22.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.
22.23.6. Executing OPT_DFF pass (perform DFF optimizations).
22.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 22 unused wires.
<suppressed ~1 debug messages>
22.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
22.23.9. Rerunning OPT passes. (Maybe there is more to do..)
22.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~96 debug messages>
22.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
22.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
22.23.13. Executing OPT_DFF pass (perform DFF optimizations).
22.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
22.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
22.23.16. Finished OPT passes. (There is nothing left to do.)
22.24. Executing MEMORY pass.
22.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
22.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.
22.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
Analyzing top.SOC.Core.RegisterBank.registers write port 0.
Analyzing top.SOC.Core.RegisterBank.registers write port 1.
Analyzing top.SOC.Core.RegisterBank.registers write port 2.
Analyzing top.SOC.Memory.memory write port 0.
Analyzing top.SOC.Memory.memory write port 1.
Analyzing top.SOC.Memory.memory write port 2.
Analyzing top.SOC.Uart.RX_FIFO.memory write port 0.
Analyzing top.SOC.Uart.TX_FIFO.memory write port 0.
22.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
22.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[2] in module `\top': merging output FF to cell.
Write port 0: don't care on collision.
Write port 1: non-transparent.
Write port 2: non-transparent.
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': FF found, but with a mux select that doesn't seem to correspond to transparency logic.
Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell.
Write port 0: non-transparent.
Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Core.RegisterBank.registers'[1] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.
Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': merged address FF to cell.
22.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 44 unused wires.
<suppressed ~7 debug messages>
22.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Memory.memory by address:
Merging ports 0, 1 (address \SOC.Memory.address [12:2]).
Merging ports 0, 2 (address \SOC.Memory.address [12:2]).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing:
Checking group clocked with posedge \clk, width 32: ports 0, 1.
Common input cone for all EN signals: 13 cells.
Size of unconstrained SAT problem: 103 variables, 281 clauses
Merging port 1 into port 0.
22.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
22.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
[Pipeline] }
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>
22.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).
22.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
22.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 2 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[2]
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted addr FF from read port 0 of top.SOC.Uart.RX_FIFO.memory: $\SOC.Uart.RX_FIFO.memory$rdreg[0]
mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0]
<suppressed ~1084 debug messages>
22.27. Executing TECHMAP pass (map to technology primitives).
22.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.
22.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
[Pipeline] // stage
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.
22.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$8e5e72577b4c3b167a98ad5915719acd6a2ff3f4\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$58f24e643e5858c811559272a02c6d84f974d8a6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b7ec8ee89a7cd4851359941621e9dedf8c3b7d83\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$6d2a7df30888468e46c2233cf858b33a106d24cc\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1a510b238205ce75968c294c5a2f9682007038e9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$d697ed060a7caa7345cbd011d88bf1d0e8cd46a0\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$882b16869816e01f56a454af0eb6e24b6778fa0c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b6fd6d9e43fa3d8e6bc64941b5b57ab422f7e603\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$983d377398e8a630797eecf765a80311ec60d100\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c8ec1437ade7762ec3882c3e3f576764a2f7bb09\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1de9eb29388171a23037c69580dd741dfa07544f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$ccbfc2f8b7417ea49ec4f806e284aeee31f607b3\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b1d6656f42d8fe2eb2a963373a2667cf617d2bc5\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$80ae742e83efa97f5ae3dddd041ab9a1ef9ac7b6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$9a18a5918aa94986c2ace7118a70e41127dc33df\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c4c009ae968ecf5722a8a929fbdc163f47dedcc6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$7e65f9170886a0570d9059c94eef599a8e7c0c53\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$88ca364434c15edf84547ebc10bbf93659adea39\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$219b7093d2a2ec9427a92a1f7d983c7335efd508\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$0f1e956af4a0dd7da6349454a915a33336b22174\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$20534e299f87b4db290b2588b7ce04615b91104c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$73e415998dfd4e0d8b84ec3ac6390921a6a2c53b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$7d81e3db939f1224434306a374696f893743b990\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$060a68a0493c8190183716105f9d8172975de01f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1419 debug messages>
22.28. Executing OPT pass (performing simple optimizations).
22.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~103 debug messages>
22.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~30 debug messages>
Removed a total of 10 cells.
22.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $\SOC.Uart.RX_FIFO.memory$rdreg[0] ($dff) from module top (D = $auto$rtlil.cc:2582:Mux$4062, Q = $\SOC.Uart.RX_FIFO.memory$rdreg[0]$q, rval = 3'000).
Adding SRST signal on $auto$ff.cc:266:slice$3758 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1995_Y, Q = \ResetBootSystem.counter, rval = 6'000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3741 ($sdff) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
22.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
[Pipeline] }
Failed in branch Gowin
Finding unused cells or wires in module \top..
Removed 19 unused cells and 7629 unused wires.
<suppressed ~20 debug messages>
22.28.5. Rerunning OPT passes. (Removed registers in this run.)
22.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
22.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
22.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$6550 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$3784 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).
22.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 1 unused wires.
<suppressed ~2 debug messages>
22.28.10. Rerunning OPT passes. (Removed registers in this run.)
22.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
22.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
22.28.13. Executing OPT_DFF pass (perform DFF optimizations).
22.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Sending interrupt signal to process
Sending interrupt signal to process
Finding unused cells or wires in module \top..
22.28.15. Finished fast OPT passes.
22.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
22.30. Executing OPT pass (performing simple optimizations).
22.30.1. Executing OPT_EXPR pass (perform const folding).
Terminated
script returned exit code 143
Terminated
script returned exit code 143
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch Vivado
[Pipeline] stage
[Pipeline] { (NextPNR)
Stage "NextPNR" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
Stage "ECPPACK" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch OSS-Cad-Suite
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
Stage "FPGA Flash" skipped due to earlier failure(s)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
Stage "openFPGAloader ECP5" skipped due to earlier failure(s)
[Pipeline] }
Stage "openFPGAloader Tangnano 20k" skipped due to earlier failure(s)
[Pipeline] }
Stage "openFPGAloader Nexys 4 DDR" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch openFPGAloader ECP5
[Pipeline] }
Failed in branch openFPGAloader Tangnano 20k
[Pipeline] }
Failed in branch openFPGAloader Nexys 4 DDR
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
Stage "Testes" skipped due to earlier failure(s)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
Stage "ECP5 - Testes" skipped due to earlier failure(s)
[Pipeline] }
Stage "TangNano - Testes" skipped due to earlier failure(s)
[Pipeline] }
Stage "Nexys 4 - Testes" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch ECP5 - Testes
[Pipeline] }
Failed in branch TangNano - Testes
[Pipeline] }
Failed in branch Nexys 4 - Testes
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE
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