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State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 2053 ; free virtual = 26167
---------------------------------------------------------------------------------
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Start RTL Component Statistics
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Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
3 Input 32 Bit Adders := 1
2 Input 11 Bit Adders := 2
2 Input 6 Bit Adders := 4
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
+---XORs :
2 Bit Wide XORs := 1
+---Registers :
33 Bit Registers := 1
32 Bit Registers := 48
16 Bit Registers := 2
11 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 1
4 Bit Registers := 2
1 Bit Registers := 19
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
46 Input 46 Bit Muxes := 1
2 Input 46 Bit Muxes := 17
11 Input 46 Bit Muxes := 1
3 Input 33 Bit Muxes := 1
2 Input 32 Bit Muxes := 35
8 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 13
16 Input 32 Bit Muxes := 1
6 Input 32 Bit Muxes := 1
2 Input 8 Bit Muxes := 3
5 Input 8 Bit Muxes := 1
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
46 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 1
8 Input 4 Bit Muxes := 1
23 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
4 Input 3 Bit Muxes := 2
46 Input 3 Bit Muxes := 3
10 Input 3 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 14
46 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 4
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 49
46 Input 1 Bit Muxes := 12
4 Input 1 Bit Muxes := 2
13 Input 1 Bit Muxes := 2
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Finished RTL Component Statistics
---------------------------------------------------------------------------------
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Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
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Finished Part Resource Summary
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Info: at iteration #8, type ALL: wirelen solved = 30431, spread = 59888, legal = 61354; time = 0.65s
Info: at iteration #9, type ALL: wirelen solved = 29550, spread = 61457, legal = 62811; time = 0.40s
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
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WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
Info: at iteration #10, type ALL: wirelen solved = 32697, spread = 60250, legal = 61407; time = 0.40s
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
Info: at iteration #11, type ALL: wirelen solved = 33684, spread = 58714, legal = 60218; time = 0.45s
Info: at iteration #12, type ALL: wirelen solved = 34958, spread = 56540, legal = 58186; time = 0.46s
Info: at iteration #13, type ALL: wirelen solved = 34950, spread = 57063, legal = 58599; time = 0.51s
Info: at iteration #14, type ALL: wirelen solved = 35677, spread = 57793, legal = 59369; time = 0.40s
Info: at iteration #15, type ALL: wirelen solved = 36995, spread = 57171, legal = 58542; time = 0.40s
Info: at iteration #16, type ALL: wirelen solved = 37639, spread = 56017, legal = 57446; time = 0.40s
Info: at iteration #17, type ALL: wirelen solved = 37632, spread = 55425, legal = 56777; time = 0.57s
Info: at iteration #18, type ALL: wirelen solved = 37670, spread = 55666, legal = 57061; time = 0.41s
Info: at iteration #19, type ALL: wirelen solved = 38213, spread = 56197, legal = 57620; time = 0.40s
Info: at iteration #20, type ALL: wirelen solved = 38942, spread = 55813, legal = 57193; time = 0.40s
Info: at iteration #21, type ALL: wirelen solved = 39393, spread = 55549, legal = 56885; time = 0.48s
Info: at iteration #22, type ALL: wirelen solved = 39320, spread = 53417, legal = 55274; time = 0.50s
Info: at iteration #23, type ALL: wirelen solved = 38176, spread = 54253, legal = 55715; time = 0.40s
Info: at iteration #24, type ALL: wirelen solved = 39128, spread = 54484, legal = 55781; time = 0.40s
Info: at iteration #25, type ALL: wirelen solved = 39725, spread = 54886, legal = 56215; time = 0.40s
Info: at iteration #26, type ALL: wirelen solved = 39569, spread = 53314, legal = 54940; time = 0.55s
Info: at iteration #27, type ALL: wirelen solved = 39277, spread = 53320, legal = 54981; time = 0.40s
Info: at iteration #28, type ALL: wirelen solved = 40208, spread = 53428, legal = 54905; time = 0.41s
Info: at iteration #29, type ALL: wirelen solved = 40367, spread = 52961, legal = 54558; time = 0.41s
Info: at iteration #30, type ALL: wirelen solved = 40439, spread = 53217, legal = 54808; time = 0.56s
Info: at iteration #31, type ALL: wirelen solved = 40927, spread = 53210, legal = 54679; time = 0.40s
Info: at iteration #32, type ALL: wirelen solved = 40860, spread = 53013, legal = 54449; time = 0.40s
Info: at iteration #33, type ALL: wirelen solved = 41453, spread = 52720, legal = 54273; time = 0.40s
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":226)
WARN (NL0002) : The module "MUX" instantiated to "MemoryAddressMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":100)
WARN (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":152)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
Info: at iteration #34, type ALL: wirelen solved = 40951, spread = 52813, legal = 54361; time = 0.44s
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 1950 ; free virtual = 26074
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Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
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Info: at iteration #35, type ALL: wirelen solved = 41553, spread = 52757, legal = 54288; time = 0.52s
Info: at iteration #36, type ALL: wirelen solved = 41332, spread = 52786, legal = 54300; time = 0.39s
Info: at iteration #37, type ALL: wirelen solved = 41633, spread = 52409, legal = 53965; time = 0.39s
Info: at iteration #38, type ALL: wirelen solved = 41241, spread = 52308, legal = 53818; time = 0.39s
Info: at iteration #39, type ALL: wirelen solved = 41401, spread = 52342, legal = 53814; time = 0.55s
Info: at iteration #40, type ALL: wirelen solved = 41599, spread = 52485, legal = 54023; time = 0.39s
Info: at iteration #41, type ALL: wirelen solved = 41599, spread = 52489, legal = 53976; time = 0.39s
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Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 1949 ; free virtual = 26073
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Start Timing Optimization
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Info: at iteration #42, type ALL: wirelen solved = 41973, spread = 52299, legal = 53672; time = 0.39s
Info: at iteration #43, type ALL: wirelen solved = 41947, spread = 52338, legal = 53918; time = 0.40s
[10%] Placement Phase 0 completed
Info: at iteration #44, type ALL: wirelen solved = 42085, spread = 52658, legal = 54122; time = 0.54s
[20%] Placement Phase 1 completed
Info: at iteration #45, type ALL: wirelen solved = 42267, spread = 52298, legal = 53852; time = 0.39s
Info: at iteration #46, type ALL: wirelen solved = 42117, spread = 52661, legal = 53961; time = 0.39s
Info: at iteration #47, type ALL: wirelen solved = 42365, spread = 52188, legal = 53611; time = 0.39s
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 1869 ; free virtual = 25993
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
Info: at iteration #48, type ALL: wirelen solved = 42317, spread = 52270, legal = 53559; time = 0.56s
Info: at iteration #49, type ALL: wirelen solved = 42693, spread = 52194, legal = 53551; time = 0.39s
Info: at iteration #50, type ALL: wirelen solved = 42693, spread = 52057, legal = 53513; time = 0.39s
Info: at iteration #51, type ALL: wirelen solved = 42781, spread = 54039, legal = 55366; time = 0.39s
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 1859 ; free virtual = 25983
---------------------------------------------------------------------------------
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Start IO Insertion
---------------------------------------------------------------------------------
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
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Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
Info: at iteration #52, type ALL: wirelen solved = 43983, spread = 53864, legal = 55466; time = 0.50s
Info: at iteration #53, type ALL: wirelen solved = 42966, spread = 52527, legal = 54338; time = 0.50s
Info: at iteration #54, type ALL: wirelen solved = 43589, spread = 52271, legal = 53899; time = 0.42s
Info: HeAP Placer Time: 36.03s
Info: of which solving equations: 20.54s
Info: of which spreading cells: 2.93s
Info: of which strict legalisation: 0.81s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 20362, wirelen = 53513
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:48 ; elapsed = 00:00:48 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 1746 ; free virtual = 25871
---------------------------------------------------------------------------------
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Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:48 ; elapsed = 00:00:48 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 1746 ; free virtual = 25871
---------------------------------------------------------------------------------
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Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 1746 ; free virtual = 25871
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 1746 ; free virtual = 25871
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 1746 ; free virtual = 25871
---------------------------------------------------------------------------------
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Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 1746 ; free virtual = 25871
---------------------------------------------------------------------------------
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Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 55|
|3 |LUT1 | 15|
|4 |LUT2 | 167|
|5 |LUT3 | 245|
|6 |LUT4 | 294|
|7 |LUT5 | 440|
|8 |LUT6 | 1451|
|9 |MUXF7 | 387|
|10 |MUXF8 | 28|
|11 |RAM256X1S | 64|
|12 |RAM32M | 2|
|13 |RAM32X1D | 4|
|14 |FDRE | 1871|
|15 |FDSE | 5|
|16 |LD | 4|
|17 |IBUF | 2|
|18 |OBUF | 9|
|19 |OBUFT | 8|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 1746 ; free virtual = 25871
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 44 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2282.410 ; gain = 510.496 ; free physical = 1746 ; free virtual = 25871
Synthesis Optimization Complete : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2282.410 ; gain = 658.281 ; free physical = 1746 ; free virtual = 25871
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2282.410 ; gain = 0.000 ; free physical = 2021 ; free virtual = 26145
INFO: [Netlist 29-17] Analyzing 544 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2354.406 ; gain = 0.000 ; free physical = 2008 ; free virtual = 26132
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 74 instances were transformed.
LD => LDCE: 4 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 9a768a6
INFO: [Common 17-83] Releasing license: Synthesis
75 Infos, 121 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:00:55 . Memory (MB): peak = 2354.441 ; gain = 1040.352 ; free physical = 2008 ; free virtual = 26132
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2020.647; main = 1756.556; forked = 422.855
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3220.016; main = 2354.410; forked = 969.652
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors, 8 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2418.438 ; gain = 63.996 ; free physical = 2007 ; free virtual = 26131
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1bbc9ccb5
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2522.250 ; gain = 103.812 ; free physical = 1942 ; free virtual = 26066
Info: at iteration #5: temp = 0.000000, timing cost = 21951, wirelen = 47997
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 1bbc9ccb5
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2771.156 ; gain = 0.000 ; free physical = 1674 ; free virtual = 25798
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1bbc9ccb5
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2771.156 ; gain = 0.000 ; free physical = 1674 ; free virtual = 25798
Phase 1 Initialization | Checksum: 1bbc9ccb5
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2771.156 ; gain = 0.000 ; free physical = 1674 ; free virtual = 25798
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1bbc9ccb5
Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2771.156 ; gain = 0.000 ; free physical = 1674 ; free virtual = 25798
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1bbc9ccb5
Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2771.156 ; gain = 0.000 ; free physical = 1674 ; free virtual = 25798
Phase 2 Timer Update And Timing Data Collection | Checksum: 1bbc9ccb5
Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2771.156 ; gain = 0.000 ; free physical = 1674 ; free virtual = 25798
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 4 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 29873a049
Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2771.156 ; gain = 0.000 ; free physical = 1673 ; free virtual = 25797
Retarget | Checksum: 29873a049
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 9 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 29873a049
Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2771.156 ; gain = 0.000 ; free physical = 1673 ; free virtual = 25797
Constant propagation | Checksum: 29873a049
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 20271f92d
Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2771.156 ; gain = 0.000 ; free physical = 1673 ; free virtual = 25797
Sweep | Checksum: 20271f92d
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 1 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 20271f92d
Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2803.172 ; gain = 32.016 ; free physical = 1673 ; free virtual = 25797
BUFG optimization | Checksum: 20271f92d
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 20271f92d
Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2803.172 ; gain = 32.016 ; free physical = 1673 ; free virtual = 25797
Shift Register Optimization | Checksum: 20271f92d
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 26b3a7663
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2803.172 ; gain = 32.016 ; free physical = 1673 ; free virtual = 25797
Post Processing Netlist | Checksum: 26b3a7663
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 295e54300
Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2803.172 ; gain = 32.016 ; free physical = 1673 ; free virtual = 25797
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2803.172 ; gain = 0.000 ; free physical = 1673 ; free virtual = 25797
Phase 9.2 Verifying Netlist Connectivity | Checksum: 295e54300
Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2803.172 ; gain = 32.016 ; free physical = 1673 ; free virtual = 25797
Phase 9 Finalization | Checksum: 295e54300
Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2803.172 ; gain = 32.016 ; free physical = 1673 ; free virtual = 25797
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 9 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 8 | 1 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 295e54300
Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2803.172 ; gain = 32.016 ; free physical = 1673 ; free virtual = 25797
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.172 ; gain = 0.000 ; free physical = 1673 ; free virtual = 25797
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 295e54300
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2803.172 ; gain = 0.000 ; free physical = 1672 ; free virtual = 25796
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 295e54300
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.172 ; gain = 0.000 ; free physical = 1672 ; free virtual = 25796
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.172 ; gain = 0.000 ; free physical = 1672 ; free virtual = 25796
Ending Netlist Obfuscation Task | Checksum: 295e54300
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.172 ; gain = 0.000 ; free physical = 1672 ; free virtual = 25796
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2803.172 ; gain = 448.730 ; free physical = 1672 ; free virtual = 25796
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 8 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.188 ; gain = 0.000 ; free physical = 1639 ; free virtual = 25763
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d00b5f36
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2835.188 ; gain = 0.000 ; free physical = 1639 ; free virtual = 25763
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.188 ; gain = 0.000 ; free physical = 1639 ; free virtual = 25763
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
[30%] Placement Phase 2 completed
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b25fb3a0
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.86 . Memory (MB): peak = 2835.188 ; gain = 0.000 ; free physical = 1621 ; free virtual = 25745
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: e661f65d
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1622 ; free virtual = 25746
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: e661f65d
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1622 ; free virtual = 25746
Phase 1 Placer Initialization | Checksum: e661f65d
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1622 ; free virtual = 25746
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 11e037c0f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1621 ; free virtual = 25745
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 155c6d0a1
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1621 ; free virtual = 25745
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 155c6d0a1
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1621 ; free virtual = 25745
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 197850230
Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1609 ; free virtual = 25733
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 68 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 29 nets or LUTs. Breaked 0 LUT, combined 29 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1607 ; free virtual = 25731
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 29 | 29 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 29 | 29 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 9a4b326a
Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1607 ; free virtual = 25731
Phase 2.4 Global Placement Core | Checksum: 89355008
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1607 ; free virtual = 25731
Phase 2 Global Placement | Checksum: 89355008
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1607 ; free virtual = 25731
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 10281d1bd
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1607 ; free virtual = 25731
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: e6768742
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1607 ; free virtual = 25731
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 17ab67479
Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1607 ; free virtual = 25731
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 162002af2
Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1607 ; free virtual = 25731
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 141baaea6
Time (s): cpu = 00:00:21 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1608 ; free virtual = 25732
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 10950e876
Time (s): cpu = 00:00:22 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1608 ; free virtual = 25732
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 103172eff
Time (s): cpu = 00:00:22 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1608 ; free virtual = 25732
Phase 3 Detail Placement | Checksum: 103172eff
Time (s): cpu = 00:00:22 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1608 ; free virtual = 25732
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: fe2fae3c
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.882 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1bbb49bf2
Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1608 ; free virtual = 25732
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1bbb49bf2
Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1608 ; free virtual = 25732
Phase 4.1.1.1 BUFG Insertion | Checksum: fe2fae3c
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1608 ; free virtual = 25732
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1047be65b
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1608 ; free virtual = 25732
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1608 ; free virtual = 25732
Phase 4.1 Post Commit Optimization | Checksum: 1047be65b
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1608 ; free virtual = 25732
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1047be65b
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1608 ; free virtual = 25732
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 2x2|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1047be65b
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1608 ; free virtual = 25732
Phase 4.3 Placer Reporting | Checksum: 1047be65b
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1608 ; free virtual = 25732
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1608 ; free virtual = 25732
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1608 ; free virtual = 25732
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18ed22daf
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1607 ; free virtual = 25731
Ending Placer Task | Checksum: 18030ff7c
Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.215 ; gain = 7.027 ; free physical = 1603 ; free virtual = 25727
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:10 . Memory (MB): peak = 2842.215 ; gain = 39.043 ; free physical = 1602 ; free virtual = 25726
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
Info: at iteration #10: temp = 0.000000, timing cost = 21482, wirelen = 46500
report_io: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1601 ; free virtual = 25725
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1599 ; free virtual = 25724
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: ac1bb603 ConstDB: 0 ShapeSum: d4154979 RouteDB: 0
Info: at iteration #15: temp = 0.000000, timing cost = 21263, wirelen = 45941
[50%] Placement Phase 3 completed
Running routing......
Info: at iteration #20: temp = 0.000000, timing cost = 19871, wirelen = 45746
[60%] Routing Phase 0 completed
Info: at iteration #23: temp = 0.000000, timing cost = 19494, wirelen = 45683
Info: SA placement time 45.03s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 27.05 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.60 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 9.32 ns
Info: Slack histogram:
Info: legend: * represents 169 endpoint(s)
Info: + represents [1,169) endpoint(s)
Info: [ 3037, 4848) |+
Info: [ 4848, 6659) |**+
Info: [ 6659, 8470) |*****+
Info: [ 8470, 10281) |***+
Info: [ 10281, 12092) |+
Info: [ 12092, 13903) |*+
Info: [ 13903, 15714) |***********+
Info: [ 15714, 17525) |*******************+
Info: [ 17525, 19336) |************************************************************
Info: [ 19336, 21147) |*****************************************+
Info: [ 21147, 22958) |**+
Info: [ 22958, 24769) |*+
Info: [ 24769, 26580) |+
Info: [ 26580, 28391) |***+
Info: [ 28391, 30202) |*+
Info: [ 30202, 32013) |+
Info: [ 32013, 33824) |*+
Info: [ 33824, 35635) |**+
Info: [ 35635, 37446) |*+
Info: [ 37446, 39257) |*+
Info: Checksum: 0x5c775faa
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 70113 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 216 783 | 216 783 | 69519| 1.36 1.36|
Info: 2000 | 371 1628 | 155 845 | 68937| 0.40 1.76|
Info: 3000 | 541 2458 | 170 830 | 68875| 0.36 2.12|
Info: 4000 | 697 3302 | 156 844 | 68860| 0.34 2.47|
Info: 5000 | 819 4180 | 122 878 | 68477| 0.36 2.83|
[70%] Routing Phase 1 completed
Info: 6000 | 1038 4961 | 219 781 | 68267| 0.42 3.25|
Info: 7000 | 1147 5852 | 109 891 | 67621| 0.44 3.69|
Info: 8000 | 1276 6723 | 129 871 | 66905| 0.53 4.22|
Info: 9000 | 1422 7577 | 146 854 | 67030| 0.60 4.82|
Info: 10000 | 1546 8453 | 124 876 | 66405| 0.55 5.37|
Info: 11000 | 1672 9327 | 126 874 | 66208| 0.53 5.90|
Info: 12000 | 1781 10218 | 109 891 | 65584| 0.64 6.54|
Info: 13000 | 1907 11092 | 126 874 | 65045| 0.56 7.10|
Info: 14000 | 2037 11962 | 130 870 | 64412| 0.45 7.55|
Info: 15000 | 2194 12805 | 157 843 | 63915| 0.41 7.96|
Post Restoration Checksum: NetGraph: 5ae7c01f | NumContArr: 756a9276 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 255a447cf
Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1524 ; free virtual = 25649
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 255a447cf
Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1524 ; free virtual = 25649
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 255a447cf
Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1524 ; free virtual = 25649
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 14dbaa9cc
Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1494 ; free virtual = 25618
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 |
Router Utilization Summary
Global Vertical Routing Utilization = 0.000304652 %
Global Horizontal Routing Utilization = 0.000213129 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 3784
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 3780
Number of Partially Routed Nets = 4
Number of Node Overlaps = 1
Phase 2 Router Initialization | Checksum: 1b34de596
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1491 ; free virtual = 25616
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 1b34de596
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1491 ; free virtual = 25616
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 17b265583
Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1491 ; free virtual = 25616
Phase 3 Initial Routing | Checksum: 17b265583
Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1491 ; free virtual = 25616
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 537
Number of Nodes with overlaps = 8
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.540 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 28d88d834
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1487 ; free virtual = 25612
Phase 4 Rip-up And Reroute | Checksum: 28d88d834
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1487 ; free virtual = 25611
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 28d88d834
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1486 ; free virtual = 25610
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 28d88d834
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1485 ; free virtual = 25610
Phase 5 Delay and Skew Optimization | Checksum: 28d88d834
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1485 ; free virtual = 25610
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 2edf1f0a2
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1484 ; free virtual = 25608
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 2edf1f0a2
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1483 ; free virtual = 25608
Phase 6 Post Hold Fix | Checksum: 2edf1f0a2
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1483 ; free virtual = 25608
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.817905 %
Global Horizontal Routing Utilization = 1.00945 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 2edf1f0a2
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1480 ; free virtual = 25604
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 2edf1f0a2
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1487 ; free virtual = 25612
Phase 9 Depositing Routes
Info: 16000 | 2374 13625 | 180 820 | 63407| 0.51 8.47|
Info: 17000 | 2523 14476 | 149 851 | 63034| 0.50 8.97|
Phase 9 Depositing Routes | Checksum: 337bde8f8
Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1489 ; free virtual = 25613
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 337bde8f8
Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1489 ; free virtual = 25613
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 19857a58c
Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1489 ; free virtual = 25613
Ending Routing Task | Checksum: 19857a58c
Time (s): cpu = 00:00:48 ; elapsed = 00:00:33 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1489 ; free virtual = 25613
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:34 . Memory (MB): peak = 2842.215 ; gain = 0.000 ; free physical = 1488 ; free virtual = 25613
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Info: 18000 | 2643 15356 | 120 880 | 62792| 0.58 9.56|
Info: 19000 | 2754 16245 | 111 889 | 62344| 0.42 9.98|
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (2175)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (7062)
5. checking no_input_delay (1)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (2175)
---------------------------
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[36]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[37]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[39]/Q (HIGH)
There are 2163 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (7062)
---------------------------------------------------
There are 7062 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (9)
-------------------------------
There are 9 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Info: 20000 | 2966 17033 | 212 788 | 62279| 0.57 10.54|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
Info: 21000 | 3082 17917 | 116 884 | 61859| 0.49 11.03|
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Info: 22000 | 3253 18746 | 171 829 | 61712| 0.74 11.77|
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Info: 23000 | 3333 19666 | 80 920 | 61706| 0.73 12.50|
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Info: 24000 | 3457 20542 | 124 876 | 61159| 0.52 13.01|
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
Info: 25000 | 3604 21395 | 147 853 | 60994| 0.47 13.48|
Info: 26000 | 3734 22265 | 130 870 | 60698| 0.45 13.93|
Info: 27000 | 3838 23161 | 104 896 | 60501| 0.43 14.37|
Info: 28000 | 3961 24038 | 123 877 | 59953| 0.35 14.71|
Info: 29000 | 4094 24905 | 133 867 | 59443| 0.37 15.08|
Info: 30000 | 4301 25698 | 207 793 | 59171| 0.35 15.44|
Info: 31000 | 4495 26504 | 194 806 | 58921| 0.35 15.79|
Info: 32000 | 4598 27401 | 103 897 | 58898| 0.43 16.22|
Info: 33000 | 4717 28282 | 119 881 | 58272| 0.39 16.60|
Info: 34000 | 4826 29173 | 109 891 | 58371| 0.44 17.05|
Info: 35000 | 4899 30100 | 73 927 | 57868| 0.44 17.49|
Info: 36000 | 5009 30990 | 110 890 | 57538| 0.43 17.91|
Info: 37000 | 5102 31897 | 93 907 | 57787| 0.31 18.22|
Info: 38000 | 5198 32801 | 96 904 | 57174| 0.30 18.53|
Info: 39000 | 5354 33645 | 156 844 | 56787| 0.34 18.87|
Info: 40000 | 5521 34478 | 167 833 | 56610| 0.40 19.27|
Info: 41000 | 5631 35368 | 110 890 | 56152| 0.43 19.70|
Info: 42000 | 5787 36212 | 156 844 | 55870| 0.33 20.03|
Info: 43000 | 5888 37111 | 101 899 | 55543| 0.31 20.34|
Info: 44000 | 6085 37914 | 197 803 | 55147| 0.36 20.71|
[80%] Routing Phase 2 completed
Info: 45000 | 6280 38719 | 195 805 | 54771| 0.36 21.07|
Info: 46000 | 6345 39654 | 65 935 | 54952| 0.31 21.38|
Info: 47000 | 6457 40542 | 112 888 | 54281| 0.33 21.71|
Info: 48000 | 6608 41391 | 151 849 | 53738| 0.39 22.11|
Info: 49000 | 6818 42181 | 210 790 | 54882| 0.42 22.53|
Info: 50000 | 7045 42954 | 227 773 | 54558| 0.39 22.92|
Info: 51000 | 7217 43782 | 172 828 | 54226| 0.33 23.25|
Info: 52000 | 7384 44615 | 167 833 | 53673| 0.30 23.56|
Info: 53000 | 7554 45445 | 170 830 | 53077| 0.46 24.02|
Info: 54000 | 7690 46309 | 136 864 | 52652| 0.39 24.41|
Info: 55000 | 7841 47158 | 151 849 | 52117| 0.46 24.87|
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[39]_1[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Info: 56000 | 7954 48045 | 113 887 | 53411| 0.65 25.52|
Info: 57000 | 8043 48956 | 89 911 | 52962| 0.64 26.16|
Info: 58000 | 8085 49914 | 42 958 | 53314| 0.51 26.66|
Info: 59000 | 8214 50785 | 129 871 | 53506| 0.57 27.23|
Info: 60000 | 8299 51700 | 85 915 | 53804| 0.59 27.82|
Loading site data...
Info: 61000 | 8335 52664 | 36 964 | 52928| 0.68 28.49|
Info: 62000 | 8416 53583 | 81 919 | 52244| 0.56 29.06|
Loading route data...
Processing options...
Creating bitmap...
Info: 63000 | 8540 54459 | 124 876 | 51583| 0.49 29.55|
Info: 64000 | 8667 55332 | 127 873 | 51331| 0.65 30.19|
Info: 65000 | 8805 56194 | 138 862 | 50848| 0.60 30.80|
Info: 66000 | 8950 57049 | 145 855 | 50763| 0.41 31.20|
Creating bitstream...
Info: 67000 | 9137 57862 | 187 813 | 50201| 0.43 31.64|
Info: 68000 | 9281 58718 | 144 856 | 50098| 0.47 32.11|
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
Info: 69000 | 9381 59618 | 100 900 | 50100| 0.58 32.69|
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 3156.301 ; gain = 250.176 ; free physical = 1119 ; free virtual = 25247
INFO: [Common 17-206] Exiting Vivado at Wed Apr 24 02:07:32 2024...
[Pipeline] }
Info: 70000 | 9514 60485 | 133 867 | 49461| 0.39 33.09|
[Pipeline] // stage
[Pipeline] }
Info: 71000 | 9647 61352 | 133 867 | 48764| 0.38 33.47|
Info: 72000 | 9784 62215 | 137 863 | 48161| 0.37 33.84|
Info: 73000 | 9908 63091 | 124 876 | 48412| 0.38 34.22|
Info: 74000 | 10033 63966 | 125 875 | 47705| 0.37 34.59|
Info: 75000 | 10207 64792 | 174 826 | 47784| 0.41 35.00|
Info: 76000 | 10424 65575 | 217 783 | 47477| 0.39 35.39|
WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
Info: 77000 | 10575 66424 | 151 849 | 46858| 0.38 35.77|
Info: 78000 | 10719 67280 | 144 856 | 46718| 0.39 36.16|
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Info: 79000 | 10883 68116 | 164 836 | 46387| 0.41 36.57|
Info: 80000 | 11036 68963 | 153 847 | 47683| 0.35 36.92|
Info: 81000 | 11083 69916 | 47 953 | 46841| 0.44 37.36|
Info: 82000 | 11162 70837 | 79 921 | 46018| 0.38 37.74|
Info: 83000 | 11292 71707 | 130 870 | 46543| 0.36 38.10|
Info: 84000 | 11358 72641 | 66 934 | 45638| 0.32 38.42|
Info: 85000 | 11578 73421 | 220 780 | 45046| 0.41 38.82|
Info: 86000 | 11732 74267 | 154 846 | 44426| 0.41 39.23|
Info: 87000 | 11889 75110 | 157 843 | 44407| 0.43 39.65|
Info: 88000 | 12063 75936 | 174 826 | 43784| 0.38 40.03|
Info: 89000 | 12272 76727 | 209 791 | 45258| 0.46 40.49|
Info: 90000 | 12298 77701 | 26 974 | 44294| 0.54 41.03|
Info: 91000 | 12405 78594 | 107 893 | 43721| 0.46 41.50|
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Wed Apr 24 02:07:41 2024
[Pipeline] }
[Pipeline] // stage
Info: 92000 | 12526 79473 | 121 879 | 43027| 0.38 41.88|
[Pipeline] }
Info: 93000 | 12688 80311 | 162 838 | 42668| 0.39 42.26|
Info: 94000 | 12830 81169 | 142 858 | 41977| 0.43 42.70|
Info: 95000 | 13041 81958 | 211 789 | 41504| 0.38 43.08|
Info: 96000 | 13199 82800 | 158 842 | 40790| 0.34 43.42|
Info: 97000 | 13348 83651 | 149 851 | 40446| 0.34 43.76|
Info: 98000 | 13505 84494 | 157 843 | 40339| 0.37 44.12|
Info: 99000 | 13683 85316 | 178 822 | 39830| 0.41 44.53|
Info: 100000 | 13880 86119 | 197 803 | 39475| 0.40 44.94|
Info: 101000 | 14053 86946 | 173 827 | 38817| 0.39 45.33|
Info: 102000 | 14232 87767 | 179 821 | 38658| 0.40 45.73|
Info: 103000 | 14467 88532 | 235 765 | 38083| 0.38 46.11|
Info: 104000 | 14705 89294 | 238 762 | 37508| 0.37 46.48|
Info: 105000 | 15000 89999 | 295 705 | 37262| 0.47 46.95|
Info: 106000 | 15178 90821 | 178 822 | 36991| 0.41 47.36|
Info: 107000 | 15401 91598 | 223 777 | 36594| 0.47 47.84|
Info: 108000 | 15565 92434 | 164 836 | 36394| 0.41 48.25|
Info: 109000 | 15809 93190 | 244 756 | 35920| 0.37 48.62|
Info: 110000 | 15932 94067 | 123 877 | 36609| 0.47 49.09|
Info: 111000 | 16050 94949 | 118 882 | 35905| 0.45 49.53|
Info: 112000 | 16268 95731 | 218 782 | 35605| 0.51 50.05|
Info: 113000 | 16498 96501 | 230 770 | 35173| 0.41 50.46|
Info: 114000 | 16754 97245 | 256 744 | 34695| 0.43 50.89|
Info: 115000 | 17035 97964 | 281 719 | 34261| 0.49 51.38|
Info: 116000 | 17297 98702 | 262 738 | 33698| 0.43 51.82|
Info: 117000 | 17542 99457 | 245 755 | 33491| 0.44 52.26|
Info: 118000 | 17794 100205 | 252 748 | 33097| 0.49 52.75|
Info: 119000 | 18076 100923 | 282 718 | 32618| 0.40 53.15|
Info: 120000 | 18423 101576 | 347 653 | 32209| 0.43 53.58|
Info: 121000 | 18754 102245 | 331 669 | 31896| 0.49 54.07|
Info: 122000 | 19023 102976 | 269 731 | 32140| 0.52 54.59|
Info: 123000 | 19212 103787 | 189 811 | 31413| 0.47 55.06|
Info: 124000 | 19567 104432 | 355 645 | 31109| 0.44 55.50|
Info: 125000 | 19859 105140 | 292 708 | 31009| 0.45 55.95|
Info: 126000 | 20194 105805 | 335 665 | 30585| 0.49 56.44|
Info: 127000 | 20605 106394 | 411 589 | 30226| 0.46 56.90|
Info: 128000 | 20949 107050 | 344 656 | 29931| 0.45 57.35|
Info: 129000 | 21223 107776 | 274 726 | 29747| 0.44 57.80|
Info: 130000 | 21603 108396 | 380 620 | 29413| 0.45 58.25|
Info: 131000 | 22022 108977 | 419 581 | 29025| 0.44 58.69|
Info: 132000 | 22360 109639 | 338 662 | 28885| 0.56 59.24|
Info: 133000 | 22713 110286 | 353 647 | 28771| 0.51 59.75|
Info: 134000 | 23135 110864 | 422 578 | 28324| 0.45 60.20|
Info: 135000 | 23475 111524 | 340 660 | 28316| 0.57 60.77|
Info: 136000 | 23775 112224 | 300 700 | 28186| 0.49 61.26|
Info: 137000 | 24073 112926 | 298 702 | 27852| 0.41 61.67|
Info: 138000 | 24373 113626 | 300 700 | 27651| 0.45 62.12|
Info: 139000 | 24810 114189 | 437 563 | 27405| 0.45 62.57|
Info: 140000 | 25274 114725 | 464 536 | 27087| 0.48 63.05|
Info: 141000 | 25743 115256 | 469 531 | 26840| 0.50 63.54|
Info: 142000 | 26245 115754 | 502 498 | 26562| 0.49 64.03|
Info: 143000 | 26782 116217 | 537 463 | 26296| 0.45 64.49|
Info: 144000 | 27318 116681 | 536 464 | 25996| 0.45 64.94|
Info: 145000 | 27717 117282 | 399 601 | 25728| 0.49 65.42|
Info: 146000 | 28229 117770 | 512 488 | 25482| 0.49 65.91|
Info: 147000 | 28694 118305 | 465 535 | 25214| 0.45 66.37|
Info: 148000 | 29206 118793 | 512 488 | 25218| 0.46 66.83|
Info: 149000 | 29433 119566 | 227 773 | 26874| 0.48 67.31|
Info: 150000 | 29528 120471 | 95 905 | 26020| 0.43 67.74|
Info: 151000 | 29590 121409 | 62 938 | 25143| 0.37 68.11|
Info: 152000 | 29925 122074 | 335 665 | 25638| 0.53 68.64|
Info: 153000 | 30229 122770 | 304 696 | 26140| 0.62 69.26|
Info: 154000 | 30501 123498 | 272 728 | 25755| 0.70 69.96|
Info: 155000 | 30721 124278 | 220 780 | 25905| 0.50 70.46|
Info: 156000 | 31044 124955 | 323 677 | 25884| 0.65 71.11|
Info: 157000 | 31260 125739 | 216 784 | 25264| 0.54 71.65|
Info: 158000 | 31679 126320 | 419 581 | 24844| 0.51 72.17|
Info: 159000 | 32217 126782 | 538 462 | 24479| 0.43 72.60|
Info: 160000 | 32685 127314 | 468 532 | 24126| 0.44 73.04|
Info: 161000 | 33223 127776 | 538 462 | 23771| 0.47 73.50|
Info: 162000 | 33741 128258 | 518 482 | 23454| 0.57 74.07|
Info: 163000 | 34191 128793 | 450 535 | 23077| 0.43 74.50|
Info: 164000 | 34585 129381 | 394 588 | 22560| 0.38 74.88|
Info: 165000 | 34883 130059 | 298 678 | 22225| 0.42 75.30|
Info: 166000 | 35218 130703 | 335 644 | 21635| 0.32 75.63|
Info: 167000 | 35481 131380 | 263 677 | 20971| 0.29 75.92|
Info: 168000 | 35774 132010 | 293 630 | 20306| 0.30 76.22|
Info: 169000 | 36131 132584 | 357 574 | 19757| 0.38 76.60|
Info: 170000 | 36455 133174 | 324 590 | 19195| 0.35 76.95|
Info: 171000 | 36902 133644 | 447 470 | 18742| 0.37 77.32|
Info: 172000 | 37317 134136 | 415 492 | 18307| 0.40 77.72|
Info: 173000 | 37603 134820 | 286 684 | 18171| 0.56 78.28|
Info: 174000 | 38061 135294 | 458 474 | 17797| 0.41 78.68|
Info: 175000 | 38554 135707 | 493 413 | 17359| 0.41 79.10|
Info: 176000 | 39093 136108 | 539 401 | 16953| 0.47 79.56|
Info: 177000 | 39521 136646 | 428 538 | 16744| 0.55 80.12|
Info: 178000 | 40005 137101 | 484 455 | 16389| 0.51 80.63|
Info: 179000 | 40460 137584 | 455 483 | 15965| 0.41 81.03|
Info: 180000 | 40766 138105 | 306 521 | 15332| 0.35 81.38|
Info: 181000 | 40956 138854 | 190 749 | 14570| 0.27 81.65|
Info: 182000 | 40990 139806 | 34 952 | 13608| 0.17 81.82|
Info: 183000 | 41007 140788 | 17 982 | 12625| 0.16 81.98|
Info: 184000 | 41035 141757 | 28 969 | 11654| 0.16 82.14|
Info: 185000 | 41048 142742 | 13 985 | 10679| 0.17 82.31|
Info: 186000 | 41068 143717 | 20 975 | 9700| 0.16 82.47|
Info: 187000 | 41079 144689 | 11 972 | 8711| 0.15 82.61|
Info: 188000 | 41096 145665 | 17 976 | 7732| 0.15 82.77|
Info: 189000 | 41104 146650 | 8 985 | 6741| 0.15 82.92|
Info: 190000 | 41108 147643 | 4 993 | 5745| 0.15 83.06|
Info: 191000 | 41117 148625 | 9 982 | 4754| 0.15 83.22|
Info: 192000 | 41141 149589 | 24 964 | 3783| 0.18 83.39|
Info: 193000 | 41283 150388 | 142 799 | 2931| 0.34 83.73|
Info: 194000 | 41406 151234 | 123 846 | 2058| 0.33 84.05|
Info: 195000 | 41551 151979 | 145 745 | 1243| 0.40 84.46|
Info: 196000 | 41589 152674 | 38 695 | 290| 0.30 84.76|
Info: 196291 | 41591 152821 | 2 147 | 0| 0.20 84.96|
Info: Routing complete.
Info: Router1 time 84.96s
Info: Checksum: 0x350bd394
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info: 1.1 1.6 Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_D_LUT4_Z_B[1] (8,6) -> (8,5)
Info: Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 1.9 Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 1.9 Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT (8,5) -> (8,5)
Info: Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.30-141.32
Info: 0.2 2.0 Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 2.0 Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1 (8,5) -> (8,5)
Info: Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 2.3 Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 2.6 4.8 Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (8,5) -> (26,25)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.1 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_LUT4_Z.F
Info: 2.4 7.5 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1 (26,25) -> (34,9)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB0.B
Info: 0.4 7.9 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.9 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_FCI_INT (34,9) -> (34,9)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.9 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.9 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT (34,9) -> (34,9)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.0 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB0.FCO
Info: 0.0 8.0 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_FCI_INT (34,9) -> (34,9)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB1.FCI
Info: 0.0 8.0 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB1.FCO
Info: 0.0 8.0 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN_COUT (34,9) -> (34,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.1 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 8.1 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (34,9) -> (34,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 8.1 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 8.1 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (34,9) -> (35,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.1 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 8.1 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (35,9) -> (35,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 8.1 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 8.1 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (35,9) -> (35,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.2 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 8.2 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (35,9) -> (35,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 8.2 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 8.2 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (35,9) -> (35,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.3 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 8.3 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (35,9) -> (35,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 8.3 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 8.3 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (35,9) -> (35,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.4 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 8.4 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (35,9) -> (35,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 8.4 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 8.4 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (35,9) -> (36,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.4 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 8.4 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (36,9) -> (36,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 8.4 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 8.4 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1_CIN (36,9) -> (36,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.5 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 8.5 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (36,9) -> (36,9)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 8.5 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 8.5 Net $nextpnr_CCU2C_1$CIN (36,9) -> (36,9)
Info: Sink $nextpnr_CCU2C_1$CCU2_COMB0.FCI
Info: 0.4 8.9 Source $nextpnr_CCU2C_1$CCU2_COMB0.F
Info: 1.0 10.0 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1_COUT (36,9) -> (36,17)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B1_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.2 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B1_LUT4_C.F
Info: 2.6 12.8 Net SOC.Memory.address_LUT4_Z_C[1] (36,17) -> (25,40)
Info: Sink SOC.Memory.address_LUT4_Z_3.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.1 Source SOC.Memory.address_LUT4_Z_3.F
Info: 2.4 15.5 Net SOC.slave_address[2] (25,40) -> (15,56)
Info: Sink SOC.Memory.memory.0.937$DPRAM_COMB3.D
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.5-22.18
Info: 0.2 15.7 Source SOC.Memory.memory.0.937$DPRAM_COMB3.F
Info: 0.6 16.3 Net SOC.Memory.memory.0.937_DO[3] (15,56) -> (16,56)
Info: Sink SOC.Memory.memory.0.913_DO_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 16.6 Source SOC.Memory.memory.0.913_DO_LUT4_Z.F
Info: 0.7 17.3 Net SOC.Memory.memory.0.913_DO[4] (16,56) -> (16,55)
Info: Sink SOC.Memory.memory.0.905_DO_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 17.5 Source SOC.Memory.memory.0.905_DO_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.2 17.7 Net SOC.Memory.memory.0.905_DO_LUT4_C_Z[3] (16,55) -> (16,55)
Info: Sink SOC.Memory.memory.0.849_DO_LUT4_C_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 18.0 Source SOC.Memory.memory.0.849_DO_LUT4_C_Z_LUT4_Z.F
Info: 0.8 18.7 Net SOC.Memory.memory.0.849_DO_LUT4_C_Z[4] (16,55) -> (18,54)
Info: Sink SOC.Memory.memory.0.849_DO_LUT4_C_Z_LUT4_B.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 19.0 Source SOC.Memory.memory.0.849_DO_LUT4_C_Z_LUT4_B.OFX
Info: 0.8 19.8 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_C_LUT4_C_Z_LUT4_Z_2_B[3] (18,54) -> (18,54)
Info: Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_C_LUT4_C_Z_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 20.0 Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_C_LUT4_C_Z_LUT4_Z_2.F
Info: 1.6 21.6 Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_C_LUT4_C_Z[3] (18,54) -> (22,42)
Info: Sink SOC.Core.read_data_LUT4_Z_7_D_PFUMX_Z_ALUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 21.9 Source SOC.Core.read_data_LUT4_Z_7_D_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 21.9 Net SOC.Core.read_data_LUT4_Z_7_D_PFUMX_Z_ALUT (22,42) -> (22,42)
Info: Sink SOC.Core.read_data_LUT4_Z_7_D_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info: 0.2 22.0 Source SOC.Core.read_data_LUT4_Z_7_D_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 2.0 24.0 Net SOC.Core.read_data_LUT4_Z_7_C[3] (22,42) -> (26,25)
Info: Sink SOC.Core.read_data_LUT4_Z_15_C_PFUMX_Z_C0_LUT4_C_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 24.2 Source SOC.Core.read_data_LUT4_Z_15_C_PFUMX_Z_C0_LUT4_C_Z_LUT4_Z.F
Info: 2.2 26.4 Net SOC.Core.read_data_LUT4_Z_10_D[2] (26,25) -> (41,16)
Info: Sink SOC.Core.read_data_PFUMX_Z_13_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 26.6 Source SOC.Core.read_data_PFUMX_Z_13_BLUT_LUT4_Z.OFX
Info: 0.8 27.4 Net SOC.read_data[31] (41,16) -> (33,16)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:21.34-21.43
Info: 0.0 27.4 Setup SOC.Core.instruction_register_TRELLIS_FF_Q.M
Info: 5.7 ns logic, 21.7 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source rx$tr_io.O
Info: 1.7 1.7 Net rx$TRELLIS_IO_IN (90,20) -> (70,11)
Info: Sink SOC.Uart.i_uart_rx.rxd_reg_0_TRELLIS_FF_Q.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:4.16-4.18
Info: 0.0 1.7 Setup SOC.Uart.i_uart_rx.rxd_reg_0_TRELLIS_FF_Q.M
Info: 0.0 ns logic, 1.7 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info: 2.8 3.3 Net SOC.Core.read_data_LUT4_Z_2_C[0] (43,16) -> (78,21)
Info: Sink led_LUT4_Z_6.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: 0.2 3.5 Source led_LUT4_Z_6.F
Info: 2.8 6.4 Net led[2]$TRELLIS_IO_OUT (78,21) -> (90,44)
Info: Sink led[2]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.6 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 36.49 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 1.73 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.36 ns
Info: Slack histogram:
Info: legend: * represents 193 endpoint(s)
Info: + represents [1,193) endpoint(s)
Info: [ 12596, 13919) |+
Info: [ 13919, 15242) |*****+
Info: [ 15242, 16565) |****+
Info: [ 16565, 17888) |+
Info: [ 17888, 19211) |+
Info: [ 19211, 20534) |*+
Info: [ 20534, 21857) |************+
Info: [ 21857, 23180) |********+
Info: [ 23180, 24503) |**********************************+
Info: [ 24503, 25826) |************************************************************
Info: [ 25826, 27149) |***+
Info: [ 27149, 28472) |+
Info: [ 28472, 29795) |***+
Info: [ 29795, 31118) |*+
Info: [ 31118, 32441) |+
Info: [ 32441, 33764) |+
Info: [ 33764, 35087) |+
Info: [ 35087, 36410) |**+
Info: [ 36410, 37733) |**+
Info: [ 37733, 39056) |*+
Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Open file DONE
Parse file DONE
load program
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
Loading: [==== ] 7.65%[Pipeline] // script
Load SRAM: [========= ] 18.00%[Pipeline] }
Loading: [======== ] 15.29%[Pipeline] // stage
[Pipeline] }
Load SRAM: [=================== ] 38.00%
Loading: [============ ] 22.94%
Load SRAM: [============================= ] 58.00%
Loading: [================ ] 30.58%
Load SRAM: [======================================= ] 78.00%
Loading: [==================== ] 38.23%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
[Pipeline] }
Lock released on resource [nexys4]
Loading: [======================= ] 45.87%[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
Loading: [=========================== ] 53.52%[Pipeline] // stage
[Pipeline] }
Loading: [=============================== ] 61.16%
Loading: [=================================== ] 68.81%
Loading: [======================================= ] 76.46%
Loading: [=========================================== ] 84.10%
Loading: [============================================== ] 91.75%
Loading: [==================================================] 99.39%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
[Pipeline] }
+ echo testando na tang nano
testando na tang nano
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
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