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INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:118]
INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
WARNING: [Synth 8-7071] port 'save_pc' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:228]
WARNING: [Synth 8-7071] port 'interrupt_on_hold' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:228]
WARNING: [Synth 8-7023] instance 'CSR_Unit' of module 'CSR_Unit' has 15 connections declared, but only 13 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:228]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1]
WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32]
WARNING: [Synth 8-7071] port 'interruption_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32]
WARNING: [Synth 8-7071] port 'interruption_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32]
WARNING: [Synth 8-7071] port 'interruption_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32]
WARNING: [Synth 8-7071] port 'interruption_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32]
WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 14 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string
Parameter MEMORY_SIZE bound to: 2048 - type: integer
INFO: [Synth 8-3876] $readmem data file '../../software/memory/fpga_test_3.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:35]
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
Parameter CLOCK_FREQ bound to: 100000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
Parameter DEPTH bound to: 8 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 100000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 100000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
Parameter WIDHT bound to: 8 - type: integer
INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
WARNING: [Synth 8-3848] Net interrupt_on_hold in module/entity CSR_Unit does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:20]
Info: Packing FFs...
Info: 229 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x4613b3cc
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 704/43848 1%
Info: TRELLIS_COMB: 13126/43848 29%
Info: TRELLIS_RAMW: 1076/ 5481 19%
WARNING: [Synth 8-6014] Unused sequential element buffer_full_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:52]
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:46]
WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[2] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module UART is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2116.297 ; gain = 491.652 ; free physical = 3624 ; free virtual = 26321
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2134.109 ; gain = 509.465 ; free physical = 3624 ; free virtual = 26321
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2134.109 ; gain = 509.465 ; free physical = 3624 ; free virtual = 26321
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Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2134.109 ; gain = 0.000 ; free physical = 3608 ; free virtual = 26305
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 6237 cells, random placement wirelen = 570079.
Info: at initial placer iter 0, wirelen = 2865
Info: at initial placer iter 1, wirelen = 2252
Info: at initial placer iter 2, wirelen = 1718
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Info: at initial placer iter 3, wirelen = 1684
Info: Running main analytical placer, max placement attempts per cell = 27844453.
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2283.859 ; gain = 0.000 ; free physical = 3577 ; free virtual = 26274
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2283.895 ; gain = 0.000 ; free physical = 3577 ; free virtual = 26274
Info: at iteration #1, type ALL: wirelen solved = 1668, spread = 101886, legal = 102720; time = 0.42s
Info: at iteration #2, type ALL: wirelen solved = 7496, spread = 71010, legal = 72193; time = 0.45s
Info: at iteration #3, type ALL: wirelen solved = 13000, spread = 66620, legal = 67656; time = 0.60s
Info: at iteration #4, type ALL: wirelen solved = 19007, spread = 63531, legal = 64668; time = 0.41s
Info: at iteration #5, type ALL: wirelen solved = 21184, spread = 59230, legal = 60767; time = 0.42s
Info: at iteration #6, type ALL: wirelen solved = 24007, spread = 57386, legal = 58817; time = 0.39s
Info: at iteration #7, type ALL: wirelen solved = 25389, spread = 54164, legal = 55815; time = 0.56s
Info: at iteration #8, type ALL: wirelen solved = 27290, spread = 53364, legal = 54718; time = 0.38s
Info: at iteration #9, type ALL: wirelen solved = 28822, spread = 52112, legal = 53538; time = 0.38s
Info: at iteration #10, type ALL: wirelen solved = 29707, spread = 50985, legal = 52581; time = 0.38s
Info: at iteration #11, type ALL: wirelen solved = 30125, spread = 50117, legal = 51663; time = 0.43s
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Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3514 ; free virtual = 26213
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Start Loading Part and Timing Information
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Loading part: xc7a100tcsg324-1
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3514 ; free virtual = 26213
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Start Applying 'set_property' XDC Constraints
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3513 ; free virtual = 26213
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INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 0000000000000000000000000000000000000000000001 | 000000
DECODE | 0000000000000000000000000000000000000000000010 | 000001
MEMADR | 0000000000000000000000000000000000000000000100 | 000010
MEMREAD_UNALIGNED | 0000000000000000000000000000000000000000001000 | 010110
LOAD_FIRST_BLOCK | 0000000000000000000000000000000000000000010000 | 010000
SAVE_FIRST_BLOCK | 0000000000000000000000000000000000000000100000 | 010001
CALC_NEXT_ADDRESS | 0000000000000000000000000000000000000001000000 | 010010
READ_SECOND_BLOCK | 0000000000000000000000000000000000000010000000 | 010011
LOAD_SECOND_BLOCK | 0000000000000000000000000000000000000100000000 | 010100
MERGE_BLOCKS | 0000000000000000000000000000000000001000000000 | 010101
FILTER_ALU_WB | 0000000000000000000000000000000000010000000000 | 010111
MEMREAD | 0000000000000000000000000000000000100000000000 | 000011
MEMWB | 0000000000000000000000000000000001000000000000 | 000100
MEMWRITE_UNALIGNED | 0000000000000000000000000000000010000000000000 | 011000
GEN_FIRST_BLOCK_PART_1 | 0000000000000000000000000000000100000000000000 | 011001
GEN_FIRST_BLOCK_PART_2 | 0000000000000000000000000000001000000000000000 | 011010
GEN_SECOND_BLOCK_PART_1 | 0000000000000000000000000000010000000000000000 | 011011
GEN_SECOND_BLOCK_PART_2 | 0000000000000000000000000000100000000000000000 | 011100
MERGE_WRITE_BLOCKS | 0000000000000000000000000001000000000000000000 | 011101
SWAP_VALUE_DIRECTION | 0000000000000000000000000010000000000000000000 | 011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 0000000000000000000000000100000000000000000000 | 100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 0000000000000000000000001000000000000000000000 | 100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 0000000000000000000000010000000000000000000000 | 100100
CLEAR_VALUE | 0000000000000000000000100000000000000000000000 | 011111
MERGE_WRITE_VALUE_1 | 0000000000000000000001000000000000000000000000 | 100000
WRITE_VALUE_1 | 0000000000000000000010000000000000000000000000 | 100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 0000000000000000000100000000000000000000000000 | 100101
READ_SECOND_BLOCK_TO_WRITE | 0000000000000000001000000000000000000000000000 | 100110
LOAD_SECOND_BLOCK_TO_WRITE | 0000000000000000010000000000000000000000000000 | 100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 0000000000000000100000000000000000000000000000 | 101000
SWAP_VALUE_DIRECTION_2 | 0000000000000001000000000000000000000000000000 | 101001
CLEAR_VALUE_PART_2 | 0000000000000010000000000000000000000000000000 | 101010
CLEAR_VALUE_PART_2_1 | 0000000000000100000000000000000000000000000000 | 101011
MERGE_WRITE_VALUE_2 | 0000000000001000000000000000000000000000000000 | 101100
WRITE_VALUE_2 | 0000000000010000000000000000000000000000000000 | 101101
MEMWRITE | 0000000000100000000000000000000000000000000000 | 000101
EXECUTER | 0000000001000000000000000000000000000000000000 | 000110
EXECUTEI | 0000000010000000000000000000000000000000000000 | 001000
JAL | 0000000100000000000000000000000000000000000000 | 001001
BEQ | 0000001000000000000000000000000000000000000000 | 001010
AUIPC | 0000010000000000000000000000000000000000000000 | 001100
LUI | 0000100000000000000000000000000000000000000000 | 001101
JALR_PC | 0001000000000000000000000000000000000000000000 | 001110
JALR | 0010000000000000000000000000000000000000000000 | 001011
ALUWB | 0100000000000000000000000000000000000000000000 | 000111
EXECUTECSR | 1000000000000000000000000000000000000000000000 | 001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3497 ; free virtual = 26198
---------------------------------------------------------------------------------
Info: at iteration #12, type ALL: wirelen solved = 31234, spread = 50397, legal = 52010; time = 0.59s
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
3 Input 32 Bit Adders := 1
2 Input 11 Bit Adders := 2
2 Input 6 Bit Adders := 4
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
+---XORs :
2 Bit Wide XORs := 1
+---Registers :
33 Bit Registers := 1
32 Bit Registers := 48
16 Bit Registers := 2
11 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 1
4 Bit Registers := 2
1 Bit Registers := 18
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
46 Input 46 Bit Muxes := 1
2 Input 46 Bit Muxes := 17
11 Input 46 Bit Muxes := 1
3 Input 33 Bit Muxes := 1
2 Input 32 Bit Muxes := 21
8 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 10
6 Input 32 Bit Muxes := 1
2 Input 31 Bit Muxes := 1
2 Input 8 Bit Muxes := 3
5 Input 8 Bit Muxes := 1
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
46 Input 4 Bit Muxes := 1
9 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
4 Input 3 Bit Muxes := 2
46 Input 3 Bit Muxes := 3
10 Input 3 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 14
46 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 4
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 65
46 Input 1 Bit Muxes := 12
4 Input 1 Bit Muxes := 3
8 Input 1 Bit Muxes := 7
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":226)
WARN (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":152)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
Info: at iteration #13, type ALL: wirelen solved = 32325, spread = 48489, legal = 50206; time = 0.36s
Info: at iteration #14, type ALL: wirelen solved = 32079, spread = 48768, legal = 50338; time = 0.36s
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
Info: at iteration #15, type ALL: wirelen solved = 32860, spread = 48839, legal = 50338; time = 0.40s
Info: at iteration #16, type ALL: wirelen solved = 33864, spread = 49642, legal = 51086; time = 0.47s
Info: at iteration #17, type ALL: wirelen solved = 34870, spread = 48462, legal = 50067; time = 0.47s
Info: at iteration #18, type ALL: wirelen solved = 34731, spread = 47436, legal = 48958; time = 0.40s
Info: at iteration #19, type ALL: wirelen solved = 34815, spread = 47406, legal = 49136; time = 0.38s
Info: at iteration #20, type ALL: wirelen solved = 34898, spread = 46880, legal = 48465; time = 0.37s
Info: at iteration #21, type ALL: wirelen solved = 34803, spread = 46487, legal = 48051; time = 0.54s
[10%] Placement Phase 0 completed
Info: at iteration #22, type ALL: wirelen solved = 34902, spread = 46174, legal = 47993; time = 0.37s
Info: at iteration #23, type ALL: wirelen solved = 35135, spread = 45696, legal = 47439; time = 0.38s
[20%] Placement Phase 1 completed
Info: at iteration #24, type ALL: wirelen solved = 35198, spread = 45462, legal = 47321; time = 0.37s
Info: at iteration #25, type ALL: wirelen solved = 35360, spread = 45512, legal = 47193; time = 0.37s
Info: at iteration #26, type ALL: wirelen solved = 35640, spread = 45414, legal = 47282; time = 0.53s
Info: at iteration #27, type ALL: wirelen solved = 35692, spread = 45270, legal = 46965; time = 0.37s
Info: at iteration #28, type ALL: wirelen solved = 35706, spread = 46115, legal = 47745; time = 0.37s
Info: at iteration #29, type ALL: wirelen solved = 36346, spread = 45894, legal = 47610; time = 0.37s
Info: at iteration #30, type ALL: wirelen solved = 36349, spread = 46727, legal = 48286; time = 0.38s
Info: at iteration #31, type ALL: wirelen solved = 36890, spread = 46387, legal = 47843; time = 0.52s
Info: at iteration #32, type ALL: wirelen solved = 37226, spread = 45981, legal = 47625; time = 0.37s
Info: HeAP Placer Time: 20.85s
Info: of which solving equations: 12.31s
Info: of which spreading cells: 1.60s
Info: of which strict legalisation: 0.46s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 9739, wirelen = 46965
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3276 ; free virtual = 25984
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3268 ; free virtual = 25975
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
Info: at iteration #5: temp = 0.000000, timing cost = 9648, wirelen = 42779
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3269 ; free virtual = 25977
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
[30%] Placement Phase 2 completed
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3231 ; free virtual = 25939
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3219 ; free virtual = 25927
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3223 ; free virtual = 25930
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3222 ; free virtual = 25930
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3222 ; free virtual = 25930
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3222 ; free virtual = 25930
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3222 ; free virtual = 25930
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 23|
|3 |LUT1 | 8|
|4 |LUT2 | 162|
|5 |LUT3 | 193|
|6 |LUT4 | 186|
|7 |LUT5 | 402|
|8 |LUT6 | 1435|
|9 |MUXF7 | 387|
|10 |MUXF8 | 30|
|11 |RAM256X1S | 64|
|12 |RAM32M | 2|
|13 |RAM32X1D | 4|
|14 |FDRE | 1758|
|15 |FDSE | 5|
|16 |LD | 4|
|17 |IBUF | 2|
|18 |IOBUF | 8|
|19 |OBUF | 9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3222 ; free virtual = 25930
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 38 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2283.895 ; gain = 509.465 ; free physical = 3222 ; free virtual = 25930
Synthesis Optimization Complete : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.895 ; gain = 659.250 ; free physical = 3222 ; free virtual = 25930
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2283.895 ; gain = 0.000 ; free physical = 3465 ; free virtual = 26173
INFO: [Netlist 29-17] Analyzing 522 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Info: at iteration #10: temp = 0.000000, timing cost = 10193, wirelen = 41294
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2347.891 ; gain = 0.000 ; free physical = 3464 ; free virtual = 26171
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 82 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 8 instances
LD => LDCE: 4 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 2cad56c5
INFO: [Common 17-83] Releasing license: Synthesis
74 Infos, 119 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:54 ; elapsed = 00:00:51 . Memory (MB): peak = 2347.926 ; gain = 1070.258 ; free physical = 3454 ; free virtual = 26161
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1998.631; main = 1748.348; forked = 399.175
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3221.500; main = 2347.895; forked = 969.652
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2411.922 ; gain = 63.996 ; free physical = 3458 ; free virtual = 26165
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 105e4cc7e
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2521.734 ; gain = 109.812 ; free physical = 3393 ; free virtual = 26101
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 105e4cc7e
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2768.672 ; gain = 0.000 ; free physical = 3122 ; free virtual = 25830
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 105e4cc7e
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.672 ; gain = 0.000 ; free physical = 3122 ; free virtual = 25830
Phase 1 Initialization | Checksum: 105e4cc7e
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.672 ; gain = 0.000 ; free physical = 3122 ; free virtual = 25830
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 105e4cc7e
Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2768.672 ; gain = 0.000 ; free physical = 3122 ; free virtual = 25830
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 105e4cc7e
Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2768.672 ; gain = 0.000 ; free physical = 3120 ; free virtual = 25828
Phase 2 Timer Update And Timing Data Collection | Checksum: 105e4cc7e
Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2768.672 ; gain = 0.000 ; free physical = 3120 ; free virtual = 25828
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 8 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: c751195a
Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2768.672 ; gain = 0.000 ; free physical = 3123 ; free virtual = 25831
Retarget | Checksum: c751195a
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 2 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: c751195a
Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2768.672 ; gain = 0.000 ; free physical = 3123 ; free virtual = 25831
Constant propagation | Checksum: c751195a
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: d05c018c
Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2768.672 ; gain = 0.000 ; free physical = 3122 ; free virtual = 25830
Sweep | Checksum: d05c018c
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 1 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: d05c018c
Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2800.688 ; gain = 32.016 ; free physical = 3120 ; free virtual = 25828
BUFG optimization | Checksum: d05c018c
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: d05c018c
Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2800.688 ; gain = 32.016 ; free physical = 3119 ; free virtual = 25827
Shift Register Optimization | Checksum: d05c018c
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 126e560c2
Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2800.688 ; gain = 32.016 ; free physical = 3117 ; free virtual = 25825
Post Processing Netlist | Checksum: 126e560c2
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1dd117c22
Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2800.688 ; gain = 32.016 ; free physical = 3117 ; free virtual = 25825
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.688 ; gain = 0.000 ; free physical = 3117 ; free virtual = 25825
Phase 9.2 Verifying Netlist Connectivity | Checksum: 1dd117c22
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2800.688 ; gain = 32.016 ; free physical = 3117 ; free virtual = 25825
Phase 9 Finalization | Checksum: 1dd117c22
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2800.688 ; gain = 32.016 ; free physical = 3117 ; free virtual = 25825
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 2 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 8 | 1 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 1dd117c22
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2800.688 ; gain = 32.016 ; free physical = 3117 ; free virtual = 25825
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.688 ; gain = 0.000 ; free physical = 3117 ; free virtual = 25825
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1dd117c22
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.688 ; gain = 0.000 ; free physical = 3118 ; free virtual = 25826
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1dd117c22
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.688 ; gain = 0.000 ; free physical = 3118 ; free virtual = 25826
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.688 ; gain = 0.000 ; free physical = 3118 ; free virtual = 25826
Ending Netlist Obfuscation Task | Checksum: 1dd117c22
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.688 ; gain = 0.000 ; free physical = 3118 ; free virtual = 25826
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2800.688 ; gain = 452.762 ; free physical = 3118 ; free virtual = 25826
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2832.703 ; gain = 0.000 ; free physical = 3117 ; free virtual = 25825
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 130b01abc
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2832.703 ; gain = 0.000 ; free physical = 3117 ; free virtual = 25825
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2832.703 ; gain = 0.000 ; free physical = 3117 ; free virtual = 25825
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Info: at iteration #15: temp = 0.000000, timing cost = 10728, wirelen = 40777
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f76724fb
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.91 . Memory (MB): peak = 2832.703 ; gain = 0.000 ; free physical = 3117 ; free virtual = 25825
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: f91e9462
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.730 ; gain = 7.027 ; free physical = 3114 ; free virtual = 25821
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: f91e9462
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.730 ; gain = 7.027 ; free physical = 3112 ; free virtual = 25819
Phase 1 Placer Initialization | Checksum: f91e9462
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.730 ; gain = 7.027 ; free physical = 3110 ; free virtual = 25818
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 153a46bcf
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.730 ; gain = 7.027 ; free physical = 3117 ; free virtual = 25824
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1d0eb1b7d
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.730 ; gain = 7.027 ; free physical = 3130 ; free virtual = 25838
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1d0eb1b7d
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.730 ; gain = 7.027 ; free physical = 3130 ; free virtual = 25838
Phase 2.4 Global Placement Core
Info: at iteration #16: temp = 0.000000, timing cost = 10191, wirelen = 40716
Info: SA placement time 28.07s
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1e0fe456a
Time (s): cpu = 00:00:14 ; elapsed = 00:00:04 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3014 ; free virtual = 25722
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 71 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 27 nets or LUTs. Breaked 0 LUT, combined 27 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 35.01 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 12.95 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.60 ns
Info: Slack histogram:
Info: legend: * represents 163 endpoint(s)
Info: + represents [1,163) endpoint(s)
Info: [ 11440, 12830) |+
Info: [ 12830, 14220) |+
Info: [ 14220, 15610) |**+
Info: [ 15610, 17000) |*****+
Info: [ 17000, 18390) |*****+
Info: [ 18390, 19780) |*+
Info: [ 19780, 21170) |****+
Info: [ 21170, 22560) |*************+
Info: [ 22560, 23950) |***********+
Info: [ 23950, 25340) |****+
Info: [ 25340, 26730) |********************************+
Info: [ 26730, 28120) |************************************************************
Info: [ 28120, 29510) |********************+
Info: [ 29510, 30900) |+
Info: [ 30900, 32290) |*+
Info: [ 32290, 33680) |**+
Info: [ 33680, 35070) |*+
Info: [ 35070, 36460) |+
Info: [ 36460, 37850) |+
Info: [ 37850, 39240) |+
Info: Checksum: 0xdea8d9eb
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 3154 ; free virtual = 25862
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 27 | 27 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 27 | 27 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 17563c468
Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3111 ; free virtual = 25819
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Phase 2.4 Global Placement Core | Checksum: 220001dff
Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3116 ; free virtual = 25824
Phase 2 Global Placement | Checksum: 220001dff
Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3116 ; free virtual = 25824
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 20a403ec0
Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3115 ; free virtual = 25823
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 12ca45ff8
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3115 ; free virtual = 25823
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 13b2d4308
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3115 ; free virtual = 25823
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1796c96ac
Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3115 ; free virtual = 25823
Phase 3.5 Small Shape Detail Placement
Info: Routing 66433 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 146 853 | 146 853 | 65760| 1.45 1.45|
Info: 2000 | 217 1782 | 71 929 | 65168| 0.37 1.82|
Info: 3000 | 318 2681 | 101 899 | 64986| 0.37 2.19|
Info: 4000 | 398 3601 | 80 920 | 64468| 0.35 2.54|
Phase 3.5 Small Shape Detail Placement | Checksum: 1798ffff3
Time (s): cpu = 00:00:20 ; elapsed = 00:00:07 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3113 ; free virtual = 25821
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1a8ef1000
Time (s): cpu = 00:00:20 ; elapsed = 00:00:07 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3113 ; free virtual = 25821
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 16a9fefa4
Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3113 ; free virtual = 25821
Phase 3 Detail Placement | Checksum: 16a9fefa4
Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3113 ; free virtual = 25821
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Info: 5000 | 494 4505 | 96 904 | 63668| 0.39 2.93|
Info: 6000 | 603 5396 | 109 891 | 63006| 0.49 3.42|
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1f138cc74
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
Info: 7000 | 700 6299 | 97 903 | 62751| 0.39 3.81|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.882 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1a9e2d7ff
Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 3105 ; free virtual = 25813
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1a9e2d7ff
Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 3105 ; free virtual = 25813
Phase 4.1.1.1 BUFG Insertion | Checksum: 1f138cc74
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3105 ; free virtual = 25813
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1f2c40495
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3105 ; free virtual = 25813
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3105 ; free virtual = 25813
Phase 4.1 Post Commit Optimization | Checksum: 1f2c40495
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3105 ; free virtual = 25813
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1f2c40495
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3105 ; free virtual = 25813
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 2x2|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1f2c40495
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3105 ; free virtual = 25813
Phase 4.3 Placer Reporting | Checksum: 1f2c40495
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3105 ; free virtual = 25813
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 3105 ; free virtual = 25813
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3105 ; free virtual = 25813
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ca941ac3
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3105 ; free virtual = 25813
Ending Placer Task | Checksum: d5518cc7
Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2847.734 ; gain = 15.031 ; free physical = 3105 ; free virtual = 25813
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 2847.734 ; gain = 47.047 ; free physical = 3105 ; free virtual = 25813
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
Info: 8000 | 779 7220 | 79 921 | 62099| 0.35 4.16|
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
Info: 9000 | 886 8113 | 107 893 | 61645| 0.32 4.47|
report_io: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 3104 ; free virtual = 25812
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 3104 ; free virtual = 25812
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
Info: 10000 | 991 9008 | 105 895 | 61072| 0.37 4.85|
Info: 11000 | 1067 9932 | 76 924 | 60286| 0.33 5.18|
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
Info: 12000 | 1177 10822 | 110 890 | 59901| 0.51 5.69|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 3910ec48 ConstDB: 0 ShapeSum: 9c40a07f RouteDB: 0
Info: 13000 | 1285 11714 | 108 892 | 59654| 0.45 6.14|
Info: 14000 | 1395 12604 | 110 890 | 59786| 0.43 6.57|
Info: 15000 | 1463 13536 | 68 932 | 59019| 0.29 6.86|
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
Info: 16000 | 1575 14424 | 112 888 | 58701| 0.29 7.15|
Info: 17000 | 1670 15329 | 95 905 | 58139| 0.31 7.46|
Info: 18000 | 1784 16215 | 114 886 | 57421| 0.34 7.80|
Info: 19000 | 1879 17120 | 95 905 | 57188| 0.33 8.13|
Info: 20000 | 1961 18038 | 82 918 | 56557| 0.33 8.46|
Info: 21000 | 2046 18953 | 85 915 | 55718| 0.32 8.78|
Info: 22000 | 2169 19830 | 123 877 | 55545| 0.38 9.16|
Info: 23000 | 2252 20747 | 83 917 | 55355| 0.38 9.54|
Info: 24000 | 2331 21668 | 79 921 | 55179| 0.36 9.90|
Info: 25000 | 2436 22563 | 105 895 | 54629| 0.37 10.26|
Info: 26000 | 2503 23496 | 67 933 | 54326| 0.33 10.59|
Info: 27000 | 2557 24442 | 54 946 | 54025| 0.30 10.90|
Info: 28000 | 2654 25345 | 97 903 | 53201| 0.34 11.23|
Info: 29000 | 2742 26257 | 88 912 | 52481| 0.35 11.58|
Info: 30000 | 2879 27120 | 137 863 | 53112| 0.57 12.16|
Info: 31000 | 2967 28032 | 88 912 | 52538| 0.48 12.64|
Info: 32000 | 3005 28994 | 38 962 | 51696| 0.34 12.98|
Info: 33000 | 3116 29883 | 111 889 | 51256| 0.38 13.36|
Info: 34000 | 3196 30803 | 80 920 | 50393| 0.38 13.74|
Info: 35000 | 3282 31717 | 86 914 | 49718| 0.35 14.09|
Info: 36000 | 3389 32610 | 107 893 | 49196| 0.35 14.45|
Info: 37000 | 3528 33471 | 139 861 | 48595| 0.36 14.81|
Info: 38000 | 3710 34289 | 182 818 | 48336| 0.40 15.22|
Info: 39000 | 3838 35161 | 128 872 | 47497| 0.33 15.55|
Info: 40000 | 3954 36045 | 116 884 | 47099| 0.38 15.92|
Info: 41000 | 4056 36943 | 102 898 | 46346| 0.33 16.26|
Info: 42000 | 4177 37822 | 121 879 | 45670| 0.35 16.61|
[70%] Routing Phase 1 completed
Info: 43000 | 4271 38728 | 94 906 | 45278| 0.34 16.95|
Info: 44000 | 4363 39636 | 92 908 | 46150| 0.38 17.33|
Info: 45000 | 4433 40566 | 70 930 | 45876| 0.40 17.73|
Info: 46000 | 4472 41527 | 39 961 | 44918| 0.35 18.08|
Info: 47000 | 4589 42410 | 117 883 | 45392| 0.37 18.44|
Info: 48000 | 4651 43348 | 62 938 | 44569| 0.34 18.79|
Info: 49000 | 4821 44178 | 170 830 | 43919| 0.38 19.16|
Info: 50000 | 4948 45051 | 127 873 | 43341| 0.36 19.52|
Info: 51000 | 5046 45953 | 98 902 | 43935| 0.39 19.91|
Info: 52000 | 5073 46926 | 27 973 | 43135| 0.39 20.31|
Info: 53000 | 5174 47825 | 101 899 | 42574| 0.37 20.68|
Info: 54000 | 5286 48713 | 112 888 | 41882| 0.36 21.04|
Info: 55000 | 5427 49572 | 141 859 | 41308| 0.36 21.40|
Info: 56000 | 5541 50458 | 114 886 | 40753| 0.36 21.76|
Info: 57000 | 5666 51333 | 125 875 | 39968| 0.36 22.11|
Info: 58000 | 5787 52212 | 121 879 | 39425| 0.39 22.50|
Info: 59000 | 5919 53080 | 132 868 | 38698| 0.37 22.87|
Info: 60000 | 6104 53895 | 185 815 | 38197| 0.41 23.28|
Info: 61000 | 6241 54758 | 137 863 | 37444| 0.36 23.64|
Info: 62000 | 6344 55655 | 103 897 | 37089| 0.37 24.02|
Info: 63000 | 6404 56595 | 60 940 | 36698| 0.34 24.36|
Info: 64000 | 6539 57460 | 135 865 | 36328| 0.38 24.74|
Info: 65000 | 6668 58331 | 129 871 | 35900| 0.40 25.14|
Info: 66000 | 6804 59195 | 136 864 | 35662| 0.41 25.55|
Info: 67000 | 6867 60132 | 63 937 | 35533| 0.40 25.95|
Info: 68000 | 7019 60980 | 152 848 | 35348| 0.40 26.35|
Info: 69000 | 7137 61862 | 118 882 | 35026| 0.40 26.74|
Info: 70000 | 7275 62724 | 138 862 | 34341| 0.39 27.14|
Info: 71000 | 7377 63622 | 102 898 | 34001| 0.38 27.51|
Info: 72000 | 7565 64434 | 188 812 | 33365| 0.40 27.92|
Info: 73000 | 7829 65170 | 264 736 | 33324| 0.50 28.42|
Info: 74000 | 7986 66013 | 157 843 | 32623| 0.41 28.83|
[80%] Routing Phase 2 completed
Info: 75000 | 8065 66934 | 79 921 | 33832| 0.40 29.23|
Info: 76000 | 8081 67918 | 16 984 | 32861| 0.38 29.60|
Info: 77000 | 8231 68768 | 150 850 | 32086| 0.39 29.99|
Info: 78000 | 8399 69600 | 168 832 | 31622| 0.39 30.38|
Info: 79000 | 8591 70408 | 192 808 | 30875| 0.41 30.79|
Info: 80000 | 8818 71181 | 227 773 | 30337| 0.44 31.23|
Info: 81000 | 9066 71933 | 248 752 | 29767| 0.48 31.71|
Info: 82000 | 9314 72685 | 248 752 | 29164| 0.42 32.13|
Info: 83000 | 9597 73402 | 283 717 | 28929| 0.45 32.58|
Info: 84000 | 9935 74064 | 338 662 | 28494| 0.44 33.02|
Info: 85000 | 10220 74779 | 285 715 | 28397| 0.52 33.54|
Info: 86000 | 10429 75570 | 209 791 | 29157| 0.65 34.18|
Info: 87000 | 10556 76443 | 127 873 | 28532| 0.53 34.72|
Info: 88000 | 10700 77299 | 144 856 | 29863| 0.55 35.26|
Info: 89000 | 10776 78223 | 76 924 | 29288| 0.42 35.68|
Info: 90000 | 10862 79137 | 86 914 | 28593| 0.58 36.26|
Info: 91000 | 11085 79914 | 223 777 | 27952| 0.61 36.88|
Info: 92000 | 11331 80668 | 246 754 | 28859| 0.51 37.38|
Info: 93000 | 11401 81598 | 70 930 | 27975| 0.42 37.81|
Post Restoration Checksum: NetGraph: 411f1306 | NumContArr: e34b1284 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2a9bc1ac4
Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 3020 ; free virtual = 25729
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2a9bc1ac4
Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 3020 ; free virtual = 25728
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2a9bc1ac4
Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 3020 ; free virtual = 25728
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2d66eb66d
Time (s): cpu = 00:00:39 ; elapsed = 00:00:30 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2997 ; free virtual = 25706
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 |
Router Utilization Summary
Global Vertical Routing Utilization = 0.000391696 %
Global Horizontal Routing Utilization = 0.000639386 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 3568
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 3564
Number of Partially Routed Nets = 4
Number of Node Overlaps = 2
Phase 2 Router Initialization | Checksum: 3338cb7c9
Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2991 ; free virtual = 25699
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 3338cb7c9
Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2991 ; free virtual = 25699
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 1cbb2d3c9
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2980 ; free virtual = 25689
Phase 3 Initial Routing | Checksum: 1cbb2d3c9
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2983 ; free virtual = 25691
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 493
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.540 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1fc6c14ca
Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25681
Phase 4 Rip-up And Reroute | Checksum: 1fc6c14ca
Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25681
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1fc6c14ca
Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25681
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1fc6c14ca
Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25681
Phase 5 Delay and Skew Optimization | Checksum: 1fc6c14ca
Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25681
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 181650c03
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25681
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 181650c03
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25681
Phase 6 Post Hold Fix | Checksum: 181650c03
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25681
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.763764 %
Global Horizontal Routing Utilization = 0.966823 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 181650c03
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25681
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 181650c03
Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25680
Phase 9 Depositing Routes
Info: 94000 | 11672 82327 | 271 729 | 27373| 0.60 38.41|
Phase 9 Depositing Routes | Checksum: 21c8133ba
Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25681
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 21c8133ba
Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25681
INFO: [Route 35-16] Router Completed Successfully
Info: 95000 | 12058 82941 | 386 614 | 26933| 0.48 38.89|
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 20b5d0693
Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2972 ; free virtual = 25681
Ending Routing Task | Checksum: 20b5d0693
Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2973 ; free virtual = 25681
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:34 . Memory (MB): peak = 2847.734 ; gain = 0.000 ; free physical = 2973 ; free virtual = 25681
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Info: 96000 | 12451 83548 | 393 607 | 26471| 0.64 39.52|
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (2062)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (6725)
5. checking no_input_delay (9)
6. checking no_output_delay (17)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (2062)
---------------------------
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[36]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[37]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[39]/Q (HIGH)
There are 2050 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (6725)
---------------------------------------------------
There are 6725 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (9)
------------------------------
There are 9 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (17)
--------------------------------
There are 17 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Info: 97000 | 12844 84155 | 393 607 | 26173| 0.57 40.09|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
Info: 98000 | 13196 84803 | 352 648 | 25974| 0.47 40.56|
INFO: [DRC 23-27] Running DRC with 8 threads
Info: 99000 | 13565 85434 | 369 631 | 25565| 0.53 41.09|
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Info: 100000 | 13976 86023 | 411 589 | 25170| 0.55 41.64|
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Info: 101000 | 14300 86699 | 324 676 | 24820| 0.58 42.22|
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Info: 102000 | 14523 87476 | 223 777 | 24833| 0.63 42.85|
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
Info: 103000 | 14887 88112 | 364 636 | 24383| 0.47 43.32|
WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
Info: 104000 | 15344 88655 | 457 543 | 24090| 0.48 43.80|
Info: 105000 | 15819 89180 | 475 525 | 23715| 0.46 44.26|
Info: 106000 | 16304 89695 | 485 515 | 23368| 0.47 44.73|
Info: 107000 | 16787 90212 | 483 517 | 23000| 0.47 45.20|
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Info: 108000 | 17229 90770 | 442 558 | 22645| 0.49 45.69|
Info: 109000 | 17699 91300 | 470 530 | 22417| 0.49 46.18|
Info: 110000 | 18129 91868 | 430 568 | 22011| 0.42 46.61|
Info: 111000 | 18573 92423 | 444 555 | 21650| 0.46 47.06|
Info: 112000 | 18983 93012 | 410 589 | 21390| 0.43 47.50|
Info: 113000 | 19458 93529 | 475 517 | 21016| 0.47 47.97|
Info: 114000 | 19733 94252 | 275 723 | 20935| 0.55 48.51|
Info: 115000 | 20130 94836 | 397 584 | 20395| 0.38 48.89|
Info: 116000 | 20208 95756 | 78 920 | 20433| 0.45 49.34|
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Info: 117000 | 20440 96480 | 232 724 | 19803| 0.37 49.71|
Info: 118000 | 20710 97144 | 270 664 | 19163| 0.31 50.02|
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Sat May 18 02:07:15 2024
Info: 119000 | 21015 97759 | 305 615 | 18500| 0.30 50.32|
[Pipeline] }
Info: 120000 | 21391 98329 | 376 570 | 17929| 0.36 50.69|
[Pipeline] // stage
[Pipeline] }
Info: 121000 | 21736 98905 | 345 576 | 17353| 0.36 51.05|
Info: 122000 | 22127 99460 | 391 555 | 16800| 0.34 51.39|
Info: 123000 | 22541 99999 | 414 539 | 16355| 0.41 51.80|
Info: 124000 | 22951 100521 | 410 522 | 15836| 0.39 52.19|
Info: 125000 | 23430 100962 | 479 441 | 15406| 0.41 52.60|
Info: 126000 | 23794 101530 | 364 568 | 15038| 0.43 53.03|
Info: 127000 | 24237 102016 | 443 486 | 14524| 0.46 53.48|
Info: 128000 | 24620 102560 | 383 544 | 13921| 0.45 53.93|
Info: 129000 | 24823 103276 | 203 716 | 13137| 0.26 54.19|
Info: 130000 | 24939 104077 | 116 801 | 12287| 0.24 54.43|
Info: 131000 | 25055 104928 | 116 851 | 11408| 0.22 54.65|
Info: 132000 | 25067 105908 | 12 980 | 10421| 0.16 54.81|
Info: 133000 | 25073 106898 | 6 990 | 9427| 0.15 54.96|
Info: 134000 | 25080 107885 | 7 987 | 8434| 0.15 55.11|
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[39]_1[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Info: 135000 | 25089 108875 | 9 990 | 7443| 0.14 55.25|
Info: 136000 | 25090 109874 | 1 999 | 6444| 0.14 55.39|
Info: 137000 | 25097 110867 | 7 993 | 5453| 0.15 55.54|
Info: 138000 | 25102 111862 | 5 995 | 4458| 0.15 55.69|
Info: 139000 | 25108 112856 | 6 994 | 3464| 0.15 55.84|
Info: 140000 | 25113 113847 | 5 991 | 2470| 0.16 56.00|
Info: 141000 | 25177 114757 | 64 910 | 1551| 0.25 56.25|
Info: 142000 | 25346 115544 | 169 787 | 748| 0.35 56.60|
Info: 142781 | 25370 115937 | 24 393 | 0| 0.26 56.86|
Info: Routing complete.
Info: Router1 time 56.86s
Info: Checksum: 0xaf386bbc
Loading site data...
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_2.Q
Info: 1.2 1.7 Net SOC.Core.Control_Unit.state[3] (32,39) -> (30,42)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.0 Source SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z.F
Info: 0.6 2.6 Net SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D[2] (30,42) -> (30,42)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.8 Source SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D_LUT4_D.F
Info: 0.9 3.7 Net SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_B_Z_LUT4_Z_D[3] (30,42) -> (32,40)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.9 Source SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z_LUT4_Z.F
Info: 1.4 5.3 Net SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z[0] (32,40) -> (30,26)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z_LUT4_B.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.6 Source SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z_LUT4_B.F
Info: 2.0 7.6 Net SOC.Memory.memory.0.868_DO_LUT4_A_Z_LUT4_Z_C[2] (30,26) -> (20,16)
Info: Sink SOC.Memory.address_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 7.8 Source SOC.Memory.address_LUT4_Z_2.F
Info: 2.3 10.1 Net SOC.address[3] (20,16) -> (2,8)
Info: Sink SOC.Memory.memory.0.681$DPRAM_COMB3.B
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.5-22.18
Info: 0.2 10.4 Source SOC.Memory.memory.0.681$DPRAM_COMB3.F
Info: 0.6 11.0 Net SOC.Memory.memory.0.681_DO[1] (2,8) -> (2,8)
Info: Sink SOC.Memory.memory.0.641_DO_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 11.2 Source SOC.Memory.memory.0.641_DO_LUT4_Z.F
Info: 0.7 11.9 Net SOC.Memory.memory.0.641_DO[4] (2,8) -> (3,7)
Info: Sink SOC.Memory.memory.0.649_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 12.2 Source SOC.Memory.memory.0.649_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.6 12.8 Net SOC.Memory.memory.0.649_DO_LUT4_A_Z[3] (3,7) -> (4,7)
Info: Sink SOC.Memory.memory.0.649_DO_LUT4_A_Z_LUT4_B.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.0 Source SOC.Memory.memory.0.649_DO_LUT4_A_Z_LUT4_B.F
Info: 0.8 13.9 Net SOC.Memory.memory.0.753_DO_LUT4_A_Z_LUT4_B_Z[2] (4,7) -> (7,7)
Info: Sink SOC.Memory.memory.0.753_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 14.3 Source SOC.Memory.memory.0.753_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B.OFX
Info: 1.5 15.8 Net SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_C[4] (7,7) -> (9,18)
Info: Sink SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 16.0 Source SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 16.0 Net SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1 (9,18) -> (9,18)
Info: Sink SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 16.3 Source SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 2.4 18.7 Net SOC.Core.read_data_LUT4_Z_10_D[2] (9,18) -> (30,28)
Info: Sink SOC.Memory.memory.0.615_DO_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 19.0 Source SOC.Memory.memory.0.615_DO_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 2.7 21.6 Net SOC.Core.read_data_L6MUX21_Z_2_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] (30,28) -> (54,16)
Info: Sink SOC.Core.read_data_PFUMX_Z_3_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 21.9 Source SOC.Core.read_data_PFUMX_Z_3_BLUT_LUT4_Z.OFX
Info: 0.5 22.4 Net SOC.read_data[19] (54,16) -> (54,16)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_12.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:21.34-21.43
Info: 0.0 22.4 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_12.M
Info: 4.1 ns logic, 18.3 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[0]$tr_io.O
Info: 2.9 2.9 Net gpios[0]$TRELLIS_IO_IN (0,44) -> (6,23)
Info: Sink SOC.GPIOS.Gpios[0].direction_LUT4_C.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 3.2 Source SOC.GPIOS.Gpios[0].direction_LUT4_C.F
Info: 1.3 4.5 Net SOC.GPIOS.Gpios[0].direction_LUT4_C_Z[2] (6,23) -> (6,16)
Info: Sink SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_LUT4_C.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.7 Source SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_LUT4_C.F
Info: 1.9 6.6 Net SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_LUT4_C_Z[1] (6,16) -> (22,12)
Info: Sink SOC.Core.read_data_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.9 Source SOC.Core.read_data_LUT4_Z.F
Info: 1.9 8.7 Net SOC.read_data[0] (22,12) -> (31,21)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:21.34-21.43
Info: 0.0 8.7 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info: 0.7 ns logic, 8.0 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_27.Q
Info: 2.9 3.4 Net SOC.Leds.data[4] (5,24) -> (6,54)
Info: Sink led_LUT4_Z_3.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: 0.2 3.7 Source led_LUT4_Z_3.F
Info: 2.3 6.0 Net led[4]$TRELLIS_IO_OUT (6,54) -> (15,71)
Info: Sink led[4]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.3 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 44.71 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.74 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.02 ns
Info: Slack histogram:
Info: legend: * represents 202 endpoint(s)
Info: + represents [1,202) endpoint(s)
Info: [ 17634, 18706) |+
Info: [ 18706, 19778) |*+
Info: [ 19778, 20850) |****+
Info: [ 20850, 21922) |****+
Info: [ 21922, 22994) |+
Info: [ 22994, 24066) |*+
Info: [ 24066, 25138) |****+
Info: [ 25138, 26210) |************+
Info: [ 26210, 27282) |********+
Info: [ 27282, 28354) |**+
Info: [ 28354, 29426) |***************+
Info: [ 29426, 30498) |************************************************************
Info: [ 30498, 31570) |***************+
Info: [ 31570, 32642) |+
Info: [ 32642, 33714) |+
Info: [ 33714, 34786) |*+
Info: [ 34786, 35858) |**+
Info: [ 35858, 36930) |+
Info: [ 36930, 38002) |+
Info: [ 38002, 39074) |+
Loading route data...
Processing options...
Creating bitmap...
Info: Program finished normally.
[Pipeline] }
Creating bitstream...
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
Writing bitstream ./build/out.bit...
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 3152.723 ; gain = 248.145 ; free physical = 3239 ; free virtual = 26000
INFO: [Common 17-206] Exiting Vivado at Sat May 18 02:07:27 2024...
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
[Pipeline] }
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
unable to open ftdi device: -3 (device not found)
empty
JTAG init failed with: unable to open ftdi device
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
Loading: [==== ] 8.00%[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
Loading: [======== ] 16.00%[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Loading: [============ ] 23.99%Failed in branch openFPGAloader Nexys 4 DDR
Sending interrupt signal to process
Terminated
script returned exit code 143
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch openFPGAloader ECP5
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
Stage "Testes" skipped due to earlier failure(s)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
Stage "ECP5 - Testes" skipped due to earlier failure(s)
[Pipeline] }
Stage "TangNano - Testes" skipped due to earlier failure(s)
[Pipeline] }
Stage "Nexys 4 - Testes" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch ECP5 - Testes
[Pipeline] }
Failed in branch TangNano - Testes
[Pipeline] }
Failed in branch Nexys 4 - Testes
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE
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