Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 13076/43848 29%
Info: logic LUTs: 6500/43848 14%
Info: carry LUTs: 120/43848 0%
Info: RAM LUTs: 4304/ 5481 78%
Info: RAMW LUTs: 2152/10962 19%
Info: Total DFFs: 704/43848 1%
Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 229 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x4613b3cc
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 704/43848 1%
Info: TRELLIS_COMB: 13126/43848 29%
Info: TRELLIS_RAMW: 1076/ 5481 19%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 6237 cells, random placement wirelen = 570079.
Info: at initial placer iter 0, wirelen = 2865
Info: at initial placer iter 1, wirelen = 2252
Info: at initial placer iter 2, wirelen = 1718
Info: at initial placer iter 3, wirelen = 1684
Info: Running main analytical placer, max placement attempts per cell = 27844453.
Info: at iteration #1, type ALL: wirelen solved = 1668, spread = 101886, legal = 102720; time = 0.41s
Info: at iteration #2, type ALL: wirelen solved = 7496, spread = 71010, legal = 72193; time = 0.56s
Info: at iteration #3, type ALL: wirelen solved = 13000, spread = 66620, legal = 67656; time = 0.43s
Info: at iteration #4, type ALL: wirelen solved = 19007, spread = 63531, legal = 64668; time = 0.41s
Info: at iteration #5, type ALL: wirelen solved = 21184, spread = 59230, legal = 60767; time = 0.41s
Info: at iteration #6, type ALL: wirelen solved = 24007, spread = 57386, legal = 58817; time = 0.50s
Info: at iteration #7, type ALL: wirelen solved = 25389, spread = 54164, legal = 55815; time = 0.42s
Info: at iteration #8, type ALL: wirelen solved = 27290, spread = 53364, legal = 54718; time = 0.39s
Info: at iteration #9, type ALL: wirelen solved = 28822, spread = 52112, legal = 53538; time = 0.38s
Info: at iteration #10, type ALL: wirelen solved = 29707, spread = 50985, legal = 52581; time = 0.38s
Info: at iteration #11, type ALL: wirelen solved = 30125, spread = 50117, legal = 51663; time = 0.52s
Info: at iteration #12, type ALL: wirelen solved = 31234, spread = 50397, legal = 52010; time = 0.40s
Info: at iteration #13, type ALL: wirelen solved = 32325, spread = 48489, legal = 50206; time = 0.43s
Info: at iteration #14, type ALL: wirelen solved = 32079, spread = 48768, legal = 50338; time = 0.41s
Info: at iteration #15, type ALL: wirelen solved = 32860, spread = 48839, legal = 50338; time = 0.45s
Info: at iteration #16, type ALL: wirelen solved = 33864, spread = 49642, legal = 51086; time = 0.47s
Info: at iteration #17, type ALL: wirelen solved = 34870, spread = 48462, legal = 50067; time = 0.39s
Info: at iteration #18, type ALL: wirelen solved = 34731, spread = 47436, legal = 48958; time = 0.36s
Info: at iteration #19, type ALL: wirelen solved = 34815, spread = 47406, legal = 49136; time = 0.37s
Info: at iteration #20, type ALL: wirelen solved = 34898, spread = 46880, legal = 48465; time = 0.53s
Info: at iteration #21, type ALL: wirelen solved = 34803, spread = 46487, legal = 48051; time = 0.37s
Info: at iteration #22, type ALL: wirelen solved = 34902, spread = 46174, legal = 47993; time = 0.38s
Info: at iteration #23, type ALL: wirelen solved = 35135, spread = 45696, legal = 47439; time = 0.38s
Info: at iteration #24, type ALL: wirelen solved = 35198, spread = 45462, legal = 47321; time = 0.37s
Info: at iteration #25, type ALL: wirelen solved = 35360, spread = 45512, legal = 47193; time = 0.53s
Info: at iteration #26, type ALL: wirelen solved = 35640, spread = 45414, legal = 47282; time = 0.37s
Info: at iteration #27, type ALL: wirelen solved = 35692, spread = 45270, legal = 46965; time = 0.36s
Info: at iteration #28, type ALL: wirelen solved = 35706, spread = 46115, legal = 47745; time = 0.38s
Info: at iteration #29, type ALL: wirelen solved = 36346, spread = 45894, legal = 47610; time = 0.38s
Info: at iteration #30, type ALL: wirelen solved = 36349, spread = 46727, legal = 48286; time = 0.51s
Info: at iteration #31, type ALL: wirelen solved = 36890, spread = 46387, legal = 47843; time = 0.37s
Info: at iteration #32, type ALL: wirelen solved = 37226, spread = 45981, legal = 47625; time = 0.37s
Info: HeAP Placer Time: 20.47s
Info: of which solving equations: 11.96s
Info: of which spreading cells: 1.58s
Info: of which strict legalisation: 0.46s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 9739, wirelen = 46965
Info: at iteration #5: temp = 0.000000, timing cost = 9648, wirelen = 42779
Info: at iteration #10: temp = 0.000000, timing cost = 10193, wirelen = 41294
Info: at iteration #15: temp = 0.000000, timing cost = 10728, wirelen = 40777
Info: at iteration #16: temp = 0.000000, timing cost = 10191, wirelen = 40716
Info: SA placement time 28.46s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 35.01 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 12.95 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.60 ns
Info: Slack histogram:
Info: legend: * represents 163 endpoint(s)
Info: + represents [1,163) endpoint(s)
Info: [ 11440, 12830) |+
Info: [ 12830, 14220) |+
Info: [ 14220, 15610) |**+
Info: [ 15610, 17000) |*****+
Info: [ 17000, 18390) |*****+
Info: [ 18390, 19780) |*+
Info: [ 19780, 21170) |****+
Info: [ 21170, 22560) |*************+
Info: [ 22560, 23950) |***********+
Info: [ 23950, 25340) |****+
Info: [ 25340, 26730) |********************************+
Info: [ 26730, 28120) |************************************************************
Info: [ 28120, 29510) |********************+
Info: [ 29510, 30900) |+
Info: [ 30900, 32290) |*+
Info: [ 32290, 33680) |**+
Info: [ 33680, 35070) |*+
Info: [ 35070, 36460) |+
Info: [ 36460, 37850) |+
Info: [ 37850, 39240) |+
Info: Checksum: 0xdea8d9eb
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 66433 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 146 853 | 146 853 | 65760| 1.47 1.47|
Info: 2000 | 217 1782 | 71 929 | 65168| 0.38 1.86|
Info: 3000 | 318 2681 | 101 899 | 64986| 0.40 2.26|
Info: 4000 | 398 3601 | 80 920 | 64468| 0.35 2.60|
Info: 5000 | 494 4505 | 96 904 | 63668| 0.33 2.93|
Info: 6000 | 603 5396 | 109 891 | 63006| 0.45 3.38|
Info: 7000 | 700 6299 | 97 903 | 62751| 0.43 3.81|
Info: 8000 | 779 7220 | 79 921 | 62099| 0.34 4.15|
Info: 9000 | 886 8113 | 107 893 | 61645| 0.33 4.48|
Info: 10000 | 991 9008 | 105 895 | 61072| 0.37 4.85|
Info: 11000 | 1067 9932 | 76 924 | 60286| 0.36 5.21|
Info: 12000 | 1177 10822 | 110 890 | 59901| 0.40 5.61|
Info: 13000 | 1285 11714 | 108 892 | 59654| 0.33 5.94|
Info: 14000 | 1395 12604 | 110 890 | 59786| 0.45 6.39|
Info: 15000 | 1463 13536 | 68 932 | 59019| 0.29 6.68|
Info: 16000 | 1575 14424 | 112 888 | 58701| 0.30 6.97|
Info: 17000 | 1670 15329 | 95 905 | 58139| 0.34 7.32|
Info: 18000 | 1784 16215 | 114 886 | 57421| 0.35 7.67|
Info: 19000 | 1879 17120 | 95 905 | 57188| 0.33 8.00|
Info: 20000 | 1961 18038 | 82 918 | 56557| 0.33 8.33|
Info: 21000 | 2046 18953 | 85 915 | 55718| 0.32 8.65|
Info: 22000 | 2169 19830 | 123 877 | 55545| 0.36 9.01|
Info: 23000 | 2252 20747 | 83 917 | 55355| 0.37 9.38|
Info: 24000 | 2331 21668 | 79 921 | 55179| 0.36 9.74|
Info: 25000 | 2436 22563 | 105 895 | 54629| 0.39 10.12|
Info: 26000 | 2503 23496 | 67 933 | 54326| 0.34 10.47|
Info: 27000 | 2557 24442 | 54 946 | 54025| 0.31 10.77|
Info: 28000 | 2654 25345 | 97 903 | 53201| 0.33 11.11|
Info: 29000 | 2742 26257 | 88 912 | 52481| 0.33 11.44|
Info: 30000 | 2879 27120 | 137 863 | 53112| 0.47 11.91|
Info: 31000 | 2967 28032 | 88 912 | 52538| 0.73 12.64|
Info: 32000 | 3005 28994 | 38 962 | 51696| 0.49 13.12|
Info: 33000 | 3116 29883 | 111 889 | 51256| 0.44 13.57|
Info: 34000 | 3196 30803 | 80 920 | 50393| 0.39 13.96|
Info: 35000 | 3282 31717 | 86 914 | 49718| 0.35 14.31|
Info: 36000 | 3389 32610 | 107 893 | 49196| 0.33 14.64|
Info: 37000 | 3528 33471 | 139 861 | 48595| 0.34 14.97|
Info: 38000 | 3710 34289 | 182 818 | 48336| 0.41 15.38|
Info: 39000 | 3838 35161 | 128 872 | 47497| 0.34 15.72|
Info: 40000 | 3954 36045 | 116 884 | 47099| 0.40 16.12|
Info: 41000 | 4056 36943 | 102 898 | 46346| 0.35 16.48|
Info: 42000 | 4177 37822 | 121 879 | 45670| 0.36 16.84|
Info: 43000 | 4271 38728 | 94 906 | 45278| 0.34 17.18|
Info: 44000 | 4363 39636 | 92 908 | 46150| 0.35 17.53|
Info: 45000 | 4433 40566 | 70 930 | 45876| 0.38 17.92|
Info: 46000 | 4472 41527 | 39 961 | 44918| 0.36 18.27|
Info: 47000 | 4589 42410 | 117 883 | 45392| 0.39 18.67|
Info: 48000 | 4651 43348 | 62 938 | 44569| 0.37 19.03|
Info: 49000 | 4821 44178 | 170 830 | 43919| 0.38 19.41|
Info: 50000 | 4948 45051 | 127 873 | 43341| 0.35 19.77|
Info: 51000 | 5046 45953 | 98 902 | 43935| 0.37 20.14|
Info: 52000 | 5073 46926 | 27 973 | 43135| 0.37 20.50|
Info: 53000 | 5174 47825 | 101 899 | 42574| 0.37 20.87|
Info: 54000 | 5286 48713 | 112 888 | 41882| 0.37 21.24|
Info: 55000 | 5427 49572 | 141 859 | 41308| 0.38 21.62|
Info: 56000 | 5541 50458 | 114 886 | 40753| 0.38 22.00|
Info: 57000 | 5666 51333 | 125 875 | 39968| 0.36 22.36|
Info: 58000 | 5787 52212 | 121 879 | 39425| 0.37 22.73|
Info: 59000 | 5919 53080 | 132 868 | 38698| 0.35 23.08|
Info: 60000 | 6104 53895 | 185 815 | 38197| 0.40 23.48|
Info: 61000 | 6241 54758 | 137 863 | 37444| 0.36 23.84|
Info: 62000 | 6344 55655 | 103 897 | 37089| 0.39 24.23|
Info: 63000 | 6404 56595 | 60 940 | 36698| 0.35 24.59|
Info: 64000 | 6539 57460 | 135 865 | 36328| 0.39 24.98|
Info: 65000 | 6668 58331 | 129 871 | 35900| 0.40 25.38|
Info: 66000 | 6804 59195 | 136 864 | 35662| 0.39 25.77|
Info: 67000 | 6867 60132 | 63 937 | 35533| 0.39 26.15|
Info: 68000 | 7019 60980 | 152 848 | 35348| 0.40 26.55|
Info: 69000 | 7137 61862 | 118 882 | 35026| 0.43 26.98|
Info: 70000 | 7275 62724 | 138 862 | 34341| 0.42 27.40|
Info: 71000 | 7377 63622 | 102 898 | 34001| 0.38 27.78|
Info: 72000 | 7565 64434 | 188 812 | 33365| 0.39 28.17|
Info: 73000 | 7829 65170 | 264 736 | 33324| 0.47 28.64|
Info: 74000 | 7986 66013 | 157 843 | 32623| 0.42 29.05|
Info: 75000 | 8065 66934 | 79 921 | 33832| 0.41 29.47|
Info: 76000 | 8081 67918 | 16 984 | 32861| 0.40 29.87|
Info: 77000 | 8231 68768 | 150 850 | 32086| 0.40 30.26|
Info: 78000 | 8399 69600 | 168 832 | 31622| 0.39 30.66|
Info: 79000 | 8591 70408 | 192 808 | 30875| 0.39 31.04|
Info: 80000 | 8818 71181 | 227 773 | 30337| 0.42 31.47|
Info: 81000 | 9066 71933 | 248 752 | 29767| 0.48 31.95|
Info: 82000 | 9314 72685 | 248 752 | 29164| 0.43 32.38|
Info: 83000 | 9597 73402 | 283 717 | 28929| 0.52 32.89|
Info: 84000 | 9935 74064 | 338 662 | 28494| 0.59 33.48|
Info: 85000 | 10220 74779 | 285 715 | 28397| 0.61 34.09|
Info: 86000 | 10429 75570 | 209 791 | 29157| 0.54 34.63|
Info: 87000 | 10556 76443 | 127 873 | 28532| 0.53 35.16|
Info: 88000 | 10700 77299 | 144 856 | 29863| 0.65 35.81|
Info: 89000 | 10776 78223 | 76 924 | 29288| 0.54 36.36|
Info: 90000 | 10862 79137 | 86 914 | 28593| 0.44 36.80|
Info: 91000 | 11085 79914 | 223 777 | 27952| 0.51 37.31|
Info: 92000 | 11331 80668 | 246 754 | 28859| 0.47 37.78|
Info: 93000 | 11401 81598 | 70 930 | 27975| 0.55 38.33|
Info: 94000 | 11672 82327 | 271 729 | 27373| 0.61 38.94|
Info: 95000 | 12058 82941 | 386 614 | 26933| 0.54 39.48|
Info: 96000 | 12451 83548 | 393 607 | 26471| 0.49 39.97|
Info: 97000 | 12844 84155 | 393 607 | 26173| 0.47 40.43|
Info: 98000 | 13196 84803 | 352 648 | 25974| 0.52 40.96|
Info: 99000 | 13565 85434 | 369 631 | 25565| 0.59 41.55|
Info: 100000 | 13976 86023 | 411 589 | 25170| 0.56 42.11|
Info: 101000 | 14300 86699 | 324 676 | 24820| 0.50 42.60|
Info: 102000 | 14523 87476 | 223 777 | 24833| 0.50 43.11|
Info: 103000 | 14887 88112 | 364 636 | 24383| 0.44 43.55|
Info: 104000 | 15344 88655 | 457 543 | 24090| 0.50 44.05|
Info: 105000 | 15819 89180 | 475 525 | 23715| 0.48 44.53|
Info: 106000 | 16304 89695 | 485 515 | 23368| 0.47 45.00|
Info: 107000 | 16787 90212 | 483 517 | 23000| 0.45 45.46|
Info: 108000 | 17229 90770 | 442 558 | 22645| 0.47 45.93|
Info: 109000 | 17699 91300 | 470 530 | 22417| 0.50 46.43|
Info: 110000 | 18129 91868 | 430 568 | 22011| 0.46 46.89|
Info: 111000 | 18573 92423 | 444 555 | 21650| 0.47 47.36|
Info: 112000 | 18983 93012 | 410 589 | 21390| 0.43 47.79|
Info: 113000 | 19458 93529 | 475 517 | 21016| 0.45 48.24|
Info: 114000 | 19733 94252 | 275 723 | 20935| 0.53 48.77|
Info: 115000 | 20130 94836 | 397 584 | 20395| 0.39 49.16|
Info: 116000 | 20208 95756 | 78 920 | 20433| 0.49 49.65|
Info: 117000 | 20440 96480 | 232 724 | 19803| 0.38 50.03|
Info: 118000 | 20710 97144 | 270 664 | 19163| 0.31 50.34|
Info: 119000 | 21015 97759 | 305 615 | 18500| 0.31 50.66|
Info: 120000 | 21391 98329 | 376 570 | 17929| 0.34 50.99|
Info: 121000 | 21736 98905 | 345 576 | 17353| 0.35 51.34|
Info: 122000 | 22127 99460 | 391 555 | 16800| 0.34 51.69|
Info: 123000 | 22541 99999 | 414 539 | 16355| 0.43 52.12|
Info: 124000 | 22951 100521 | 410 522 | 15836| 0.41 52.53|
Info: 125000 | 23430 100962 | 479 441 | 15406| 0.50 53.03|
Info: 126000 | 23794 101530 | 364 568 | 15038| 0.48 53.51|
Info: 127000 | 24237 102016 | 443 486 | 14524| 0.41 53.92|
Info: 128000 | 24620 102560 | 383 544 | 13921| 0.36 54.27|
Info: 129000 | 24823 103276 | 203 716 | 13137| 0.26 54.54|
Info: 130000 | 24939 104077 | 116 801 | 12287| 0.24 54.78|
Info: 131000 | 25055 104928 | 116 851 | 11408| 0.23 55.00|
Info: 132000 | 25067 105908 | 12 980 | 10421| 0.16 55.16|
Info: 133000 | 25073 106898 | 6 990 | 9427| 0.14 55.31|
Info: 134000 | 25080 107885 | 7 987 | 8434| 0.14 55.45|
Info: 135000 | 25089 108875 | 9 990 | 7443| 0.14 55.59|
Info: 136000 | 25090 109874 | 1 999 | 6444| 0.14 55.73|
Info: 137000 | 25097 110867 | 7 993 | 5453| 0.15 55.88|
Info: 138000 | 25102 111862 | 5 995 | 4458| 0.14 56.02|
Info: 139000 | 25108 112856 | 6 994 | 3464| 0.15 56.17|
Info: 140000 | 25113 113847 | 5 991 | 2470| 0.16 56.32|
Info: 141000 | 25177 114757 | 64 910 | 1551| 0.23 56.56|
Info: 142000 | 25346 115544 | 169 787 | 748| 0.34 56.90|
Info: 142781 | 25370 115937 | 24 393 | 0| 0.33 57.23|
Info: Routing complete.
Info: Router1 time 57.23s
Info: Checksum: 0xaf386bbc
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_2.Q
Info: 1.2 1.7 Net SOC.Core.Control_Unit.state[3] (32,39) -> (30,42)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.0 Source SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z.F
Info: 0.6 2.6 Net SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D[2] (30,42) -> (30,42)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.8 Source SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D_LUT4_D.F
Info: 0.9 3.7 Net SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_B_Z_LUT4_Z_D[3] (30,42) -> (32,40)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.9 Source SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z_LUT4_Z.F
Info: 1.4 5.3 Net SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z[0] (32,40) -> (30,26)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z_LUT4_B.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.6 Source SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z_LUT4_B.F
Info: 2.0 7.6 Net SOC.Memory.memory.0.868_DO_LUT4_A_Z_LUT4_Z_C[2] (30,26) -> (20,16)
Info: Sink SOC.Memory.address_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 7.8 Source SOC.Memory.address_LUT4_Z_2.F
Info: 2.3 10.1 Net SOC.address[3] (20,16) -> (2,8)
Info: Sink SOC.Memory.memory.0.681$DPRAM_COMB3.B
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.5-22.18
Info: 0.2 10.4 Source SOC.Memory.memory.0.681$DPRAM_COMB3.F
Info: 0.6 11.0 Net SOC.Memory.memory.0.681_DO[1] (2,8) -> (2,8)
Info: Sink SOC.Memory.memory.0.641_DO_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 11.2 Source SOC.Memory.memory.0.641_DO_LUT4_Z.F
Info: 0.7 11.9 Net SOC.Memory.memory.0.641_DO[4] (2,8) -> (3,7)
Info: Sink SOC.Memory.memory.0.649_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 12.2 Source SOC.Memory.memory.0.649_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.6 12.8 Net SOC.Memory.memory.0.649_DO_LUT4_A_Z[3] (3,7) -> (4,7)
Info: Sink SOC.Memory.memory.0.649_DO_LUT4_A_Z_LUT4_B.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.0 Source SOC.Memory.memory.0.649_DO_LUT4_A_Z_LUT4_B.F
Info: 0.8 13.9 Net SOC.Memory.memory.0.753_DO_LUT4_A_Z_LUT4_B_Z[2] (4,7) -> (7,7)
Info: Sink SOC.Memory.memory.0.753_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 14.3 Source SOC.Memory.memory.0.753_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B.OFX
Info: 1.5 15.8 Net SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_C[4] (7,7) -> (9,18)
Info: Sink SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 16.0 Source SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 16.0 Net SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1 (9,18) -> (9,18)
Info: Sink SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 16.3 Source SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 2.4 18.7 Net SOC.Core.read_data_LUT4_Z_10_D[2] (9,18) -> (30,28)
Info: Sink SOC.Memory.memory.0.615_DO_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 19.0 Source SOC.Memory.memory.0.615_DO_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 2.7 21.6 Net SOC.Core.read_data_L6MUX21_Z_2_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] (30,28) -> (54,16)
Info: Sink SOC.Core.read_data_PFUMX_Z_3_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 21.9 Source SOC.Core.read_data_PFUMX_Z_3_BLUT_LUT4_Z.OFX
Info: 0.5 22.4 Net SOC.read_data[19] (54,16) -> (54,16)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_12.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:21.34-21.43
Info: 0.0 22.4 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_12.M
Info: 4.1 ns logic, 18.3 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[0]$tr_io.O
Info: 2.9 2.9 Net gpios[0]$TRELLIS_IO_IN (0,44) -> (6,23)
Info: Sink SOC.GPIOS.Gpios[0].direction_LUT4_C.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 3.2 Source SOC.GPIOS.Gpios[0].direction_LUT4_C.F
Info: 1.3 4.5 Net SOC.GPIOS.Gpios[0].direction_LUT4_C_Z[2] (6,23) -> (6,16)
Info: Sink SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_LUT4_C.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.7 Source SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_LUT4_C.F
Info: 1.9 6.6 Net SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_LUT4_C_Z[1] (6,16) -> (22,12)
Info: Sink SOC.Core.read_data_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.9 Source SOC.Core.read_data_LUT4_Z.F
Info: 1.9 8.7 Net SOC.read_data[0] (22,12) -> (31,21)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:21.34-21.43
Info: 0.0 8.7 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info: 0.7 ns logic, 8.0 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_27.Q
Info: 2.9 3.4 Net SOC.Leds.data[4] (5,24) -> (6,54)
Info: Sink led_LUT4_Z_3.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: 0.2 3.7 Source led_LUT4_Z_3.F
Info: 2.3 6.0 Net led[4]$TRELLIS_IO_OUT (6,54) -> (15,71)
Info: Sink led[4]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.3 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 44.71 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.74 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.02 ns
Info: Slack histogram:
Info: legend: * represents 202 endpoint(s)
Info: + represents [1,202) endpoint(s)
Info: [ 17634, 18706) |+
Info: [ 18706, 19778) |*+
Info: [ 19778, 20850) |****+
Info: [ 20850, 21922) |****+
Info: [ 21922, 22994) |+
Info: [ 22994, 24066) |*+
Info: [ 24066, 25138) |****+
Info: [ 25138, 26210) |************+
Info: [ 26210, 27282) |********+
Info: [ 27282, 28354) |**+
Info: [ 28354, 29426) |***************+
Info: [ 29426, 30498) |************************************************************
Info: [ 30498, 31570) |***************+
Info: [ 31570, 32642) |+
Info: [ 32642, 33714) |+
Info: [ 33714, 34786) |*+
Info: [ 34786, 35858) |**+
Info: [ 35858, 36930) |+
Info: [ 36930, 38002) |+
Info: [ 38002, 39074) |+
Info: Program finished normally.
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