Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 13137/43848 29%
Info: logic LUTs: 6547/43848 14%
Info: carry LUTs: 146/43848 0%
Info: RAM LUTs: 4296/ 5481 78%
Info: RAMW LUTs: 2148/10962 19%
Info: Total DFFs: 711/43848 1%
Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 249 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x989a6359
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 711/43848 1%
Info: TRELLIS_COMB: 13187/43848 30%
Info: TRELLIS_RAMW: 1074/ 5481 19%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 6297 cells, random placement wirelen = 570023.
Info: at initial placer iter 0, wirelen = 2341
Info: at initial placer iter 1, wirelen = 1746
Info: at initial placer iter 2, wirelen = 1797
Info: at initial placer iter 3, wirelen = 1808
Info: Running main analytical placer, max placement attempts per cell = 28091260.
Info: at iteration #1, type ALL: wirelen solved = 1789, spread = 88043, legal = 88716; time = 0.41s
Info: at iteration #2, type ALL: wirelen solved = 8222, spread = 72686, legal = 73858; time = 0.63s
Info: at iteration #3, type ALL: wirelen solved = 16150, spread = 70977, legal = 71634; time = 0.42s
Info: at iteration #4, type ALL: wirelen solved = 19803, spread = 60080, legal = 61549; time = 0.41s
Info: at iteration #5, type ALL: wirelen solved = 20583, spread = 59574, legal = 60646; time = 0.40s
Info: at iteration #6, type ALL: wirelen solved = 24140, spread = 54259, legal = 55540; time = 0.47s
Info: at iteration #7, type ALL: wirelen solved = 25335, spread = 51563, legal = 52796; time = 0.49s
Info: at iteration #8, type ALL: wirelen solved = 26213, spread = 51180, legal = 52489; time = 0.39s
Info: at iteration #9, type ALL: wirelen solved = 28638, spread = 50299, legal = 51833; time = 0.38s
Info: at iteration #10, type ALL: wirelen solved = 28380, spread = 49374, legal = 50909; time = 0.37s
Info: at iteration #11, type ALL: wirelen solved = 28483, spread = 49705, legal = 51066; time = 0.55s
Info: at iteration #12, type ALL: wirelen solved = 29181, spread = 50623, legal = 51701; time = 0.42s
Info: at iteration #13, type ALL: wirelen solved = 30428, spread = 48609, legal = 50095; time = 0.45s
Info: at iteration #14, type ALL: wirelen solved = 30280, spread = 48217, legal = 49887; time = 0.36s
Info: at iteration #15, type ALL: wirelen solved = 30629, spread = 50016, legal = 51141; time = 0.44s
Info: at iteration #16, type ALL: wirelen solved = 31960, spread = 49928, legal = 51146; time = 0.53s
Info: at iteration #17, type ALL: wirelen solved = 32775, spread = 49137, legal = 50442; time = 0.37s
Info: at iteration #18, type ALL: wirelen solved = 32636, spread = 48769, legal = 50016; time = 0.37s
Info: at iteration #19, type ALL: wirelen solved = 32785, spread = 48112, legal = 49511; time = 0.37s
Info: at iteration #20, type ALL: wirelen solved = 32493, spread = 48790, legal = 50079; time = 0.46s
Info: at iteration #21, type ALL: wirelen solved = 33652, spread = 48176, legal = 49487; time = 0.46s
Info: at iteration #22, type ALL: wirelen solved = 33158, spread = 47098, legal = 48745; time = 0.38s
Info: at iteration #23, type ALL: wirelen solved = 33345, spread = 46845, legal = 48411; time = 0.38s
Info: at iteration #24, type ALL: wirelen solved = 33201, spread = 46604, legal = 48212; time = 0.38s
Info: at iteration #25, type ALL: wirelen solved = 33458, spread = 46220, legal = 47907; time = 0.53s
Info: at iteration #26, type ALL: wirelen solved = 33283, spread = 46395, legal = 48107; time = 0.38s
Info: at iteration #27, type ALL: wirelen solved = 33346, spread = 47126, legal = 48613; time = 0.38s
Info: at iteration #28, type ALL: wirelen solved = 33907, spread = 48110, legal = 49353; time = 0.38s
Info: at iteration #29, type ALL: wirelen solved = 35076, spread = 47932, legal = 49439; time = 0.39s
Info: at iteration #30, type ALL: wirelen solved = 35320, spread = 46608, legal = 48161; time = 0.54s
Info: HeAP Placer Time: 19.64s
Info: of which solving equations: 11.58s
Info: of which spreading cells: 1.52s
Info: of which strict legalisation: 0.42s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 18686, wirelen = 47907
Info: at iteration #5: temp = 0.000000, timing cost = 11314, wirelen = 42540
Info: at iteration #10: temp = 0.000000, timing cost = 8162, wirelen = 41218
Info: at iteration #15: temp = 0.000000, timing cost = 7531, wirelen = 40517
Info: at iteration #20: temp = 0.000000, timing cost = 8846, wirelen = 40359
Info: at iteration #25: temp = 0.000000, timing cost = 7307, wirelen = 40282
Info: at iteration #29: temp = 0.000000, timing cost = 8779, wirelen = 40261
Info: SA placement time 50.25s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 31.23 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 10.23 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 9.56 ns
Info: Slack histogram:
Info: legend: * represents 141 endpoint(s)
Info: + represents [1,141) endpoint(s)
Info: [ 7979, 9543) |+
Info: [ 9543, 11107) |+
Info: [ 11107, 12671) |+
Info: [ 12671, 14235) |+
Info: [ 14235, 15799) |*+
Info: [ 15799, 17363) |**********+
Info: [ 17363, 18927) |*********+
Info: [ 18927, 20491) |************+
Info: [ 20491, 22055) |*********+
Info: [ 22055, 23619) |*******+
Info: [ 23619, 25183) |*********+
Info: [ 25183, 26747) |*********************************************+
Info: [ 26747, 28311) |************************************************************
Info: [ 28311, 29875) |****************+
Info: [ 29875, 31439) |***+
Info: [ 31439, 33003) |*+
Info: [ 33003, 34567) |**+
Info: [ 34567, 36131) |***+
Info: [ 36131, 37695) |*+
Info: [ 37695, 39259) |*+
Info: Checksum: 0xc8e37b8c
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 67307 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 133 866 | 133 866 | 66674| 1.27 1.27|
Info: 2000 | 340 1659 | 207 793 | 66162| 0.36 1.63|
Info: 3000 | 457 2542 | 117 883 | 65512| 0.37 2.00|
Info: 4000 | 569 3430 | 112 888 | 65409| 0.34 2.35|
Info: 5000 | 669 4330 | 100 900 | 64912| 0.31 2.65|
Info: 6000 | 776 5223 | 107 893 | 64517| 0.34 2.99|
Info: 7000 | 899 6100 | 123 877 | 63897| 0.33 3.33|
Info: 8000 | 1015 6984 | 116 884 | 63433| 0.32 3.65|
Info: 9000 | 1090 7909 | 75 925 | 63199| 0.33 3.98|
Info: 10000 | 1193 8806 | 103 897 | 62756| 0.34 4.32|
Info: 11000 | 1328 9671 | 135 865 | 62135| 0.29 4.61|
Info: 12000 | 1435 10564 | 107 893 | 61387| 0.29 4.91|
Info: 13000 | 1524 11475 | 89 911 | 61161| 0.31 5.22|
Info: 14000 | 1571 12428 | 47 953 | 61413| 0.33 5.55|
Info: 15000 | 1657 13342 | 86 914 | 60773| 0.32 5.87|
Info: 16000 | 1818 14181 | 161 839 | 60350| 0.33 6.20|
Info: 17000 | 1994 15005 | 176 824 | 60032| 0.35 6.55|
Info: 18000 | 2183 15816 | 189 811 | 59588| 0.34 6.89|
Info: 19000 | 2295 16704 | 112 888 | 59139| 0.32 7.22|
Info: 20000 | 2510 17489 | 215 785 | 58721| 0.31 7.53|
Info: 21000 | 2600 18399 | 90 910 | 59194| 0.40 7.93|
Info: 22000 | 2664 19335 | 64 936 | 58322| 0.28 8.21|
Info: 23000 | 2792 20207 | 128 872 | 57923| 0.30 8.51|
Info: 24000 | 2912 21087 | 120 880 | 57916| 0.39 8.90|
Info: 25000 | 2993 22006 | 81 919 | 57318| 0.35 9.25|
Info: 26000 | 3122 22877 | 129 871 | 56731| 0.31 9.56|
Info: 27000 | 3221 23778 | 99 901 | 57352| 0.36 9.91|
Info: 28000 | 3235 24764 | 14 986 | 57178| 0.33 10.24|
Info: 29000 | 3268 25731 | 33 967 | 56385| 0.30 10.54|
Info: 30000 | 3461 26538 | 193 807 | 55780| 0.33 10.87|
Info: 31000 | 3571 27428 | 110 890 | 55070| 0.33 11.20|
Info: 32000 | 3760 28239 | 189 811 | 54503| 0.32 11.52|
Info: 33000 | 3922 29077 | 162 838 | 54089| 0.34 11.86|
Info: 34000 | 4081 29918 | 159 841 | 53429| 0.33 12.19|
Info: 35000 | 4171 30828 | 90 910 | 53050| 0.31 12.49|
Info: 36000 | 4313 31686 | 142 858 | 52302| 0.31 12.81|
Info: 37000 | 4464 32535 | 151 849 | 51698| 0.30 13.10|
Info: 38000 | 4604 33395 | 140 860 | 51186| 0.28 13.39|
Info: 39000 | 4765 34234 | 161 839 | 50513| 0.33 13.72|
Info: 40000 | 4974 35025 | 209 791 | 49962| 0.43 14.14|
Info: 41000 | 5135 35864 | 161 839 | 49298| 0.44 14.58|
Info: 42000 | 5325 36674 | 190 810 | 48598| 0.38 14.96|
Info: 43000 | 5483 37516 | 158 842 | 48045| 0.46 15.42|
Info: 44000 | 5620 38379 | 137 863 | 47265| 0.30 15.72|
Info: 45000 | 5792 39207 | 172 828 | 46623| 0.47 16.19|
Info: 46000 | 5939 40060 | 147 853 | 45860| 0.41 16.60|
Info: 47000 | 6101 40898 | 162 838 | 45479| 0.46 17.06|
Info: 48000 | 6198 41801 | 97 903 | 45205| 0.52 17.59|
Info: 49000 | 6354 42645 | 156 844 | 44400| 0.39 17.98|
Info: 50000 | 6542 43457 | 188 812 | 43702| 0.43 18.41|
Info: 51000 | 6704 44295 | 162 838 | 43149| 0.38 18.79|
Info: 52000 | 6937 45062 | 233 767 | 42609| 0.51 19.29|
Info: 53000 | 7107 45892 | 170 830 | 41886| 0.42 19.71|
Info: 54000 | 7276 46723 | 169 831 | 41245| 0.44 20.15|
Info: 55000 | 7491 47508 | 215 785 | 40738| 0.39 20.55|
Info: 56000 | 7680 48319 | 189 811 | 40202| 0.43 20.97|
Info: 57000 | 7862 49137 | 182 818 | 39483| 0.37 21.34|
Info: 58000 | 8084 49915 | 222 778 | 38961| 0.44 21.79|
Info: 59000 | 8313 50686 | 229 771 | 38372| 0.44 22.23|
Info: 60000 | 8503 51496 | 190 810 | 37781| 0.44 22.67|
Info: 61000 | 8684 52315 | 181 819 | 37323| 0.42 23.09|
Info: 62000 | 8844 53155 | 160 840 | 36991| 0.40 23.49|
Info: 63000 | 9006 53993 | 162 838 | 36463| 0.36 23.85|
Info: 64000 | 9236 54763 | 230 770 | 36293| 0.36 24.21|
Info: 65000 | 9421 55578 | 185 815 | 35721| 0.36 24.58|
Info: 66000 | 9625 56374 | 204 796 | 35113| 0.38 24.96|
Info: 67000 | 9833 57166 | 208 792 | 34420| 0.36 25.31|
Info: 68000 | 9988 58011 | 155 845 | 34622| 0.58 25.89|
Info: 69000 | 10061 58938 | 73 927 | 34358| 0.36 26.25|
Info: 70000 | 10219 59780 | 158 842 | 33890| 0.33 26.58|
Info: 71000 | 10419 60580 | 200 800 | 33233| 0.36 26.94|
Info: 72000 | 10655 61344 | 236 764 | 32782| 0.39 27.32|
Info: 73000 | 10965 62034 | 310 690 | 32210| 0.37 27.69|
Info: 74000 | 11294 62705 | 329 671 | 31717| 0.38 28.08|
Info: 75000 | 11625 63374 | 331 669 | 31162| 0.41 28.48|
Info: 76000 | 11896 64103 | 271 729 | 30653| 0.44 28.92|
Info: 77000 | 12176 64823 | 280 720 | 30375| 0.44 29.36|
Info: 78000 | 12467 65532 | 291 709 | 29827| 0.41 29.77|
Info: 79000 | 12907 66092 | 440 560 | 29393| 0.45 30.22|
Info: 80000 | 13193 66806 | 286 714 | 29054| 0.40 30.62|
Info: 81000 | 13469 67530 | 276 724 | 28768| 0.40 31.01|
Info: 82000 | 13811 68188 | 342 658 | 28406| 0.41 31.42|
Info: 83000 | 14099 68900 | 288 712 | 27929| 0.42 31.84|
Info: 84000 | 14421 69578 | 322 678 | 27442| 0.42 32.26|
Info: 85000 | 14873 70126 | 452 548 | 26992| 0.41 32.66|
Info: 86000 | 15379 70620 | 506 494 | 26565| 0.38 33.04|
Info: 87000 | 15826 71173 | 447 553 | 26122| 0.43 33.47|
Info: 88000 | 16258 71741 | 432 568 | 25656| 0.46 33.93|
Info: 89000 | 16565 72434 | 307 693 | 25351| 0.45 34.38|
Info: 90000 | 16949 73050 | 384 616 | 24956| 0.43 34.81|
Info: 91000 | 17351 73648 | 402 598 | 24577| 0.45 35.26|
Info: 92000 | 17752 74247 | 401 599 | 24156| 0.43 35.69|
Info: 93000 | 18143 74856 | 391 609 | 23825| 0.42 36.11|
Info: 94000 | 18598 75401 | 455 545 | 23463| 0.46 36.57|
Info: 95000 | 18987 75972 | 389 571 | 23137| 0.52 37.10|
Info: 96000 | 19364 76548 | 377 576 | 22716| 0.41 37.51|
Info: 97000 | 19759 77095 | 395 547 | 22266| 0.50 38.01|
Info: 98000 | 20144 77648 | 385 553 | 21727| 0.47 38.48|
Info: 99000 | 20487 78246 | 343 598 | 21313| 0.46 38.94|
Info: 100000 | 20853 78818 | 366 572 | 20889| 0.66 39.60|
Info: 101000 | 21257 79344 | 404 526 | 20366| 0.43 40.03|
Info: 102000 | 21668 79890 | 411 546 | 19975| 0.44 40.47|
Info: 103000 | 22143 80363 | 475 473 | 19528| 0.40 40.87|
Info: 104000 | 22462 81018 | 319 655 | 19241| 0.44 41.31|
Info: 105000 | 22855 81576 | 393 558 | 18812| 0.41 41.72|
Info: 106000 | 23227 82143 | 372 567 | 18316| 0.39 42.11|
Info: 107000 | 23560 82704 | 333 561 | 17747| 0.38 42.49|
Info: 108000 | 23887 83304 | 327 600 | 17150| 0.33 42.82|
Info: 109000 | 24152 83991 | 265 687 | 16455| 0.26 43.08|
Info: 110000 | 24442 84652 | 290 661 | 15783| 0.29 43.37|
Info: 111000 | 24756 85277 | 314 625 | 15147| 0.31 43.68|
Info: 112000 | 25133 85855 | 377 578 | 14559| 0.35 44.02|
Info: 113000 | 25560 86384 | 427 529 | 14154| 0.41 44.43|
Info: 114000 | 26045 86865 | 485 481 | 13764| 0.41 44.84|
Info: 115000 | 26477 87398 | 432 533 | 13219| 0.40 45.24|
Info: 116000 | 26725 88130 | 248 732 | 12563| 0.33 45.57|
Info: 117000 | 26764 89087 | 39 957 | 11604| 0.17 45.74|
Info: 118000 | 26804 90047 | 40 960 | 10647| 0.16 45.90|
Info: 119000 | 26826 91025 | 22 978 | 9677| 0.15 46.05|
Info: 120000 | 26855 91996 | 29 971 | 8722| 0.15 46.20|
Info: 121000 | 26868 92983 | 13 987 | 7773| 0.15 46.36|
Info: 122000 | 26872 93979 | 4 996 | 6778| 0.14 46.49|
Info: 123000 | 26875 94976 | 3 997 | 5781| 0.14 46.63|
Info: 124000 | 26882 95969 | 7 993 | 4788| 0.14 46.77|
Info: 125000 | 26888 96963 | 6 994 | 3813| 0.15 46.91|
Info: 126000 | 26905 97944 | 17 981 | 2831| 0.15 47.06|
Info: 127000 | 26946 98901 | 41 957 | 1881| 0.19 47.25|
Info: 128000 | 27069 99744 | 123 843 | 1088| 0.30 47.56|
Info: 129000 | 27155 100507 | 86 763 | 225| 0.35 47.91|
Info: 129227 | 27158 100594 | 3 87 | 0| 0.18 48.09|
Info: Routing complete.
Info: Router1 time 48.09s
Info: Checksum: 0xc7d17d27
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info: 1.4 1.9 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_1_C_LUT4_Z_D[1] (14,17) -> (16,5)
Info: Sink SOC.Uart.response_LUT4_B_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.1 Source SOC.Uart.response_LUT4_B_Z_LUT4_Z.F
Info: 1.2 3.3 Net SOC.Uart.response_LUT4_B_Z[2] (16,5) -> (15,6)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_D_C_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.5 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_D_C_LUT4_Z_D_LUT4_Z.F
Info: 0.4 4.0 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_C_Z_LUT4_Z_A_LUT4_B_Z_LUT4_D_Z_LUT4_Z_C[1] (15,6) -> (15,6)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_D_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.2 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_D_C_LUT4_Z.F
Info: 1.0 5.2 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B[2] (15,6) -> (18,15)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_D_C_LUT4_D.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.5 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_D_C_LUT4_D.F
Info: 1.9 7.4 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_1_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_C0[1] (18,15) -> (32,6)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_Z_CCU2C_S0_B1_PFUMX_Z_ALUT_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 7.7 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_Z_CCU2C_S0_B1_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 7.7 Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_Z_CCU2C_S0_B1_PFUMX_Z_ALUT (32,6) -> (32,6)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_Z_CCU2C_S0_B1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info: 0.2 7.8 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_Z_CCU2C_S0_B1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 2.0 9.8 Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_Z_CCU2C_S0_A1[1] (32,6) -> (29,18)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.0 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z.F
Info: 1.0 11.0 Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_Z_2_D[2] (29,18) -> (23,19)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 11.3 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_Z_2.F
Info: 0.7 12.0 Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z[2] (23,19) -> (22,20)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_PFUMX_Z_1_ALUT_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 12.2 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_PFUMX_Z_1_ALUT_LUT4_Z.F
Info: 0.0 12.2 Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_PFUMX_Z_1_ALUT (22,20) -> (22,20)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_PFUMX_Z_1_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info: 0.2 12.4 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_PFUMX_Z_1_BLUT_LUT4_Z.OFX
Info: 0.8 13.2 Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_1_Z[6] (22,20) -> (21,18)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_LUT4_B.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 13.4 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_LUT4_B.OFX
Info: 0.0 13.4 Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_PFUMX_C0_Z (21,18) -> (21,18)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_LUT4_A.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 13.7 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_LUT4_A.OFX
Info: 1.0 14.7 Net SOC.Core.RegisterBank.registers.0.0_DO_1_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_D_LUT4_D_Z_LUT4_D_Z[4] (21,18) -> (19,14)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_6_C0_LUT4_Z_1_C_LUT4_Z_D_LUT4_C_1_Z_PFUMX_Z_3_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 14.9 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_6_C0_LUT4_Z_1_C_LUT4_Z_D_LUT4_C_1_Z_PFUMX_Z_3_BLUT_LUT4_Z.OFX
Info: 1.3 16.3 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_6_C0_LUT4_Z_1_C_LUT4_Z_D_LUT4_C_1_Z[6] (19,14) -> (14,9)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 16.5 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.9 17.5 Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z[5] (14,9) -> (17,7)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_5_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN_S0_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 17.7 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_5_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN_S0_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 19.0 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_5_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN_S0_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_B_Z[6] (17,7) -> (30,9)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 19.3 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.0 20.2 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z[3] (30,9) -> (30,15)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 20.5 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 20.5 Net SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT (30,15) -> (30,15)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.30-141.32
Info: 0.2 20.7 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 20.7 Net SOC.Core.Pc.load_L6MUX21_Z_D1 (30,15) -> (30,15)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 20.9 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.9 22.8 Net SOC.Core.Pc.load (30,15) -> (16,6)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_30.CE
Info: Defined in:
Info: Risco-5/src/core/pc.v:5.16-5.20
Info: 0.0 22.8 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_30.CE
Info: 4.9 ns logic, 17.9 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[0]$tr_io.O
Info: 2.8 2.8 Net gpios[0]$TRELLIS_IO_IN (0,44) -> (13,23)
Info: Sink SOC.GPIOS.Gpios[0].direction_LUT4_B.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 3.0 Source SOC.GPIOS.Gpios[0].direction_LUT4_B.F
Info: 2.5 5.6 Net SOC.GPIOS.Gpios[0].direction_LUT4_B_Z[1] (13,23) -> (36,20)
Info: Sink SOC.Core.read_data_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.8 Source SOC.Core.read_data_LUT4_Z.F
Info: 1.7 7.5 Net SOC.read_data[0] (36,20) -> (25,25)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:21.34-21.43
Info: 0.0 7.5 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info: 0.5 ns logic, 7.0 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info: 3.8 4.4 Net SOC.Core.read_data_LUT4_Z_2_D[1] (19,20) -> (81,20)
Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info: Defined in:
Info: Risco-5/src/peripheral/gpios.v:16.19-16.33
Info: 0.2 4.6 Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info: 0.7 5.3 Net gpios_$_TBUF__Y_3_E (81,20) -> (82,21)
Info: Sink gpios[2]$tr_io$invert_T.A
Info: 0.2 5.6 Source gpios[2]$tr_io$invert_T.F
Info: 1.3 6.8 Net gpios[2]$tr_io$invert_T$conn$Z (82,21) -> (90,23)
Info: Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 5.8 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 43.83 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.48 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.84 ns
Info: Slack histogram:
Info: legend: * represents 137 endpoint(s)
Info: + represents [1,137) endpoint(s)
Info: [ 17186, 18280) |+
Info: [ 18280, 19374) |+
Info: [ 19374, 20468) |****+
Info: [ 20468, 21562) |**********+
Info: [ 21562, 22656) |**+
Info: [ 22656, 23750) |***+
Info: [ 23750, 24844) |*********+
Info: [ 24844, 25938) |*************+
Info: [ 25938, 27032) |*******+
Info: [ 27032, 28126) |*****+
Info: [ 28126, 29220) |*************+
Info: [ 29220, 30314) |************************************************************
Info: [ 30314, 31408) |****************************************************+
Info: [ 31408, 32502) |********+
Info: [ 32502, 33596) |*+
Info: [ 33596, 34690) |*+
Info: [ 34690, 35784) |*+
Info: [ 35784, 36878) |**+
Info: [ 36878, 37972) |*+
Info: [ 37972, 39066) |*+
Info: Program finished normally.
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