Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 5854/43848 13%
Info: logic LUTs: 3830/43848 8%
Info: carry LUTs: 176/43848 0%
Info: RAM LUTs: 1232/ 5481 22%
Info: RAMW LUTs: 616/10962 5%
Info: Total DFFs: 785/43848 1%
Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 341 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xa430aef0
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 785/43848 1%
Info: TRELLIS_COMB: 5924/43848 13%
Info: TRELLIS_RAMW: 308/ 5481 5%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 3351 cells, random placement wirelen = 291369.
Info: at initial placer iter 0, wirelen = 2093
Info: at initial placer iter 1, wirelen = 1892
Info: at initial placer iter 2, wirelen = 1871
Info: at initial placer iter 3, wirelen = 1550
Info: Running main analytical placer, max placement attempts per cell = 6188162.
Info: at iteration #1, type ALL: wirelen solved = 1521, spread = 37300, legal = 37920; time = 0.17s
Info: at iteration #2, type ALL: wirelen solved = 4335, spread = 29164, legal = 29946; time = 0.18s
Info: at iteration #3, type ALL: wirelen solved = 5725, spread = 28106, legal = 28820; time = 0.24s
Info: at iteration #4, type ALL: wirelen solved = 7295, spread = 26006, legal = 26843; time = 0.24s
Info: at iteration #5, type ALL: wirelen solved = 9865, spread = 25165, legal = 25974; time = 0.24s
Info: at iteration #6, type ALL: wirelen solved = 10674, spread = 24990, legal = 25840; time = 0.22s
Info: at iteration #7, type ALL: wirelen solved = 11914, spread = 25537, legal = 26341; time = 0.21s
Info: at iteration #8, type ALL: wirelen solved = 13625, spread = 25135, legal = 25868; time = 0.21s
Info: at iteration #9, type ALL: wirelen solved = 14126, spread = 24676, legal = 25471; time = 0.22s
Info: at iteration #10, type ALL: wirelen solved = 15081, spread = 23960, legal = 24915; time = 0.22s
Info: at iteration #11, type ALL: wirelen solved = 15157, spread = 23991, legal = 24965; time = 0.22s
Info: at iteration #12, type ALL: wirelen solved = 15886, spread = 23752, legal = 24734; time = 0.21s
Info: at iteration #13, type ALL: wirelen solved = 16218, spread = 24323, legal = 25044; time = 0.15s
Info: at iteration #14, type ALL: wirelen solved = 17016, spread = 24123, legal = 24800; time = 0.20s
Info: at iteration #15, type ALL: wirelen solved = 17217, spread = 23969, legal = 24764; time = 0.21s
Info: at iteration #16, type ALL: wirelen solved = 17628, spread = 24983, legal = 25540; time = 0.20s
Info: at iteration #17, type ALL: wirelen solved = 18376, spread = 24353, legal = 24959; time = 0.14s
Info: HeAP Placer Time: 5.26s
Info: of which solving equations: 3.36s
Info: of which spreading cells: 0.36s
Info: of which strict legalisation: 0.13s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 3239, wirelen = 24734
Info: at iteration #5: temp = 0.000000, timing cost = 2719, wirelen = 21938
Info: at iteration #10: temp = 0.000000, timing cost = 2688, wirelen = 21151
Info: at iteration #15: temp = 0.000000, timing cost = 2523, wirelen = 20847
Info: at iteration #20: temp = 0.000000, timing cost = 2496, wirelen = 20756
Info: at iteration #25: temp = 0.000000, timing cost = 2503, wirelen = 20733
Info: at iteration #25: temp = 0.000000, timing cost = 2501, wirelen = 20734
Info: SA placement time 17.47s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 30.96 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 10.55 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 11.72 ns
Info: Slack histogram:
Info: legend: * represents 43 endpoint(s)
Info: + represents [1,43) endpoint(s)
Info: [ 7703, 9280) |+
Info: [ 9280, 10857) |+
Info: [ 10857, 12434) |+
Info: [ 12434, 14011) |+
Info: [ 14011, 15588) |+
Info: [ 15588, 17165) |*+
Info: [ 17165, 18742) |+
Info: [ 18742, 20319) |******+
Info: [ 20319, 21896) |*******+
Info: [ 21896, 23473) |****+
Info: [ 23473, 25050) |****************+
Info: [ 25050, 26627) |****************+
Info: [ 26627, 28204) |*****************************************************+
Info: [ 28204, 29781) |************************************************************
Info: [ 29781, 31358) |**********+
Info: [ 31358, 32935) |**+
Info: [ 32935, 34512) |*****+
Info: [ 34512, 36089) |*************+
Info: [ 36089, 37666) |********+
Info: [ 37666, 39243) |*****+
Info: Checksum: 0x445dd3f4
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 28265 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 362 637 | 362 637 | 27785| 0.65 0.65|
Info: 2000 | 704 1295 | 342 658 | 27214| 0.25 0.90|
Info: 3000 | 926 2073 | 222 778 | 26645| 0.23 1.13|
Info: 4000 | 1122 2877 | 196 804 | 26075| 0.23 1.35|
Info: 5000 | 1293 3706 | 171 829 | 25403| 0.22 1.57|
Info: 6000 | 1443 4556 | 150 850 | 24956| 0.20 1.77|
Info: 7000 | 1614 5385 | 171 829 | 24346| 0.22 1.99|
Info: 8000 | 1836 6163 | 222 778 | 23681| 0.24 2.24|
Info: 9000 | 1995 7004 | 159 841 | 23063| 0.21 2.45|
Info: 10000 | 2217 7782 | 222 778 | 22448| 0.24 2.69|
Info: 11000 | 2444 8555 | 227 773 | 22177| 0.24 2.93|
Info: 12000 | 2667 9332 | 223 777 | 21533| 0.24 3.17|
Info: 13000 | 2878 10121 | 211 789 | 20848| 0.26 3.43|
Info: 14000 | 3113 10886 | 235 765 | 20182| 0.28 3.71|
Info: 15000 | 3374 11625 | 261 739 | 19623| 0.29 4.00|
Info: 16000 | 3604 12395 | 230 770 | 19070| 0.29 4.29|
Info: 17000 | 3797 13202 | 193 807 | 18370| 0.28 4.56|
Info: 18000 | 4103 13896 | 306 694 | 17804| 0.31 4.88|
Info: 19000 | 4367 14632 | 264 736 | 17270| 0.30 5.17|
Info: 20000 | 4593 15406 | 226 774 | 16578| 0.29 5.46|
Info: 21000 | 4875 16124 | 282 718 | 15969| 0.30 5.77|
Info: 22000 | 5161 16838 | 286 714 | 15371| 0.32 6.09|
Info: 23000 | 5422 17577 | 261 739 | 14872| 0.34 6.43|
Info: 24000 | 5714 18285 | 292 708 | 14336| 0.29 6.72|
Info: 25000 | 6075 18924 | 361 639 | 13948| 0.32 7.04|
Info: 26000 | 6389 19610 | 314 686 | 13376| 0.28 7.32|
Info: 27000 | 6701 20298 | 312 688 | 12831| 0.29 7.62|
Info: 28000 | 6979 21016 | 278 718 | 12154| 0.28 7.89|
Info: 29000 | 7233 21678 | 254 662 | 11456| 0.24 8.13|
Info: 30000 | 7573 22229 | 340 551 | 10842| 0.25 8.39|
Info: 31000 | 7877 22791 | 304 562 | 10193| 0.24 8.63|
Info: 32000 | 8154 23398 | 277 607 | 9546| 0.29 8.92|
Info: 33000 | 8435 24050 | 281 652 | 8945| 0.31 9.23|
Info: 34000 | 8775 24686 | 340 636 | 8356| 0.32 9.55|
Info: 35000 | 9057 25390 | 282 704 | 7789| 0.30 9.85|
Info: 36000 | 9262 26168 | 205 778 | 7013| 0.22 10.07|
Info: 37000 | 9535 26887 | 273 719 | 6340| 0.26 10.33|
Info: 38000 | 9831 27582 | 296 695 | 5704| 0.31 10.64|
Info: 39000 | 9906 28505 | 75 923 | 4847| 0.19 10.83|
Info: 40000 | 9936 29475 | 30 970 | 3888| 0.09 10.92|
Info: 41000 | 9953 30458 | 17 983 | 2905| 0.08 11.00|
Info: 42000 | 10008 31396 | 55 938 | 1971| 0.18 11.18|
Info: 43000 | 10157 32205 | 149 809 | 1137| 0.29 11.47|
Info: 44000 | 10262 32955 | 105 750 | 327| 0.35 11.82|
Info: 44326 | 10262 33077 | 0 122 | 0| 0.10 11.92|
Info: Routing complete.
Info: Router1 time 11.92s
Info: Checksum: 0xbbf35d0d
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.instruction_register_TRELLIS_FF_Q_19.Q
Info: 2.3 2.8 Net SOC.Core.instruction_register[12] (20,16) -> (37,20)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_L6MUX21_Z_SD_L6MUX21_SD_Z_L6MUX21_Z_SD_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.0 Source SOC.Core.RegisterBank.registers.0.0_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_L6MUX21_Z_SD_L6MUX21_SD_Z_L6MUX21_Z_SD_LUT4_Z.F
Info: 0.2 3.3 Net SOC.Core.RegisterBank.registers.0.0_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_L6MUX21_Z_SD_L6MUX21_SD_Z_L6MUX21_Z_SD[5] (37,20) -> (37,20)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_L6MUX21_Z_SD_L6MUX21_SD_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 3.5 Source SOC.Core.RegisterBank.registers.0.0_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_L6MUX21_Z_SD_L6MUX21_SD_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 2.1 5.6 Net SOC.Core.RegisterBank.registers.0.0_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C[2] (37,20) -> (18,17)
Info: Sink SOC.Core.RegisterBank.registers.0.6_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.9 Source SOC.Core.RegisterBank.registers.0.6_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z.F
Info: 1.3 7.1 Net SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z[3] (18,17) -> (9,16)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 7.4 Source SOC.Core.RegisterBank.registers.0.1_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.6 8.0 Net SOC.Core.RegisterBank.registers.0.1_DO_LUT4_A_Z[0] (9,16) -> (10,17)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z.A
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 8.2 Source SOC.Core.RegisterBank.registers.0.7_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 8.2 Net SOC.Core.RegisterBank.registers.0.7_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT (10,17) -> (10,17)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.22-141.24
Info: 0.2 8.4 Source SOC.Core.RegisterBank.registers.0.7_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 8.4 Net SOC.Core.RegisterBank.registers.0.7_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0 (10,17) -> (10,17)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.34-141.36
Info: 0.2 8.7 Source SOC.Core.RegisterBank.registers.0.7_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 9.9 Net SOC.Core.RegisterBank.registers.0.7_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_SD_Z[3] (10,17) -> (24,15)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_1_SD_PFUMX_Z_BLUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 10.3 Source SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_1_SD_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.9 11.2 Net SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_1_SD[5] (24,15) -> (24,18)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 11.5 Source SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 11.5 Net SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_1_D1 (24,18) -> (24,18)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 11.7 Source SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.5 13.2 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_2_SD_LUT4_Z_B_PFUMX_Z_BLUT_LUT4_Z_C[4] (24,18) -> (14,19)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_LUT4_Z_1_B_LUT4_D_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 13.4 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_LUT4_Z_1_B_LUT4_D_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.6 14.0 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_LUT4_Z_1_B_LUT4_D_Z[3] (14,19) -> (15,19)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 14.3 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 14.3 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT (15,19) -> (15,19)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.30-157.32
Info: 0.2 14.4 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 14.4 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1 (15,19) -> (15,19)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.54-157.56
Info: 0.2 14.7 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 14.7 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_L6MUX21_Z_1_D0 (15,19) -> (15,19)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.66-157.68
Info: 0.2 14.9 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.2 16.1 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z_A[3] (15,19) -> (15,24)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 16.5 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_1_BLUT_LUT4_Z.OFX
Info: 0.6 17.1 Net SOC.Core.alu_out[0] (15,24) -> (15,25)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_2_SD_PFUMX_Z_1_C0_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_D_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: Risco-5/src/core/core.v:58.31-58.38
Info: 0.3 17.4 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_2_SD_PFUMX_Z_1_C0_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_D_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.8 19.2 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_2_SD_PFUMX_Z_1_C0_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_D_Z[6] (15,25) -> (33,20)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_2_B_LUT4_Z_D_LUT4_D_B_LUT4_Z_B_LUT4_C_Z_LUT4_Z_1_B_LUT4_C_1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 19.5 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_2_B_LUT4_Z_D_LUT4_D_B_LUT4_Z_B_LUT4_C_Z_LUT4_Z_1_B_LUT4_C_1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.7 20.1 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_2_B_LUT4_Z_D_LUT4_D_B_LUT4_Z_B_LUT4_C_Z_LUT4_Z_1_B_LUT4_C_1_Z[4] (33,20) -> (33,18)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 20.4 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 20.4 Net SOC.Core.Pc.load_L6MUX21_Z_D1 (33,18) -> (33,18)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 20.6 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 2.2 22.8 Net SOC.Core.pc_load (33,18) -> (10,23)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_30.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:50.32-50.39
Info: 0.0 22.8 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_30.CE
Info: 5.6 ns logic, 17.2 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[2]$tr_io.O
Info: 5.0 5.0 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (28,14)
Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_C.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 5.2 Source SOC.GPIOS.Gpios[2].direction_LUT4_C.F
Info: 2.0 7.2 Net SOC.GPIOS.Gpios[2].direction_LUT4_C_Z[2] (28,14) -> (10,13)
Info: Sink SOC.Core.read_data_LUT4_Z_20.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 7.4 Source SOC.Core.read_data_LUT4_Z_20.F
Info: 0.9 8.3 Net SOC.read_data[2] (10,13) -> (10,14)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 8.3 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: 0.5 ns logic, 7.9 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info: 4.5 5.0 Net SOC.Leds.data[2] (10,19) -> (76,29)
Info: Sink led_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: 0.2 5.2 Source led_LUT4_Z.F
Info: 2.3 7.5 Net led[2]$TRELLIS_IO_OUT (76,29) -> (90,44)
Info: Sink led[2]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.7 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 43.79 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.33 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.48 ns
Info: Slack histogram:
Info: legend: * represents 47 endpoint(s)
Info: + represents [1,47) endpoint(s)
Info: [ 17166, 18261) |+
Info: [ 18261, 19356) |+
Info: [ 19356, 20451) |+
Info: [ 20451, 21546) |*+
Info: [ 21546, 22641) |*******+
Info: [ 22641, 23736) |******+
Info: [ 23736, 24831) |*+
Info: [ 24831, 25926) |***+
Info: [ 25926, 27021) |***********+
Info: [ 27021, 28116) |******************+
Info: [ 28116, 29211) |**+
Info: [ 29211, 30306) |*********************************+
Info: [ 30306, 31401) |************************************************************
Info: [ 31401, 32496) |***************+
Info: [ 32496, 33591) |******+
Info: [ 33591, 34686) |****+
Info: [ 34686, 35781) |***+
Info: [ 35781, 36876) |*******+
Info: [ 36876, 37971) |**********+
Info: [ 37971, 39066) |****+
Info: Program finished normally.
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