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WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module LEDs is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2117.781 ; gain = 493.684 ; free physical = 867 ; free virtual = 25299
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2132.625 ; gain = 508.527 ; free physical = 867 ; free virtual = 25299
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2132.625 ; gain = 508.527 ; free physical = 867 ; free virtual = 25299
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2132.625 ; gain = 0.000 ; free physical = 867 ; free virtual = 25299
Info: at iteration #10: temp = 0.000000, timing cost = 3601, wirelen = 20294
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2280.375 ; gain = 0.000 ; free physical = 854 ; free virtual = 25285
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2280.410 ; gain = 0.000 ; free physical = 853 ; free virtual = 25285
Info: at iteration #15: temp = 0.000000, timing cost = 3362, wirelen = 20117
Info: at iteration #20: temp = 0.000000, timing cost = 3358, wirelen = 20073
Info: at iteration #20: temp = 0.000000, timing cost = 3352, wirelen = 20076
Info: SA placement time 13.38s
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":226)
WARN (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":152)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 33.24 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.35 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.68 ns
Info: Slack histogram:
Info: legend: * represents 37 endpoint(s)
Info: + represents [1,37) endpoint(s)
Info: [ 9914, 11381) |+
Info: [ 11381, 12848) |
Info: [ 12848, 14315) |+
Info: [ 14315, 15782) |*+
Info: [ 15782, 17249) |**+
Info: [ 17249, 18716) |*********+
Info: [ 18716, 20183) |******+
Info: [ 20183, 21650) |*************+
Info: [ 21650, 23117) |*******************+
Info: [ 23117, 24584) |*********+
Info: [ 24584, 26051) |******************************************************+
Info: [ 26051, 27518) |************************************************************
Info: [ 27518, 28985) |******+
Info: [ 28985, 30452) |*************************+
Info: [ 30452, 31919) |***+
Info: [ 31919, 33386) |***+
Info: [ 33386, 34853) |*******+
Info: [ 34853, 36320) |***********+
Info: [ 36320, 37787) |**********+
Info: [ 37787, 39254) |*******+
Info: Checksum: 0x845f82aa
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 28047 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 106 893 | 106 893 | 27184| 0.61 0.61|
Info: 2000 | 259 1740 | 153 847 | 26438| 0.31 0.92|
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 742 ; free virtual = 25176
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 742 ; free virtual = 25176
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 758 ; free virtual = 25192
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 00000000000000000000000000000000000000000000001 | 000000
VALIDATE_FETCH | 00000000000000000000000000000000000000000000010 | 101110
DECODE | 00000000000000000000000000000000000000000000100 | 000001
MEMADR | 00000000000000000000000000000000000000000001000 | 000010
MEMREAD_UNALIGNED | 00000000000000000000000000000000000000000010000 | 010110
LOAD_FIRST_BLOCK | 00000000000000000000000000000000000000000100000 | 010000
SAVE_FIRST_BLOCK | 00000000000000000000000000000000000000001000000 | 010001
CALC_NEXT_ADDRESS | 00000000000000000000000000000000000000010000000 | 010010
READ_SECOND_BLOCK | 00000000000000000000000000000000000000100000000 | 010011
LOAD_SECOND_BLOCK | 00000000000000000000000000000000000001000000000 | 010100
MERGE_BLOCKS | 00000000000000000000000000000000000010000000000 | 010101
FILTER_ALU_WB | 00000000000000000000000000000000000100000000000 | 010111
MEMREAD | 00000000000000000000000000000000001000000000000 | 000011
MEMWB | 00000000000000000000000000000000010000000000000 | 000100
MEMWRITE_UNALIGNED | 00000000000000000000000000000000100000000000000 | 011000
GEN_FIRST_BLOCK_PART_1 | 00000000000000000000000000000001000000000000000 | 011001
GEN_FIRST_BLOCK_PART_2 | 00000000000000000000000000000010000000000000000 | 011010
GEN_SECOND_BLOCK_PART_1 | 00000000000000000000000000000100000000000000000 | 011011
GEN_SECOND_BLOCK_PART_2 | 00000000000000000000000000001000000000000000000 | 011100
MERGE_WRITE_BLOCKS | 00000000000000000000000000010000000000000000000 | 011101
SWAP_VALUE_DIRECTION | 00000000000000000000000000100000000000000000000 | 011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 00000000000000000000000001000000000000000000000 | 100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 00000000000000000000000010000000000000000000000 | 100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 00000000000000000000000100000000000000000000000 | 100100
CLEAR_VALUE | 00000000000000000000001000000000000000000000000 | 011111
MERGE_WRITE_VALUE_1 | 00000000000000000000010000000000000000000000000 | 100000
WRITE_VALUE_1 | 00000000000000000000100000000000000000000000000 | 100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 00000000000000000001000000000000000000000000000 | 100101
READ_SECOND_BLOCK_TO_WRITE | 00000000000000000010000000000000000000000000000 | 100110
LOAD_SECOND_BLOCK_TO_WRITE | 00000000000000000100000000000000000000000000000 | 100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 00000000000000001000000000000000000000000000000 | 101000
SWAP_VALUE_DIRECTION_2 | 00000000000000010000000000000000000000000000000 | 101001
CLEAR_VALUE_PART_2 | 00000000000000100000000000000000000000000000000 | 101010
CLEAR_VALUE_PART_2_1 | 00000000000001000000000000000000000000000000000 | 101011
MERGE_WRITE_VALUE_2 | 00000000000010000000000000000000000000000000000 | 101100
WRITE_VALUE_2 | 00000000000100000000000000000000000000000000000 | 101101
MEMWRITE | 00000000001000000000000000000000000000000000000 | 000101
EXECUTER | 00000000010000000000000000000000000000000000000 | 000110
EXECUTEI | 00000000100000000000000000000000000000000000000 | 001000
JAL | 00000001000000000000000000000000000000000000000 | 001001
BEQ | 00000010000000000000000000000000000000000000000 | 001010
AUIPC | 00000100000000000000000000000000000000000000000 | 001100
LUI | 00001000000000000000000000000000000000000000000 | 001101
JALR_PC | 00010000000000000000000000000000000000000000000 | 001110
JALR | 00100000000000000000000000000000000000000000000 | 001011
ALUWB | 01000000000000000000000000000000000000000000000 | 000111
EXECUTECSR | 10000000000000000000000000000000000000000000000 | 001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
Info: 3000 | 476 2523 | 217 783 | 25881| 0.37 1.29|
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 0000 | 0000
COPY_WRITE_BUFFER | 0001 | 0100
WRITE | 0010 | 0010
READ | 0011 | 0001
READ_RX_FIFO_EMPTY | 0100 | 0110
READ_TX_FIFO_EMPTY | 0101 | 0111
READ_RX_FIFO_FULL | 0110 | 1000
READ_TX_FIFO_FULL | 0111 | 1001
WB | 1000 | 0101
FINISH | 1001 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 762 ; free virtual = 25197
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
3 Input 32 Bit Adders := 1
2 Input 10 Bit Adders := 2
2 Input 6 Bit Adders := 6
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 2
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
+---XORs :
2 Bit Wide XORs := 1
+---Registers :
33 Bit Registers := 1
32 Bit Registers := 50
16 Bit Registers := 2
10 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 5
4 Bit Registers := 2
3 Bit Registers := 1
1 Bit Registers := 20
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
128 Bit (16 X 8 bit) RAMs := 2
+---Muxes :
47 Input 47 Bit Muxes := 1
2 Input 47 Bit Muxes := 17
11 Input 47 Bit Muxes := 1
3 Input 33 Bit Muxes := 1
2 Input 32 Bit Muxes := 21
8 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 10
6 Input 32 Bit Muxes := 1
10 Input 32 Bit Muxes := 2
2 Input 31 Bit Muxes := 1
2 Input 8 Bit Muxes := 3
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
47 Input 4 Bit Muxes := 1
9 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 2
2 Input 4 Bit Muxes := 3
6 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
4 Input 3 Bit Muxes := 2
47 Input 3 Bit Muxes := 3
10 Input 3 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 16
47 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 4
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 71
47 Input 1 Bit Muxes := 12
4 Input 1 Bit Muxes := 3
8 Input 1 Bit Muxes := 7
10 Input 1 Bit Muxes := 8
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Info: 4000 | 657 3342 | 181 819 | 25227| 0.35 1.64|
Info: 5000 | 877 4122 | 220 780 | 24575| 0.28 1.92|
Info: 6000 | 1050 4949 | 173 827 | 23991| 0.26 2.18|
Info: 7000 | 1279 5720 | 229 771 | 23290| 0.27 2.45|
Info: 8000 | 1499 6500 | 220 780 | 22601| 0.25 2.69|
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
Info: 9000 | 1723 7276 | 224 776 | 22100| 0.29 2.98|
Info: 10000 | 1989 8010 | 266 734 | 21535| 0.33 3.31|
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
Info: 11000 | 2285 8714 | 296 704 | 20991| 0.27 3.58|
Info: 12000 | 2569 9430 | 284 716 | 20364| 0.27 3.85|
Info: 13000 | 2817 10182 | 248 752 | 19685| 0.28 4.13|
Info: 14000 | 3108 10891 | 291 709 | 19023| 0.32 4.45|
Info: 15000 | 3354 11645 | 246 754 | 18352| 0.33 4.78|
[10%] Placement Phase 0 completed
Info: 16000 | 3592 12407 | 238 762 | 17747| 0.33 5.11|
Info: 17000 | 3841 13158 | 249 751 | 17080| 0.33 5.44|
Info: 18000 | 4124 13875 | 283 717 | 16456| 0.32 5.75|
Info: 19000 | 4475 14524 | 351 649 | 15955| 0.31 6.07|
Info: 20000 | 4756 15243 | 281 719 | 15327| 0.36 6.42|
[20%] Placement Phase 1 completed
Info: 21000 | 5028 15971 | 272 728 | 14840| 0.33 6.76|
Info: 22000 | 5423 16576 | 395 605 | 14365| 0.34 7.10|
Info: 23000 | 5856 17143 | 433 567 | 13924| 0.40 7.49|
Info: 24000 | 6084 17915 | 228 772 | 13780| 0.34 7.84|
Info: 25000 | 6318 18681 | 234 766 | 13235| 0.32 8.15|
Info: 26000 | 6614 19385 | 296 704 | 12936| 0.33 8.49|
Info: 27000 | 7116 19883 | 502 498 | 12555| 0.31 8.79|
Info: 28000 | 7579 20420 | 463 537 | 12163| 0.34 9.14|
Info: 29000 | 7903 21096 | 324 676 | 11871| 0.35 9.48|
Info: 30000 | 8302 21697 | 399 601 | 11403| 0.35 9.83|
Info: 31000 | 8661 22330 | 359 633 | 11092| 0.39 10.23|
Info: 32000 | 9078 22873 | 417 543 | 10610| 0.32 10.54|
Info: 33000 | 9428 23415 | 350 542 | 10062| 0.29 10.83|
Info: 34000 | 9808 23944 | 380 529 | 9542| 0.29 11.13|
Info: 35000 | 10142 24522 | 334 578 | 8922| 0.26 11.38|
Info: 36000 | 10433 25094 | 291 572 | 8281| 0.25 11.63|
Info: 37000 | 10724 25725 | 291 631 | 7631| 0.24 11.87|
Info: 38000 | 11001 26437 | 277 712 | 7182| 0.31 12.18|
Info: 39000 | 11453 26979 | 452 542 | 6677| 0.35 12.53|
Info: 40000 | 11840 27588 | 387 609 | 6153| 0.38 12.91|
Info: 41000 | 11962 28462 | 122 874 | 5289| 0.22 13.13|
Info: 42000 | 11983 29440 | 21 978 | 4310| 0.08 13.21|
Info: 43000 | 11999 30423 | 16 983 | 3329| 0.09 13.29|
Info: 44000 | 12046 31371 | 47 948 | 2378| 0.15 13.45|
Info: 45000 | 12151 32253 | 105 882 | 1496| 0.23 13.68|
Info: 46000 | 12257 33085 | 106 832 | 618| 0.26 13.94|
Info: 46641 | 12273 33418 | 16 333 | 0| 0.13 14.07|
Info: Routing complete.
Info: Router1 time 14.07s
Info: Checksum: 0x463d0ac0
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_1.Q
Info: 0.7 1.3 Net SOC.Uart.response_LUT4_B_Z_LUT4_Z_3_B_LUT4_Z_C[0] (41,23) -> (42,23)
Info: Sink SOC.Uart.response_LUT4_B_Z_LUT4_Z_1_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 1.5 Source SOC.Uart.response_LUT4_B_Z_LUT4_Z_1_C_LUT4_Z.F
Info: 1.0 2.5 Net SOC.Uart.response_LUT4_B_Z_LUT4_Z_1_C[4] (42,23) -> (36,23)
Info: Sink SOC.Core.RegisterBank.registers.0.3_DO_2_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 2.8 Source SOC.Core.RegisterBank.registers.0.3_DO_2_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.9 3.7 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_4_A_LUT4_Z_A_LUT4_D_Z_LUT4_B_Z_LUT4_B_Z_LUT4_Z_B_LUT4_B_Z_LUT4_Z_D[0] (36,23) -> (30,23)
Info: Sink SOC.Core.RegisterBank.registers.0.3_DO_LUT4_A_Z_LUT4_Z_1_D_L6MUX21_Z_SD_L6MUX21_SD_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.9 Source SOC.Core.RegisterBank.registers.0.3_DO_LUT4_A_Z_LUT4_Z_1_D_L6MUX21_Z_SD_L6MUX21_SD_Z_LUT4_Z.F
Info: 0.7 4.6 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_Z_LUT4_Z_C_LUT4_C_Z_LUT4_C_Z[1] (30,23) -> (28,23)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 5.0 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 5.0 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0 (28,23) -> (28,23)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.50-157.52
Info: 0.2 5.3 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 5.3 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D0 (28,23) -> (28,23)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.66-157.68
Info: 0.2 5.5 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.9 6.4 Net SOC.Core.CSR_Unit.csr_mstatus_mie_LUT4_B_C_LUT4_Z_C_LUT4_Z_D_LUT4_Z_C[3] (28,23) -> (28,21)
Info: Sink SOC.Core.RegisterBank.registers.0.3_DO_LUT4_A_Z_LUT4_Z_1_D_LUT4_A.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.6 Source SOC.Core.RegisterBank.registers.0.3_DO_LUT4_A_Z_LUT4_Z_1_D_LUT4_A.F
Info: 1.6 8.2 Net SOC.Core.CSR_Unit.csr_mstatus_mie_LUT4_B_C_LUT4_Z_C_LUT4_Z_C[1] (28,21) -> (28,9)
Info: Sink SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 8.5 Source SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.4 8.9 Net SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z[2] (28,9) -> (28,9)
Info: Sink SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 9.1 Source SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A.F
Info: 0.8 9.9 Net SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z[4] (28,9) -> (30,12)
Info: Sink SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_LUT4_A.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 10.2 Source SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_LUT4_A.OFX
Info: 1.5 11.7 Net SOC.Core.RegisterBank.registers.0.3_DO_3_LUT4_A_Z_LUT4_B_Z_PFUMX_C0_Z[3] (30,12) -> (34,17)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 12.0 Source SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 12.0 Net SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT (34,17) -> (34,17)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.30-141.32
Info: 0.2 12.1 Source SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 12.1 Net SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1 (34,17) -> (34,17)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 12.4 Source SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.2 13.6 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_9_B_LUT4_Z_D_PFUMX_Z_C0_LUT4_Z_D_LUT4_D_Z_L6MUX21_Z_SD_LUT4_Z_B[6] (34,17) -> (38,25)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_C_LUT4_C_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.8 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_C_LUT4_C_1.F
Info: 0.7 14.5 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_PFUMX_Z_C0[3] (38,25) -> (37,25)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 14.9 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 14.9 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 (37,25) -> (37,25)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64
Info: 0.2 15.2 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 15.2 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1 (37,25) -> (37,25)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 15.4 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 16.7 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z[4] (37,25) -> (41,21)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_COUT_CCU2C_CIN_S0_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 16.9 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_COUT_CCU2C_CIN_S0_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z.F
Info: 1.0 17.9 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_COUT_CCU2C_CIN_S0_LUT4_D_Z_PFUMX_C0_Z[3] (41,21) -> (42,16)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 18.3 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 18.3 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_L6MUX21_Z_D1 (42,16) -> (42,16)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 18.5 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 19.8 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z[3] (42,16) -> (31,17)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 20.1 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_LUT4_C.F
Info: 0.7 20.8 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_LUT4_C_Z[5] (31,17) -> (31,16)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 21.0 Source SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 21.0 Net SOC.Core.Pc.load_L6MUX21_Z_D1 (31,16) -> (31,16)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 21.3 Source SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.7 22.9 Net SOC.Core.pc_load (31,16) -> (27,3)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_17.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:50.32-50.39
Info: 0.0 22.9 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_17.CE
Info: 6.5 ns logic, 16.4 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[2]$tr_io.O
Info: 4.9 4.9 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (20,21)
Info: Sink SOC.GPIOS.Gpios[2].data_in_LUT4_C.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 5.1 Source SOC.GPIOS.Gpios[2].data_in_LUT4_C.F
Info: 0.8 5.9 Net SOC.GPIOS.Gpios[2].data_in_LUT4_C_Z[2] (20,21) -> (20,17)
Info: Sink SOC.Core.read_data_LUT4_Z_19.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.1 Source SOC.Core.read_data_LUT4_Z_19.F
Info: 0.8 6.9 Net SOC.read_data[2] (20,17) -> (22,16)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 6.9 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: 0.5 ns logic, 6.5 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info: 3.6 4.1 Net SOC.GPIOS.gpio_direction[2] (17,21) -> (78,21)
Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info: Defined in:
Info: Risco-5/src/peripheral/gpios.v:16.19-16.33
Info: 0.2 4.3 Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info: 1.0 5.3 Net gpios_$_TBUF__Y_3_E (78,21) -> (81,23)
Info: Sink gpios[2]$tr_io$invert_T.A
Info: 0.2 5.6 Source gpios[2]$tr_io$invert_T.F
Info: 1.2 6.8 Net gpios[2]$tr_io$invert_T$conn$Z (81,23) -> (90,23)
Info: Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 5.8 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 43.61 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.93 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.80 ns
Info: Slack histogram:
Info: legend: * represents 44 endpoint(s)
Info: + represents [1,44) endpoint(s)
Info: [ 17067, 18167) |+
Info: [ 18167, 19267) |+
Info: [ 19267, 20367) |+
Info: [ 20367, 21467) |****+
Info: [ 21467, 22567) |**********+
Info: [ 22567, 23667) |****+
Info: [ 23667, 24767) |***+
Info: [ 24767, 25867) |*****************+
Info: [ 25867, 26967) |************+
Info: [ 26967, 28067) |**+
Info: [ 28067, 29167) |********************************+
Info: [ 29167, 30267) |************************************************************
Info: [ 30267, 31367) |***************+
Info: [ 31367, 32467) |************+
Info: [ 32467, 33567) |**+
Info: [ 33567, 34667) |****+
Info: [ 34667, 35767) |****+
Info: [ 35767, 36867) |******+
Info: [ 36867, 37967) |*********+
Info: [ 37967, 39067) |******+
Info: Program finished normally.
[Pipeline] }
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 655 ; free virtual = 25097
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[30%] Placement Phase 2 completed
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 901 ; free virtual = 25361
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 864 ; free virtual = 25324
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 859 ; free virtual = 25319
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 857 ; free virtual = 25317
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 857 ; free virtual = 25317
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 856 ; free virtual = 25316
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 856 ; free virtual = 25316
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 856 ; free virtual = 25316
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 856 ; free virtual = 25316
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 23|
|3 |LUT1 | 12|
|4 |LUT2 | 179|
|5 |LUT3 | 206|
|6 |LUT4 | 229|
|7 |LUT5 | 366|
|8 |LUT6 | 1543|
|9 |MUXF7 | 424|
|10 |MUXF8 | 2|
|11 |RAM256X1S | 64|
|12 |RAM32M | 2|
|13 |RAM32X1D | 4|
|14 |FDRE | 1846|
|15 |FDSE | 5|
|16 |LD | 4|
|17 |IBUF | 2|
|18 |IOBUF | 8|
|19 |OBUF | 9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 856 ; free virtual = 25316
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 38 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2280.410 ; gain = 508.527 ; free physical = 856 ; free virtual = 25316
Synthesis Optimization Complete : Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.410 ; gain = 656.312 ; free physical = 856 ; free virtual = 25316
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2280.410 ; gain = 0.000 ; free physical = 1131 ; free virtual = 25591
INFO: [Netlist 29-17] Analyzing 531 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2344.406 ; gain = 0.000 ; free physical = 1127 ; free virtual = 25587
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 82 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 8 instances
LD => LDCE: 4 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: ffd0a0d7
INFO: [Common 17-83] Releasing license: Synthesis
76 Infos, 118 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 2344.441 ; gain = 1012.445 ; free physical = 1127 ; free virtual = 25587
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2024.818; main = 1750.352; forked = 422.427
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3218.016; main = 2344.410; forked = 969.652
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2408.438 ; gain = 63.996 ; free physical = 1125 ; free virtual = 25585
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 227672ad7
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2521.250 ; gain = 112.812 ; free physical = 1073 ; free virtual = 25533
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 227672ad7
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 227672ad7
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Phase 1 Initialization | Checksum: 227672ad7
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 227672ad7
Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 227672ad7
Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Phase 2 Timer Update And Timing Data Collection | Checksum: 227672ad7
Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Phase 3 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 227672ad7
Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Retarget | Checksum: 227672ad7
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 227672ad7
Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Constant propagation | Checksum: 227672ad7
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 15f0772e8
Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Sweep | Checksum: 15f0772e8
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 1 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 15f0772e8
Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 792 ; free virtual = 25252
BUFG optimization | Checksum: 15f0772e8
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 15f0772e8
Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 792 ; free virtual = 25252
Shift Register Optimization | Checksum: 15f0772e8
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 222fad2e5
Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 792 ; free virtual = 25252
Post Processing Netlist | Checksum: 222fad2e5
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 761760f6
Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 792 ; free virtual = 25252
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.172 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Phase 9.2 Verifying Netlist Connectivity | Checksum: 761760f6
Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 792 ; free virtual = 25252
Phase 9 Finalization | Checksum: 761760f6
Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 792 ; free virtual = 25252
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 8 | 1 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 761760f6
Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 792 ; free virtual = 25252
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.172 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 761760f6
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.172 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 761760f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.172 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.172 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Ending Netlist Obfuscation Task | Checksum: 761760f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.172 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2802.172 ; gain = 457.730 ; free physical = 792 ; free virtual = 25252
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.188 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 54863e82
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.188 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.188 ; gain = 0.000 ; free physical = 792 ; free virtual = 25252
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1288fef60
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.8 . Memory (MB): peak = 2834.188 ; gain = 0.000 ; free physical = 787 ; free virtual = 25247
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1915b685f
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 779 ; free virtual = 25239
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1915b685f
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 779 ; free virtual = 25239
Phase 1 Placer Initialization | Checksum: 1915b685f
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 779 ; free virtual = 25239
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1f285648d
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 774 ; free virtual = 25234
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 222586e40
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 774 ; free virtual = 25234
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 222586e40
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 774 ; free virtual = 25234
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1dda86beb
Time (s): cpu = 00:00:15 ; elapsed = 00:00:04 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 776 ; free virtual = 25236
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 74 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 30 nets or LUTs. Breaked 0 LUT, combined 30 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
[50%] Placement Phase 3 completed
Running routing......
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 773 ; free virtual = 25233
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 30 | 30 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 30 | 30 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 222a8c92d
Time (s): cpu = 00:00:15 ; elapsed = 00:00:04 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 773 ; free virtual = 25233
Phase 2.4 Global Placement Core | Checksum: 19df3f14a
Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 773 ; free virtual = 25233
Phase 2 Global Placement | Checksum: 19df3f14a
Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 773 ; free virtual = 25233
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1da0d26de
Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 773 ; free virtual = 25233
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14f68d545
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 773 ; free virtual = 25233
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: e40f892f
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 773 ; free virtual = 25233
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 184eae3b6
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 773 ; free virtual = 25233
Phase 3.5 Small Shape Detail Placement
[60%] Routing Phase 0 completed
Phase 3.5 Small Shape Detail Placement | Checksum: 1a30c6f5f
Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 714 ; free virtual = 25174
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 153c997f4
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 720 ; free virtual = 25180
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: b4963e6d
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 720 ; free virtual = 25180
Phase 3 Detail Placement | Checksum: b4963e6d
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 719 ; free virtual = 25178
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 14202c8cc
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.882 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 13a749736
Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 720 ; free virtual = 25180
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 13a749736
Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 720 ; free virtual = 25180
Phase 4.1.1.1 BUFG Insertion | Checksum: 14202c8cc
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 720 ; free virtual = 25180
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 148ce00ef
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 720 ; free virtual = 25180
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 720 ; free virtual = 25180
Phase 4.1 Post Commit Optimization | Checksum: 148ce00ef
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 720 ; free virtual = 25180
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 148ce00ef
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 720 ; free virtual = 25180
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 1x1|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 148ce00ef
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 720 ; free virtual = 25180
Phase 4.3 Placer Reporting | Checksum: 148ce00ef
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 720 ; free virtual = 25180
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 720 ; free virtual = 25180
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 720 ; free virtual = 25180
Phase 4 Post Placement Optimization and Clean-Up | Checksum: b859b2d9
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 720 ; free virtual = 25180
Ending Placer Task | Checksum: 886f26ac
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 720 ; free virtual = 25180
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:09 . Memory (MB): peak = 2841.215 ; gain = 39.043 ; free physical = 720 ; free virtual = 25180
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 718 ; free virtual = 25177
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 718 ; free virtual = 25178
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 202e8af7 ConstDB: 0 ShapeSum: 68409bb5 RouteDB: 0
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Post Restoration Checksum: NetGraph: 3038c18c | NumContArr: 92933846 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2481def0c
Time (s): cpu = 00:00:33 ; elapsed = 00:00:26 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 689 ; free virtual = 25150
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2481def0c
Time (s): cpu = 00:00:33 ; elapsed = 00:00:26 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 691 ; free virtual = 25151
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2481def0c
Time (s): cpu = 00:00:33 ; elapsed = 00:00:26 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 691 ; free virtual = 25151
Running timing analysis......
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2037fefa4
Time (s): cpu = 00:00:36 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 663 ; free virtual = 25123
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 |
Router Utilization Summary
Global Vertical Routing Utilization = 0.000522261 %
Global Horizontal Routing Utilization = 0.000426257 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 3688
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 3684
Number of Partially Routed Nets = 4
Number of Node Overlaps = 2
Phase 2 Router Initialization | Checksum: 1cbbdcb80
Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 656 ; free virtual = 25116
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 1cbbdcb80
Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 656 ; free virtual = 25116
Phase 3.2 Initial Net Routing
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Phase 3.2 Initial Net Routing | Checksum: 283f7a0bf
Time (s): cpu = 00:00:40 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 656 ; free virtual = 25116
Phase 3 Initial Routing | Checksum: 283f7a0bf
Time (s): cpu = 00:00:40 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 656 ; free virtual = 25116
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 539
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.540 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 2bafb011f
Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
Phase 4 Rip-up And Reroute | Checksum: 2bafb011f
Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 2bafb011f
Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 2bafb011f
Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
Phase 5 Delay and Skew Optimization | Checksum: 2bafb011f
Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 25f31c6bd
Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 25f31c6bd
Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
Phase 6 Post Hold Fix | Checksum: 25f31c6bd
Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.781042 %
Global Horizontal Routing Utilization = 1.02501 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 25f31c6bd
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 25f31c6bd
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1bfee8859
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1bfee8859
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 12d5629b0
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
Ending Routing Task | Checksum: 12d5629b0
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:31 . Memory (MB): peak = 2841.215 ; gain = 0.000 ; free physical = 643 ; free virtual = 25103
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (2150)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (7021)
5. checking no_input_delay (9)
6. checking no_output_delay (17)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (2150)
---------------------------
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[37]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[38]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[40]/Q (HIGH)
There are 2138 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (7021)
---------------------------------------------------
There are 7021 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (9)
------------------------------
There are 9 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (17)
--------------------------------
There are 17 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Tue Jun 4 02:07:09 2024
[Pipeline] }
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
[Pipeline] // stage
[Pipeline] }
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[40]_1[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 3156.340 ; gain = 243.238 ; free physical = 629 ; free virtual = 25102
INFO: [Common 17-206] Exiting Vivado at Tue Jun 4 02:07:28 2024...
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
[Pipeline] }
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Parse file DONE
Erase SRAM Load SRAM Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
Loading: [====== ] 11.18%[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Load SRAM: [====== ] 10.28%
Loading: [============ ] 22.36%
Load SRAM: [=========== ] 20.56%
Loading: [================= ] 33.54%
Loading: [======================= ] 44.72%
Load SRAM: [================ ] 30.83%
Load SRAM: [===================== ] 41.11%
Loading: [============================ ] 55.90%
Loading: [================================== ] 67.08%
Load SRAM: [========================== ] 51.39%
Loading: [======================================== ] 78.26%
Load SRAM: [=============================== ] 61.67%
Loading: [============================================= ] 89.44%
Load SRAM: [==================================== ] 71.94%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Load SRAM: [========================================== ] 82.22%Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Load SRAM: [=============================================== ] 92.50%
Load SRAM: [==================================================] 100.00%
Done
DONE
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
[Pipeline] }
+ echo testando na tang nano
testando na tang nano
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
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