Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 5804/43848 13%
Info: logic LUTs: 3820/43848 8%
Info: carry LUTs: 136/43848 0%
Info: RAM LUTs: 1232/ 5481 22%
Info: RAMW LUTs: 616/10962 5%
Info: Total DFFs: 778/43848 1%
Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 342 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x8fafb922
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 778/43848 1%
Info: TRELLIS_COMB: 5870/43848 13%
Info: TRELLIS_RAMW: 308/ 5481 5%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 3368 cells, random placement wirelen = 293299.
Info: at initial placer iter 0, wirelen = 1961
Info: at initial placer iter 1, wirelen = 1576
Info: at initial placer iter 2, wirelen = 1492
Info: at initial placer iter 3, wirelen = 1455
Info: Running main analytical placer, max placement attempts per cell = 6081328.
Info: at iteration #1, type ALL: wirelen solved = 1453, spread = 37545, legal = 38085; time = 0.16s
Info: at iteration #2, type ALL: wirelen solved = 4008, spread = 31078, legal = 31710; time = 0.17s
Info: at iteration #3, type ALL: wirelen solved = 6402, spread = 30874, legal = 31639; time = 0.20s
Info: at iteration #4, type ALL: wirelen solved = 8142, spread = 27989, legal = 28689; time = 0.24s
Info: at iteration #5, type ALL: wirelen solved = 9558, spread = 25999, legal = 26760; time = 0.22s
Info: at iteration #6, type ALL: wirelen solved = 10114, spread = 25848, legal = 26529; time = 0.21s
Info: at iteration #7, type ALL: wirelen solved = 11504, spread = 24303, legal = 25132; time = 0.15s
Info: at iteration #8, type ALL: wirelen solved = 12147, spread = 24200, legal = 24934; time = 0.15s
Info: at iteration #9, type ALL: wirelen solved = 13138, spread = 23800, legal = 24541; time = 0.15s
Info: at iteration #10, type ALL: wirelen solved = 13770, spread = 23291, legal = 24131; time = 0.15s
Info: at iteration #11, type ALL: wirelen solved = 14336, spread = 22891, legal = 23670; time = 0.15s
Info: at iteration #12, type ALL: wirelen solved = 14643, spread = 22835, legal = 23715; time = 0.17s
Info: at iteration #13, type ALL: wirelen solved = 15100, spread = 22523, legal = 23407; time = 0.15s
Info: at iteration #14, type ALL: wirelen solved = 15355, spread = 22133, legal = 22918; time = 0.14s
Info: at iteration #15, type ALL: wirelen solved = 15421, spread = 22592, legal = 23325; time = 0.15s
Info: at iteration #16, type ALL: wirelen solved = 15930, spread = 21890, legal = 22779; time = 0.20s
Info: at iteration #17, type ALL: wirelen solved = 15980, spread = 22289, legal = 23049; time = 0.21s
Info: at iteration #18, type ALL: wirelen solved = 16141, spread = 22532, legal = 23293; time = 0.22s
Info: at iteration #19, type ALL: wirelen solved = 16485, spread = 23639, legal = 24103; time = 0.21s
Info: at iteration #20, type ALL: wirelen solved = 17586, spread = 23480, legal = 23921; time = 0.21s
Info: at iteration #21, type ALL: wirelen solved = 17682, spread = 26281, legal = 26588; time = 0.20s
Info: HeAP Placer Time: 5.73s
Info: of which solving equations: 3.55s
Info: of which spreading cells: 0.44s
Info: of which strict legalisation: 0.14s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 2670, wirelen = 22779
Info: at iteration #5: temp = 0.000000, timing cost = 2915, wirelen = 20998
Info: at iteration #10: temp = 0.000000, timing cost = 3601, wirelen = 20294
Info: at iteration #15: temp = 0.000000, timing cost = 3362, wirelen = 20117
Info: at iteration #20: temp = 0.000000, timing cost = 3358, wirelen = 20073
Info: at iteration #20: temp = 0.000000, timing cost = 3352, wirelen = 20076
Info: SA placement time 13.38s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 33.24 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.35 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.68 ns
Info: Slack histogram:
Info: legend: * represents 37 endpoint(s)
Info: + represents [1,37) endpoint(s)
Info: [ 9914, 11381) |+
Info: [ 11381, 12848) |
Info: [ 12848, 14315) |+
Info: [ 14315, 15782) |*+
Info: [ 15782, 17249) |**+
Info: [ 17249, 18716) |*********+
Info: [ 18716, 20183) |******+
Info: [ 20183, 21650) |*************+
Info: [ 21650, 23117) |*******************+
Info: [ 23117, 24584) |*********+
Info: [ 24584, 26051) |******************************************************+
Info: [ 26051, 27518) |************************************************************
Info: [ 27518, 28985) |******+
Info: [ 28985, 30452) |*************************+
Info: [ 30452, 31919) |***+
Info: [ 31919, 33386) |***+
Info: [ 33386, 34853) |*******+
Info: [ 34853, 36320) |***********+
Info: [ 36320, 37787) |**********+
Info: [ 37787, 39254) |*******+
Info: Checksum: 0x845f82aa
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 28047 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 106 893 | 106 893 | 27184| 0.61 0.61|
Info: 2000 | 259 1740 | 153 847 | 26438| 0.31 0.92|
Info: 3000 | 476 2523 | 217 783 | 25881| 0.37 1.29|
Info: 4000 | 657 3342 | 181 819 | 25227| 0.35 1.64|
Info: 5000 | 877 4122 | 220 780 | 24575| 0.28 1.92|
Info: 6000 | 1050 4949 | 173 827 | 23991| 0.26 2.18|
Info: 7000 | 1279 5720 | 229 771 | 23290| 0.27 2.45|
Info: 8000 | 1499 6500 | 220 780 | 22601| 0.25 2.69|
Info: 9000 | 1723 7276 | 224 776 | 22100| 0.29 2.98|
Info: 10000 | 1989 8010 | 266 734 | 21535| 0.33 3.31|
Info: 11000 | 2285 8714 | 296 704 | 20991| 0.27 3.58|
Info: 12000 | 2569 9430 | 284 716 | 20364| 0.27 3.85|
Info: 13000 | 2817 10182 | 248 752 | 19685| 0.28 4.13|
Info: 14000 | 3108 10891 | 291 709 | 19023| 0.32 4.45|
Info: 15000 | 3354 11645 | 246 754 | 18352| 0.33 4.78|
Info: 16000 | 3592 12407 | 238 762 | 17747| 0.33 5.11|
Info: 17000 | 3841 13158 | 249 751 | 17080| 0.33 5.44|
Info: 18000 | 4124 13875 | 283 717 | 16456| 0.32 5.75|
Info: 19000 | 4475 14524 | 351 649 | 15955| 0.31 6.07|
Info: 20000 | 4756 15243 | 281 719 | 15327| 0.36 6.42|
Info: 21000 | 5028 15971 | 272 728 | 14840| 0.33 6.76|
Info: 22000 | 5423 16576 | 395 605 | 14365| 0.34 7.10|
Info: 23000 | 5856 17143 | 433 567 | 13924| 0.40 7.49|
Info: 24000 | 6084 17915 | 228 772 | 13780| 0.34 7.84|
Info: 25000 | 6318 18681 | 234 766 | 13235| 0.32 8.15|
Info: 26000 | 6614 19385 | 296 704 | 12936| 0.33 8.49|
Info: 27000 | 7116 19883 | 502 498 | 12555| 0.31 8.79|
Info: 28000 | 7579 20420 | 463 537 | 12163| 0.34 9.14|
Info: 29000 | 7903 21096 | 324 676 | 11871| 0.35 9.48|
Info: 30000 | 8302 21697 | 399 601 | 11403| 0.35 9.83|
Info: 31000 | 8661 22330 | 359 633 | 11092| 0.39 10.23|
Info: 32000 | 9078 22873 | 417 543 | 10610| 0.32 10.54|
Info: 33000 | 9428 23415 | 350 542 | 10062| 0.29 10.83|
Info: 34000 | 9808 23944 | 380 529 | 9542| 0.29 11.13|
Info: 35000 | 10142 24522 | 334 578 | 8922| 0.26 11.38|
Info: 36000 | 10433 25094 | 291 572 | 8281| 0.25 11.63|
Info: 37000 | 10724 25725 | 291 631 | 7631| 0.24 11.87|
Info: 38000 | 11001 26437 | 277 712 | 7182| 0.31 12.18|
Info: 39000 | 11453 26979 | 452 542 | 6677| 0.35 12.53|
Info: 40000 | 11840 27588 | 387 609 | 6153| 0.38 12.91|
Info: 41000 | 11962 28462 | 122 874 | 5289| 0.22 13.13|
Info: 42000 | 11983 29440 | 21 978 | 4310| 0.08 13.21|
Info: 43000 | 11999 30423 | 16 983 | 3329| 0.09 13.29|
Info: 44000 | 12046 31371 | 47 948 | 2378| 0.15 13.45|
Info: 45000 | 12151 32253 | 105 882 | 1496| 0.23 13.68|
Info: 46000 | 12257 33085 | 106 832 | 618| 0.26 13.94|
Info: 46641 | 12273 33418 | 16 333 | 0| 0.13 14.07|
Info: Routing complete.
Info: Router1 time 14.07s
Info: Checksum: 0x463d0ac0
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_1.Q
Info: 0.7 1.3 Net SOC.Uart.response_LUT4_B_Z_LUT4_Z_3_B_LUT4_Z_C[0] (41,23) -> (42,23)
Info: Sink SOC.Uart.response_LUT4_B_Z_LUT4_Z_1_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 1.5 Source SOC.Uart.response_LUT4_B_Z_LUT4_Z_1_C_LUT4_Z.F
Info: 1.0 2.5 Net SOC.Uart.response_LUT4_B_Z_LUT4_Z_1_C[4] (42,23) -> (36,23)
Info: Sink SOC.Core.RegisterBank.registers.0.3_DO_2_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 2.8 Source SOC.Core.RegisterBank.registers.0.3_DO_2_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.9 3.7 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_4_A_LUT4_Z_A_LUT4_D_Z_LUT4_B_Z_LUT4_B_Z_LUT4_Z_B_LUT4_B_Z_LUT4_Z_D[0] (36,23) -> (30,23)
Info: Sink SOC.Core.RegisterBank.registers.0.3_DO_LUT4_A_Z_LUT4_Z_1_D_L6MUX21_Z_SD_L6MUX21_SD_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.9 Source SOC.Core.RegisterBank.registers.0.3_DO_LUT4_A_Z_LUT4_Z_1_D_L6MUX21_Z_SD_L6MUX21_SD_Z_LUT4_Z.F
Info: 0.7 4.6 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_Z_LUT4_Z_C_LUT4_C_Z_LUT4_C_Z[1] (30,23) -> (28,23)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 5.0 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 5.0 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0 (28,23) -> (28,23)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.50-157.52
Info: 0.2 5.3 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 5.3 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D0 (28,23) -> (28,23)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.66-157.68
Info: 0.2 5.5 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_SD_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.9 6.4 Net SOC.Core.CSR_Unit.csr_mstatus_mie_LUT4_B_C_LUT4_Z_C_LUT4_Z_D_LUT4_Z_C[3] (28,23) -> (28,21)
Info: Sink SOC.Core.RegisterBank.registers.0.3_DO_LUT4_A_Z_LUT4_Z_1_D_LUT4_A.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.6 Source SOC.Core.RegisterBank.registers.0.3_DO_LUT4_A_Z_LUT4_Z_1_D_LUT4_A.F
Info: 1.6 8.2 Net SOC.Core.CSR_Unit.csr_mstatus_mie_LUT4_B_C_LUT4_Z_C_LUT4_Z_C[1] (28,21) -> (28,9)
Info: Sink SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 8.5 Source SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.4 8.9 Net SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z[2] (28,9) -> (28,9)
Info: Sink SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 9.1 Source SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A.F
Info: 0.8 9.9 Net SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z[4] (28,9) -> (30,12)
Info: Sink SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_LUT4_A.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 10.2 Source SOC.Core.RegisterBank.registers.0.5_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_LUT4_A.OFX
Info: 1.5 11.7 Net SOC.Core.RegisterBank.registers.0.3_DO_3_LUT4_A_Z_LUT4_B_Z_PFUMX_C0_Z[3] (30,12) -> (34,17)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 12.0 Source SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 12.0 Net SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT (34,17) -> (34,17)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.30-141.32
Info: 0.2 12.1 Source SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 12.1 Net SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1 (34,17) -> (34,17)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 12.4 Source SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.2 13.6 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_9_B_LUT4_Z_D_PFUMX_Z_C0_LUT4_Z_D_LUT4_D_Z_L6MUX21_Z_SD_LUT4_Z_B[6] (34,17) -> (38,25)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_C_LUT4_C_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.8 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_C_LUT4_C_1.F
Info: 0.7 14.5 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_PFUMX_Z_C0[3] (38,25) -> (37,25)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 14.9 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 14.9 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 (37,25) -> (37,25)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64
Info: 0.2 15.2 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 15.2 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1 (37,25) -> (37,25)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 15.4 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 16.7 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_L6MUX21_Z_SD_PFUMX_C0_Z[4] (37,25) -> (41,21)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_COUT_CCU2C_CIN_S0_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 16.9 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_COUT_CCU2C_CIN_S0_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z.F
Info: 1.0 17.9 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_COUT_CCU2C_CIN_S0_LUT4_D_Z_PFUMX_C0_Z[3] (41,21) -> (42,16)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 18.3 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 18.3 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_L6MUX21_Z_D1 (42,16) -> (42,16)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 18.5 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 19.8 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z[3] (42,16) -> (31,17)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 20.1 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_LUT4_C.F
Info: 0.7 20.8 Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_ALUT_LUT4_Z_A_L6MUX21_SD_Z_LUT4_Z_1_D_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_C_1_Z_CCU2C_S1_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_A_Z_LUT4_C_Z[5] (31,17) -> (31,16)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 21.0 Source SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 21.0 Net SOC.Core.Pc.load_L6MUX21_Z_D1 (31,16) -> (31,16)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 21.3 Source SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.7 22.9 Net SOC.Core.pc_load (31,16) -> (27,3)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_17.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:50.32-50.39
Info: 0.0 22.9 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_17.CE
Info: 6.5 ns logic, 16.4 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[2]$tr_io.O
Info: 4.9 4.9 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (20,21)
Info: Sink SOC.GPIOS.Gpios[2].data_in_LUT4_C.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 5.1 Source SOC.GPIOS.Gpios[2].data_in_LUT4_C.F
Info: 0.8 5.9 Net SOC.GPIOS.Gpios[2].data_in_LUT4_C_Z[2] (20,21) -> (20,17)
Info: Sink SOC.Core.read_data_LUT4_Z_19.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.1 Source SOC.Core.read_data_LUT4_Z_19.F
Info: 0.8 6.9 Net SOC.read_data[2] (20,17) -> (22,16)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 6.9 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: 0.5 ns logic, 6.5 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info: 3.6 4.1 Net SOC.GPIOS.gpio_direction[2] (17,21) -> (78,21)
Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info: Defined in:
Info: Risco-5/src/peripheral/gpios.v:16.19-16.33
Info: 0.2 4.3 Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info: 1.0 5.3 Net gpios_$_TBUF__Y_3_E (78,21) -> (81,23)
Info: Sink gpios[2]$tr_io$invert_T.A
Info: 0.2 5.6 Source gpios[2]$tr_io$invert_T.F
Info: 1.2 6.8 Net gpios[2]$tr_io$invert_T$conn$Z (81,23) -> (90,23)
Info: Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 5.8 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 43.61 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.93 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.80 ns
Info: Slack histogram:
Info: legend: * represents 44 endpoint(s)
Info: + represents [1,44) endpoint(s)
Info: [ 17067, 18167) |+
Info: [ 18167, 19267) |+
Info: [ 19267, 20367) |+
Info: [ 20367, 21467) |****+
Info: [ 21467, 22567) |**********+
Info: [ 22567, 23667) |****+
Info: [ 23667, 24767) |***+
Info: [ 24767, 25867) |*****************+
Info: [ 25867, 26967) |************+
Info: [ 26967, 28067) |**+
Info: [ 28067, 29167) |********************************+
Info: [ 29167, 30267) |************************************************************
Info: [ 30267, 31367) |***************+
Info: [ 31367, 32467) |************+
Info: [ 32467, 33567) |**+
Info: [ 33567, 34667) |****+
Info: [ 34667, 35767) |****+
Info: [ 35767, 36867) |******+
Info: [ 36867, 37967) |*********+
Info: [ 37967, 39067) |******+
Info: Program finished normally.
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