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INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter BUFFER_SIZE bound to: 16 - type: integer
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
Parameter DEPTH bound to: 16 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
Parameter WIDHT bound to: 8 - type: integer
INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:160]
WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module LEDs is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2116.238 ; gain = 491.652 ; free physical = 5695 ; free virtual = 25906
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2131.082 ; gain = 506.496 ; free physical = 5695 ; free virtual = 25906
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2131.082 ; gain = 506.496 ; free physical = 5695 ; free virtual = 25906
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2131.082 ; gain = 0.000 ; free physical = 5694 ; free virtual = 25904
Info: at iteration #5: temp = 0.000000, timing cost = 2902, wirelen = 23090
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2280.832 ; gain = 0.000 ; free physical = 5674 ; free virtual = 25884
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2280.867 ; gain = 0.000 ; free physical = 5673 ; free virtual = 25883
Info: at iteration #10: temp = 0.000000, timing cost = 2741, wirelen = 22229
Info: at iteration #15: temp = 0.000000, timing cost = 2518, wirelen = 21852
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5647 ; free virtual = 25860
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5647 ; free virtual = 25860
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5647 ; free virtual = 25860
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 00000000000000000000000000000000000000000000001 | 000000
VALIDATE_FETCH | 00000000000000000000000000000000000000000000010 | 101110
DECODE | 00000000000000000000000000000000000000000000100 | 000001
MEMADR | 00000000000000000000000000000000000000000001000 | 000010
MEMREAD_UNALIGNED | 00000000000000000000000000000000000000000010000 | 010110
LOAD_FIRST_BLOCK | 00000000000000000000000000000000000000000100000 | 010000
SAVE_FIRST_BLOCK | 00000000000000000000000000000000000000001000000 | 010001
CALC_NEXT_ADDRESS | 00000000000000000000000000000000000000010000000 | 010010
READ_SECOND_BLOCK | 00000000000000000000000000000000000000100000000 | 010011
LOAD_SECOND_BLOCK | 00000000000000000000000000000000000001000000000 | 010100
MERGE_BLOCKS | 00000000000000000000000000000000000010000000000 | 010101
FILTER_ALU_WB | 00000000000000000000000000000000000100000000000 | 010111
MEMREAD | 00000000000000000000000000000000001000000000000 | 000011
MEMWB | 00000000000000000000000000000000010000000000000 | 000100
MEMWRITE_UNALIGNED | 00000000000000000000000000000000100000000000000 | 011000
GEN_FIRST_BLOCK_PART_1 | 00000000000000000000000000000001000000000000000 | 011001
GEN_FIRST_BLOCK_PART_2 | 00000000000000000000000000000010000000000000000 | 011010
GEN_SECOND_BLOCK_PART_1 | 00000000000000000000000000000100000000000000000 | 011011
GEN_SECOND_BLOCK_PART_2 | 00000000000000000000000000001000000000000000000 | 011100
MERGE_WRITE_BLOCKS | 00000000000000000000000000010000000000000000000 | 011101
SWAP_VALUE_DIRECTION | 00000000000000000000000000100000000000000000000 | 011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 00000000000000000000000001000000000000000000000 | 100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 00000000000000000000000010000000000000000000000 | 100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 00000000000000000000000100000000000000000000000 | 100100
CLEAR_VALUE | 00000000000000000000001000000000000000000000000 | 011111
MERGE_WRITE_VALUE_1 | 00000000000000000000010000000000000000000000000 | 100000
WRITE_VALUE_1 | 00000000000000000000100000000000000000000000000 | 100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 00000000000000000001000000000000000000000000000 | 100101
READ_SECOND_BLOCK_TO_WRITE | 00000000000000000010000000000000000000000000000 | 100110
LOAD_SECOND_BLOCK_TO_WRITE | 00000000000000000100000000000000000000000000000 | 100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 00000000000000001000000000000000000000000000000 | 101000
SWAP_VALUE_DIRECTION_2 | 00000000000000010000000000000000000000000000000 | 101001
CLEAR_VALUE_PART_2 | 00000000000000100000000000000000000000000000000 | 101010
CLEAR_VALUE_PART_2_1 | 00000000000001000000000000000000000000000000000 | 101011
MERGE_WRITE_VALUE_2 | 00000000000010000000000000000000000000000000000 | 101100
WRITE_VALUE_2 | 00000000000100000000000000000000000000000000000 | 101101
MEMWRITE | 00000000001000000000000000000000000000000000000 | 000101
EXECUTER | 00000000010000000000000000000000000000000000000 | 000110
EXECUTEI | 00000000100000000000000000000000000000000000000 | 001000
JAL | 00000001000000000000000000000000000000000000000 | 001001
BRANCH | 00000010000000000000000000000000000000000000000 | 001010
AUIPC | 00000100000000000000000000000000000000000000000 | 001100
LUI | 00001000000000000000000000000000000000000000000 | 001101
JALR_PC | 00010000000000000000000000000000000000000000000 | 001110
JALR | 00100000000000000000000000000000000000000000000 | 001011
ALUWB | 01000000000000000000000000000000000000000000000 | 000111
EXECUTECSR | 10000000000000000000000000000000000000000000000 | 001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 0000 | 0000
COPY_WRITE_BUFFER | 0001 | 0100
WRITE | 0010 | 0010
READ | 0011 | 0001
READ_RX_FIFO_EMPTY | 0100 | 0110
READ_TX_FIFO_EMPTY | 0101 | 0111
READ_RX_FIFO_FULL | 0110 | 1000
READ_TX_FIFO_FULL | 0111 | 1001
WB | 1000 | 0101
FINISH | 1001 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5632 ; free virtual = 25847
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
3 Input 32 Bit Adders := 1
2 Input 10 Bit Adders := 2
2 Input 6 Bit Adders := 6
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 2
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
+---XORs :
2 Bit Wide XORs := 1
+---Registers :
64 Bit Registers := 2
33 Bit Registers := 1
32 Bit Registers := 50
10 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 5
4 Bit Registers := 2
3 Bit Registers := 1
1 Bit Registers := 12
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
128 Bit (16 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 1
47 Input 47 Bit Muxes := 1
2 Input 47 Bit Muxes := 17
11 Input 47 Bit Muxes := 1
3 Input 33 Bit Muxes := 1
2 Input 32 Bit Muxes := 8
8 Input 32 Bit Muxes := 1
15 Input 32 Bit Muxes := 1
6 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 1
10 Input 32 Bit Muxes := 2
2 Input 8 Bit Muxes := 3
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
47 Input 4 Bit Muxes := 1
9 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 2
23 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
6 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
4 Input 3 Bit Muxes := 2
47 Input 3 Bit Muxes := 3
10 Input 3 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 16
47 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 4
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 68
47 Input 1 Bit Muxes := 12
4 Input 1 Bit Muxes := 3
6 Input 1 Bit Muxes := 5
10 Input 1 Bit Muxes := 8
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":226)
WARN (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":152)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
Info: at iteration #20: temp = 0.000000, timing cost = 2522, wirelen = 21719
Info: at iteration #23: temp = 0.000000, timing cost = 2401, wirelen = 21694
Info: SA placement time 16.21s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 32.74 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.99 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.52 ns
Info: Slack histogram:
Info: legend: * represents 53 endpoint(s)
Info: + represents [1,53) endpoint(s)
Info: [ 9460, 10949) |+
Info: [ 10949, 12438) |
Info: [ 12438, 13927) |+
Info: [ 13927, 15416) |+
Info: [ 15416, 16905) |**+
Info: [ 16905, 18394) |***+
Info: [ 18394, 19883) |******+
Info: [ 19883, 21372) |****+
Info: [ 21372, 22861) |*****+
Info: [ 22861, 24350) |*****************+
Info: [ 24350, 25839) |******+
Info: [ 25839, 27328) |************************************************************
Info: [ 27328, 28817) |**********************************+
Info: [ 28817, 30306) |****+
Info: [ 30306, 31795) |*+
Info: [ 31795, 33284) |**+
Info: [ 33284, 34773) |********+
Info: [ 34773, 36262) |************+
Info: [ 36262, 37751) |****+
Info: [ 37751, 39240) |*******+
Info: Checksum: 0xb787c032
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 28382 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 156 843 | 156 843 | 27580| 0.60 0.60|
Info: 2000 | 278 1721 | 122 878 | 26831| 0.26 0.86|
Info: 3000 | 417 2582 | 139 861 | 26071| 0.26 1.12|
Info: 4000 | 572 3427 | 155 845 | 25311| 0.25 1.37|
Info: 5000 | 713 4286 | 141 859 | 24564| 0.26 1.62|
[10%] Placement Phase 0 completed
Info: 6000 | 860 5139 | 147 853 | 23797| 0.27 1.89|
Info: 7000 | 1044 5955 | 184 816 | 23102| 0.29 2.18|
Info: 8000 | 1216 6783 | 172 828 | 22412| 0.27 2.45|
Info: 9000 | 1425 7574 | 209 791 | 21692| 0.29 2.74|
[20%] Placement Phase 1 completed
Info: 10000 | 1641 8358 | 216 784 | 20969| 0.26 3.00|
Info: 11000 | 1830 9169 | 189 811 | 20407| 0.26 3.26|
Info: 12000 | 2068 9931 | 238 762 | 19813| 0.29 3.54|
Info: 13000 | 2271 10728 | 203 797 | 19093| 0.28 3.83|
Info: 14000 | 2533 11466 | 262 738 | 18475| 0.29 4.12|
Info: 15000 | 2837 12162 | 304 696 | 17984| 0.32 4.44|
Info: 16000 | 3035 12964 | 198 802 | 17241| 0.30 4.74|
Info: 17000 | 3358 13641 | 323 677 | 16644| 0.33 5.06|
Info: 18000 | 3599 14400 | 241 759 | 15934| 0.32 5.38|
Info: 19000 | 3888 15111 | 289 711 | 15422| 0.39 5.78|
Info: 20000 | 4234 15765 | 346 654 | 14864| 0.33 6.11|
Info: 21000 | 4551 16448 | 317 683 | 14264| 0.30 6.41|
Info: 22000 | 4819 17180 | 268 732 | 13741| 0.30 6.72|
Info: 23000 | 5248 17751 | 429 571 | 13322| 0.32 7.04|
Info: 24000 | 5723 18276 | 475 525 | 12936| 0.31 7.34|
Info: 25000 | 6127 18872 | 404 596 | 12503| 0.29 7.63|
Info: 26000 | 6492 19507 | 365 635 | 11986| 0.34 7.97|
Info: 27000 | 6801 20190 | 309 683 | 11340| 0.30 8.27|
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5487 ; free virtual = 25708
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Info: 28000 | 7091 20809 | 290 619 | 10666| 0.26 8.54|
Info: 29000 | 7495 21296 | 404 487 | 10099| 0.26 8.80|
Info: 30000 | 7890 21841 | 395 545 | 9557| 0.28 9.08|
Info: 31000 | 8265 22415 | 375 574 | 9031| 0.30 9.39|
Info: 32000 | 8529 23009 | 264 594 | 8338| 0.24 9.62|
Info: 33000 | 8762 23696 | 233 687 | 7600| 0.21 9.83|
Info: 34000 | 9073 24362 | 311 666 | 6941| 0.23 10.07|
Info: 35000 | 9402 25025 | 329 663 | 6287| 0.25 10.32|
Info: 36000 | 9715 25708 | 313 683 | 5677| 0.33 10.66|
Info: 37000 | 9770 26649 | 55 941 | 4734| 0.13 10.79|
Info: 38000 | 9777 27638 | 7 989 | 3741| 0.06 10.85|
Info: 39000 | 9803 28600 | 26 962 | 2771| 0.08 10.93|
Info: 40000 | 9873 29524 | 70 924 | 1850| 0.22 11.15|
Info: 41000 | 10000 30343 | 127 819 | 998| 0.28 11.42|
Info: 42000 | 10037 31009 | 37 666 | 52| 0.22 11.64|
Info: 42051 | 10037 31028 | 0 19 | 0| 0.06 11.70|
Info: Routing complete.
Info: Router1 time 11.70s
Info: Checksum: 0x5e635f5b
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.temp_address_TRELLIS_FF_Q_31.Q
Info: 0.9 1.4 Net SOC.Core.temp_address[0] (18,33) -> (16,33)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/core/core.v:62.47-62.59
Info: 0.2 1.6 Source SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_Z.F
Info: 1.3 2.9 Net SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C[0] (16,33) -> (34,30)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A.A
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 3.3 Source SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A.OFX
Info: 0.0 3.3 Net SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A_Z_PFUMX_BLUT_Z (34,30) -> (34,30)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A_Z_PFUMX_BLUT_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.54-157.56
Info: 0.2 3.6 Source SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A_Z_PFUMX_BLUT_ALUT_LUT4_Z.OFX
Info: 0.0 3.6 Net SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_D0 (34,30) -> (34,30)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.66-157.68
Info: 0.2 3.8 Source SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.7 4.5 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_3_C_LUT4_Z_D_LUT4_D_B_LUT4_Z_D_LUT4_Z_C_L6MUX21_SD_Z_PFUMX_Z_ALUT_LUT4_Z_D[4] (34,30) -> (30,30)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_3_C_LUT4_Z_D_LUT4_D_B_LUT4_Z_D_LUT4_Z_C_L6MUX21_SD_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 4.8 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_3_C_LUT4_Z_D_LUT4_D_B_LUT4_Z_D_LUT4_Z_C_L6MUX21_SD_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 1.9 6.6 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_3_C_LUT4_Z_D_LUT4_D_B_LUT4_Z_D_LUT4_Z_C_L6MUX21_SD_Z[3] (30,30) -> (14,26)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 6.9 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.7 7.6 Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_BLUT_Z[6] (14,26) -> (14,25)
Info: Sink SOC.Core.RegisterBank.registers.0.3_DO_2_LUT4_A_Z_PFUMX_BLUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 7.8 Source SOC.Core.RegisterBank.registers.0.3_DO_2_LUT4_A_Z_PFUMX_BLUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.6 8.4 Net SOC.Core.RegisterBank.registers.0.3_DO_2_LUT4_A_Z_PFUMX_BLUT_Z[5] (14,25) -> (15,25)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 8.7 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 8.7 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1 (15,25) -> (15,25)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 8.9 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 10.2 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z[1] (15,25) -> (21,20)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_D_LUT4_A.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.5 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_D_LUT4_A.F
Info: 1.4 11.9 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_D_LUT4_A_Z[5] (21,20) -> (22,29)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_C0_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 12.2 Source SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_C0_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 13.4 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_D_LUT4_C_Z_LUT4_C_1_Z[5] (22,29) -> (17,26)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_PFUMX_Z_C0_LUT4_Z_D_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 13.7 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_PFUMX_Z_C0_LUT4_Z_D_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.0 14.7 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_PFUMX_Z_C0_LUT4_Z_D[6] (17,26) -> (23,25)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z_C_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 14.9 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z_C_LUT4_Z_1.F
Info: 0.4 15.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z_C[2] (23,25) -> (23,25)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 15.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z.F
Info: 1.3 16.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z[3] (23,25) -> (18,28)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_BLUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 17.2 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_BLUT_LUT4_Z.OFX
Info: 1.2 18.5 Net SOC.Core.alu_out[11] (18,28) -> (17,33)
Info: Sink SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_C_1_D_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: Risco-5/src/core/core.v:58.31-58.38
Info: 0.3 18.8 Source SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_C_1_D_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.2 20.0 Net SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_C_1_D_LUT4_C_Z[1] (17,33) -> (20,27)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 20.2 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 20.2 Net SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT (20,27) -> (20,27)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.30-141.32
Info: 0.2 20.4 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 20.4 Net SOC.Core.Pc.load_L6MUX21_Z_D1 (20,27) -> (20,27)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 20.6 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.6 22.3 Net SOC.Core.pc_load (20,27) -> (30,35)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_9.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:50.32-50.39
Info: 0.0 22.3 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_9.CE
Info: 5.4 ns logic, 16.8 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[2]$tr_io.O
Info: 4.8 4.8 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (8,23)
Info: Sink SOC.GPIOS.Gpios[2].data_in_LUT4_B.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 5.0 Source SOC.GPIOS.Gpios[2].data_in_LUT4_B.F
Info: 0.9 5.9 Net SOC.GPIOS.Gpios[2].data_in_LUT4_B_Z[2] (8,23) -> (8,23)
Info: Sink SOC.Core.read_data_LUT4_Z_21.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.1 Source SOC.Core.read_data_LUT4_Z_21.F
Info: 1.5 7.6 Net SOC.read_data[2] (8,23) -> (17,20)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 7.6 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: 0.5 ns logic, 7.2 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info: 4.1 4.6 Net SOC.GPIOS.gpio_direction[2] (4,23) -> (72,23)
Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info: Defined in:
Info: Risco-5/src/peripheral/gpios.v:16.19-16.33
Info: 0.2 4.8 Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info: 1.2 6.1 Net gpios_$_TBUF__Y_3_E (72,23) -> (82,23)
Info: Sink gpios[2]$tr_io$invert_T.A
Info: 0.2 6.3 Source gpios[2]$tr_io$invert_T.F
Info: 1.0 7.2 Net gpios[2]$tr_io$invert_T$conn$Z (82,23) -> (90,23)
Info: Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 6.2 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 44.93 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.64 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.25 ns
Info: Slack histogram:
Info: legend: * represents 50 endpoint(s)
Info: + represents [1,50) endpoint(s)
Info: [ 17743, 18809) |+
Info: [ 18809, 19875) |*+
Info: [ 19875, 20941) |**+
Info: [ 20941, 22007) |********+
Info: [ 22007, 23073) |***+
Info: [ 23073, 24139) |*+
Info: [ 24139, 25205) |**+
Info: [ 25205, 26271) |*******************+
Info: [ 26271, 27337) |******+
Info: [ 27337, 28403) |***+
Info: [ 28403, 29469) |************************************************************
Info: [ 29469, 30535) |***********************+
Info: [ 30535, 31601) |*****************+
Info: [ 31601, 32667) |***+
Info: [ 32667, 33733) |**+
Info: [ 33733, 34799) |****+
Info: [ 34799, 35865) |******+
Info: [ 35865, 36931) |*************+
Info: [ 36931, 37997) |*****+
Info: [ 37997, 39063) |*******+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5427 ; free virtual = 25648
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5720 ; free virtual = 25959
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
[30%] Placement Phase 2 completed
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5714 ; free virtual = 25954
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5659 ; free virtual = 25899
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5659 ; free virtual = 25899
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5659 ; free virtual = 25898
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5659 ; free virtual = 25898
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5659 ; free virtual = 25898
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5659 ; free virtual = 25898
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 39|
|3 |LUT1 | 13|
|4 |LUT2 | 184|
|5 |LUT3 | 247|
|6 |LUT4 | 237|
|7 |LUT5 | 300|
|8 |LUT6 | 1598|
|9 |MUXF7 | 431|
|10 |MUXF8 | 2|
|11 |RAM256X1S | 64|
|12 |RAM32M | 2|
|13 |RAM32X1D | 4|
|14 |FDRE | 1955|
|15 |FDSE | 4|
|16 |LD | 4|
|17 |IBUF | 2|
|18 |IOBUF | 8|
|19 |OBUF | 9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5659 ; free virtual = 25898
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 63 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2280.867 ; gain = 506.496 ; free physical = 5659 ; free virtual = 25898
Synthesis Optimization Complete : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.867 ; gain = 656.281 ; free physical = 5659 ; free virtual = 25898
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2280.867 ; gain = 0.000 ; free physical = 5904 ; free virtual = 26143
INFO: [Netlist 29-17] Analyzing 554 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2344.863 ; gain = 0.000 ; free physical = 5903 ; free virtual = 26143
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 82 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 8 instances
LD => LDCE: 4 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 40e864fe
INFO: [Common 17-83] Releasing license: Synthesis
76 Infos, 114 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:54 ; elapsed = 00:00:51 . Memory (MB): peak = 2344.898 ; gain = 1067.258 ; free physical = 5903 ; free virtual = 26143
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1994.970; main = 1744.897; forked = 398.211
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3218.477; main = 2344.867; forked = 969.656
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2408.895 ; gain = 63.996 ; free physical = 5902 ; free virtual = 26141
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 145cd93ff
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2521.707 ; gain = 112.812 ; free physical = 5836 ; free virtual = 26076
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 145cd93ff
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2771.613 ; gain = 0.000 ; free physical = 5568 ; free virtual = 25808
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 145cd93ff
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2771.613 ; gain = 0.000 ; free physical = 5568 ; free virtual = 25808
Phase 1 Initialization | Checksum: 145cd93ff
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2771.613 ; gain = 0.000 ; free physical = 5568 ; free virtual = 25808
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 145cd93ff
Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2771.613 ; gain = 0.000 ; free physical = 5568 ; free virtual = 25808
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 145cd93ff
Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2771.613 ; gain = 0.000 ; free physical = 5568 ; free virtual = 25807
Phase 2 Timer Update And Timing Data Collection | Checksum: 145cd93ff
Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2771.613 ; gain = 0.000 ; free physical = 5568 ; free virtual = 25807
Phase 3 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 145cd93ff
Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2771.613 ; gain = 0.000 ; free physical = 5568 ; free virtual = 25807
Retarget | Checksum: 145cd93ff
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 145cd93ff
Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2771.613 ; gain = 0.000 ; free physical = 5568 ; free virtual = 25807
Constant propagation | Checksum: 145cd93ff
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 19c44a45a
Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2771.613 ; gain = 0.000 ; free physical = 5568 ; free virtual = 25807
Sweep | Checksum: 19c44a45a
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 1 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 19c44a45a
Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2803.629 ; gain = 32.016 ; free physical = 5567 ; free virtual = 25807
BUFG optimization | Checksum: 19c44a45a
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 19c44a45a
Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2803.629 ; gain = 32.016 ; free physical = 5567 ; free virtual = 25807
Shift Register Optimization | Checksum: 19c44a45a
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 160310455
Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2803.629 ; gain = 32.016 ; free physical = 5567 ; free virtual = 25807
Post Processing Netlist | Checksum: 160310455
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1bba6d312
Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2803.629 ; gain = 32.016 ; free physical = 5567 ; free virtual = 25807
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2803.629 ; gain = 0.000 ; free physical = 5567 ; free virtual = 25807
Phase 9.2 Verifying Netlist Connectivity | Checksum: 1bba6d312
Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2803.629 ; gain = 32.016 ; free physical = 5567 ; free virtual = 25807
Phase 9 Finalization | Checksum: 1bba6d312
Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2803.629 ; gain = 32.016 ; free physical = 5567 ; free virtual = 25807
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 8 | 1 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 1bba6d312
Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2803.629 ; gain = 32.016 ; free physical = 5567 ; free virtual = 25807
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.629 ; gain = 0.000 ; free physical = 5567 ; free virtual = 25807
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1bba6d312
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2803.629 ; gain = 0.000 ; free physical = 5566 ; free virtual = 25806
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1bba6d312
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.629 ; gain = 0.000 ; free physical = 5566 ; free virtual = 25806
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.629 ; gain = 0.000 ; free physical = 5566 ; free virtual = 25806
Ending Netlist Obfuscation Task | Checksum: 1bba6d312
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.629 ; gain = 0.000 ; free physical = 5565 ; free virtual = 25805
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2803.629 ; gain = 458.730 ; free physical = 5565 ; free virtual = 25805
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.645 ; gain = 0.000 ; free physical = 5564 ; free virtual = 25804
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d7457de2
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2835.645 ; gain = 0.000 ; free physical = 5564 ; free virtual = 25804
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.645 ; gain = 0.000 ; free physical = 5564 ; free virtual = 25804
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 156ce44a2
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.74 . Memory (MB): peak = 2835.645 ; gain = 0.000 ; free physical = 5564 ; free virtual = 25803
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1c22c5786
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5563 ; free virtual = 25803
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1c22c5786
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5563 ; free virtual = 25803
Phase 1 Placer Initialization | Checksum: 1c22c5786
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5563 ; free virtual = 25803
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1daa97ea8
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5558 ; free virtual = 25798
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2567a4237
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5558 ; free virtual = 25798
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 2567a4237
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5558 ; free virtual = 25798
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 23be78cfe
Time (s): cpu = 00:00:15 ; elapsed = 00:00:04 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5557 ; free virtual = 25796
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 70 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 29 nets or LUTs. Breaked 0 LUT, combined 29 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5557 ; free virtual = 25796
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 29 | 29 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 29 | 29 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 19512545c
Time (s): cpu = 00:00:15 ; elapsed = 00:00:04 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5557 ; free virtual = 25796
Phase 2.4 Global Placement Core | Checksum: 1684f68be
Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5554 ; free virtual = 25793
Phase 2 Global Placement | Checksum: 1684f68be
Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5553 ; free virtual = 25793
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 14b3e88ee
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5553 ; free virtual = 25793
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: f652d223
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5556 ; free virtual = 25796
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 132afeea8
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5549 ; free virtual = 25789
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1de33cbf3
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5556 ; free virtual = 25796
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 158ade15c
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5553 ; free virtual = 25793
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 14ad0ab3f
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5553 ; free virtual = 25793
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1b64cc674
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5553 ; free virtual = 25793
Phase 3 Detail Placement | Checksum: 1b64cc674
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5553 ; free virtual = 25793
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 18669c5fd
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.882 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 23848bef8
Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5544 ; free virtual = 25784
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 23848bef8
Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5544 ; free virtual = 25784
Phase 4.1.1.1 BUFG Insertion | Checksum: 18669c5fd
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5541 ; free virtual = 25781
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1885eedda
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5552 ; free virtual = 25791
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5552 ; free virtual = 25791
Phase 4.1 Post Commit Optimization | Checksum: 1885eedda
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5551 ; free virtual = 25791
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1885eedda
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5550 ; free virtual = 25790
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 2x2|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1885eedda
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5550 ; free virtual = 25790
Phase 4.3 Placer Reporting | Checksum: 1885eedda
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5548 ; free virtual = 25787
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5547 ; free virtual = 25787
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5547 ; free virtual = 25787
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 141e9853f
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5550 ; free virtual = 25790
Ending Placer Task | Checksum: 10d72012d
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.672 ; gain = 7.027 ; free physical = 5550 ; free virtual = 25790
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.672 ; gain = 39.043 ; free physical = 5550 ; free virtual = 25790
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5551 ; free virtual = 25791
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5551 ; free virtual = 25791
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
[50%] Placement Phase 3 completed
Running routing......
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: b9efcec4 ConstDB: 0 ShapeSum: 53823269 RouteDB: 0
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
Post Restoration Checksum: NetGraph: 55eb0b84 | NumContArr: 136d7d2a | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 1eeaa7de8
Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5477 ; free virtual = 25717
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 1eeaa7de8
Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5477 ; free virtual = 25717
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 1eeaa7de8
Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5477 ; free virtual = 25717
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 212fa44cf
Time (s): cpu = 00:00:37 ; elapsed = 00:00:28 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5439 ; free virtual = 25678
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 |
Router Utilization Summary
Global Vertical Routing Utilization = 0.000217609 %
Global Horizontal Routing Utilization = 0.0004973 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 3857
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 3853
Number of Partially Routed Nets = 4
Number of Node Overlaps = 4
Phase 2 Router Initialization | Checksum: 2a1560ef0
Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5430 ; free virtual = 25670
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2a1560ef0
Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5430 ; free virtual = 25670
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 277fb4cd6
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5442 ; free virtual = 25682
Phase 3 Initial Routing | Checksum: 277fb4cd6
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5442 ; free virtual = 25682
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 558
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.540 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1bc02bf7f
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5442 ; free virtual = 25682
Phase 4 Rip-up And Reroute | Checksum: 1bc02bf7f
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5442 ; free virtual = 25682
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1bc02bf7f
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5442 ; free virtual = 25682
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1bc02bf7f
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5442 ; free virtual = 25682
Phase 5 Delay and Skew Optimization | Checksum: 1bc02bf7f
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5442 ; free virtual = 25682
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1f7167047
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5442 ; free virtual = 25682
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 1f7167047
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5442 ; free virtual = 25682
Phase 6 Post Hold Fix | Checksum: 1f7167047
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5442 ; free virtual = 25682
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.78126 %
Global Horizontal Routing Utilization = 1.0054 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1f7167047
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5442 ; free virtual = 25682
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1f7167047
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5442 ; free virtual = 25682
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 20031d3c3
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5437 ; free virtual = 25677
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 20031d3c3
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5439 ; free virtual = 25679
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 1988ca62e
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5438 ; free virtual = 25678
Ending Routing Task | Checksum: 1988ca62e
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5438 ; free virtual = 25678
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 5436 ; free virtual = 25676
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (2258)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (7344)
5. checking no_input_delay (9)
6. checking no_output_delay (17)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (2258)
---------------------------
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[37]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[38]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[40]/Q (HIGH)
There are 2246 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (7344)
---------------------------------------------------
There are 7344 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (9)
------------------------------
There are 9 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (17)
--------------------------------
There are 17 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Tue Jun 11 02:07:13 2024
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[40]_1[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 3156.820 ; gain = 245.301 ; free physical = 5410 ; free virtual = 25663
INFO: [Common 17-206] Exiting Vivado at Tue Jun 11 02:07:24 2024...
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
[Pipeline] }
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Parse file DONE
Erase SRAM Load SRAM Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
Loading: [====== ] 11.16%[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Load SRAM: [====== ] 10.28%
Loading: [============ ] 22.31%
Load SRAM: [=========== ] 20.56%
Loading: [================= ] 33.47%
Loading: [======================= ] 44.62%
Load SRAM: [================ ] 30.83%
Load SRAM: [===================== ] 41.11%
Loading: [============================ ] 55.78%
Loading: [================================== ] 66.94%
Load SRAM: [========================== ] 51.39%
Loading: [======================================== ] 78.09%
Load SRAM: [=============================== ] 61.67%
Loading: [============================================= ] 89.25%
Load SRAM: [==================================== ] 71.94%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
Load SRAM: [========================================== ] 82.22%[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Load SRAM: [=============================================== ] 92.50%
Load SRAM: [==================================================] 100.00%
Done
DONE
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
[Pipeline] }
+ echo testando na tang nano
testando na tang nano
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
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