Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 5889/43848 13%
Info: logic LUTs: 3809/43848 8%
Info: carry LUTs: 232/43848 0%
Info: RAM LUTs: 1232/ 5481 22%
Info: RAMW LUTs: 616/10962 5%
Info: Total DFFs: 886/43848 2%
Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 397 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x8f8789cf
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 886/43848 2%
Info: TRELLIS_COMB: 5963/43848 13%
Info: TRELLIS_RAMW: 308/ 5481 5%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 3438 cells, random placement wirelen = 296598.
Info: at initial placer iter 0, wirelen = 2315
Info: at initial placer iter 1, wirelen = 1820
Info: at initial placer iter 2, wirelen = 1697
Info: at initial placer iter 3, wirelen = 1673
Info: Running main analytical placer, max placement attempts per cell = 6436872.
Info: at iteration #1, type ALL: wirelen solved = 1662, spread = 38362, legal = 38874; time = 0.24s
Info: at iteration #2, type ALL: wirelen solved = 3975, spread = 30505, legal = 31086; time = 0.24s
Info: at iteration #3, type ALL: wirelen solved = 6150, spread = 30199, legal = 30767; time = 0.24s
Info: at iteration #4, type ALL: wirelen solved = 8378, spread = 27651, legal = 28412; time = 0.25s
Info: at iteration #5, type ALL: wirelen solved = 10159, spread = 27091, legal = 27745; time = 0.25s
Info: at iteration #6, type ALL: wirelen solved = 11714, spread = 27873, legal = 28430; time = 0.23s
Info: at iteration #7, type ALL: wirelen solved = 13324, spread = 26744, legal = 27339; time = 0.20s
Info: at iteration #8, type ALL: wirelen solved = 14086, spread = 25716, legal = 26334; time = 0.22s
Info: at iteration #9, type ALL: wirelen solved = 14856, spread = 26231, legal = 26800; time = 0.15s
Info: at iteration #10, type ALL: wirelen solved = 15538, spread = 25271, legal = 26070; time = 0.15s
Info: at iteration #11, type ALL: wirelen solved = 15857, spread = 25244, legal = 25999; time = 0.15s
Info: at iteration #12, type ALL: wirelen solved = 16212, spread = 26125, legal = 26786; time = 0.15s
Info: at iteration #13, type ALL: wirelen solved = 16871, spread = 25788, legal = 26507; time = 0.15s
Info: at iteration #14, type ALL: wirelen solved = 17429, spread = 25305, legal = 26074; time = 0.15s
Info: at iteration #15, type ALL: wirelen solved = 17370, spread = 25677, legal = 26315; time = 0.15s
Info: at iteration #16, type ALL: wirelen solved = 18116, spread = 25710, legal = 26383; time = 0.15s
Info: HeAP Placer Time: 5.06s
Info: of which solving equations: 3.30s
Info: of which spreading cells: 0.36s
Info: of which strict legalisation: 0.11s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 4606, wirelen = 25999
Info: at iteration #5: temp = 0.000000, timing cost = 2902, wirelen = 23090
Info: at iteration #10: temp = 0.000000, timing cost = 2741, wirelen = 22229
Info: at iteration #15: temp = 0.000000, timing cost = 2518, wirelen = 21852
Info: at iteration #20: temp = 0.000000, timing cost = 2522, wirelen = 21719
Info: at iteration #23: temp = 0.000000, timing cost = 2401, wirelen = 21694
Info: SA placement time 16.47s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 32.74 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.99 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.52 ns
Info: Slack histogram:
Info: legend: * represents 53 endpoint(s)
Info: + represents [1,53) endpoint(s)
Info: [ 9460, 10949) |+
Info: [ 10949, 12438) |
Info: [ 12438, 13927) |+
Info: [ 13927, 15416) |+
Info: [ 15416, 16905) |**+
Info: [ 16905, 18394) |***+
Info: [ 18394, 19883) |******+
Info: [ 19883, 21372) |****+
Info: [ 21372, 22861) |*****+
Info: [ 22861, 24350) |*****************+
Info: [ 24350, 25839) |******+
Info: [ 25839, 27328) |************************************************************
Info: [ 27328, 28817) |**********************************+
Info: [ 28817, 30306) |****+
Info: [ 30306, 31795) |*+
Info: [ 31795, 33284) |**+
Info: [ 33284, 34773) |********+
Info: [ 34773, 36262) |************+
Info: [ 36262, 37751) |****+
Info: [ 37751, 39240) |*******+
Info: Checksum: 0xb787c032
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 28382 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 156 843 | 156 843 | 27580| 0.64 0.64|
Info: 2000 | 278 1721 | 122 878 | 26831| 0.26 0.91|
Info: 3000 | 417 2582 | 139 861 | 26071| 0.26 1.17|
Info: 4000 | 572 3427 | 155 845 | 25311| 0.25 1.42|
Info: 5000 | 713 4286 | 141 859 | 24564| 0.25 1.67|
Info: 6000 | 860 5139 | 147 853 | 23797| 0.26 1.93|
Info: 7000 | 1044 5955 | 184 816 | 23102| 0.29 2.22|
Info: 8000 | 1216 6783 | 172 828 | 22412| 0.25 2.48|
Info: 9000 | 1425 7574 | 209 791 | 21692| 0.28 2.76|
Info: 10000 | 1641 8358 | 216 784 | 20969| 0.26 3.02|
Info: 11000 | 1830 9169 | 189 811 | 20407| 0.29 3.31|
Info: 12000 | 2068 9931 | 238 762 | 19813| 0.29 3.60|
Info: 13000 | 2271 10728 | 203 797 | 19093| 0.28 3.88|
Info: 14000 | 2533 11466 | 262 738 | 18475| 0.29 4.17|
Info: 15000 | 2837 12162 | 304 696 | 17984| 0.32 4.49|
Info: 16000 | 3035 12964 | 198 802 | 17241| 0.30 4.79|
Info: 17000 | 3358 13641 | 323 677 | 16644| 0.32 5.11|
Info: 18000 | 3599 14400 | 241 759 | 15934| 0.31 5.42|
Info: 19000 | 3888 15111 | 289 711 | 15422| 0.41 5.82|
Info: 20000 | 4234 15765 | 346 654 | 14864| 0.34 6.17|
Info: 21000 | 4551 16448 | 317 683 | 14264| 0.32 6.48|
Info: 22000 | 4819 17180 | 268 732 | 13741| 0.32 6.80|
Info: 23000 | 5248 17751 | 429 571 | 13322| 0.33 7.13|
Info: 24000 | 5723 18276 | 475 525 | 12936| 0.30 7.44|
Info: 25000 | 6127 18872 | 404 596 | 12503| 0.29 7.72|
Info: 26000 | 6492 19507 | 365 635 | 11986| 0.32 8.04|
Info: 27000 | 6801 20190 | 309 683 | 11340| 0.31 8.35|
Info: 28000 | 7091 20809 | 290 619 | 10666| 0.28 8.63|
Info: 29000 | 7495 21296 | 404 487 | 10099| 0.27 8.90|
Info: 30000 | 7890 21841 | 395 545 | 9557| 0.28 9.18|
Info: 31000 | 8265 22415 | 375 574 | 9031| 0.30 9.48|
Info: 32000 | 8529 23009 | 264 594 | 8338| 0.24 9.71|
Info: 33000 | 8762 23696 | 233 687 | 7600| 0.21 9.92|
Info: 34000 | 9073 24362 | 311 666 | 6941| 0.24 10.16|
Info: 35000 | 9402 25025 | 329 663 | 6287| 0.26 10.42|
Info: 36000 | 9715 25708 | 313 683 | 5677| 0.32 10.74|
Info: 37000 | 9770 26649 | 55 941 | 4734| 0.13 10.86|
Info: 38000 | 9777 27638 | 7 989 | 3741| 0.06 10.93|
Info: 39000 | 9803 28600 | 26 962 | 2771| 0.08 11.01|
Info: 40000 | 9873 29524 | 70 924 | 1850| 0.22 11.23|
Info: 41000 | 10000 30343 | 127 819 | 998| 0.29 11.52|
Info: 42000 | 10037 31009 | 37 666 | 52| 0.21 11.74|
Info: 42051 | 10037 31028 | 0 19 | 0| 0.06 11.80|
Info: Routing complete.
Info: Router1 time 11.80s
Info: Checksum: 0x5e635f5b
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.temp_address_TRELLIS_FF_Q_31.Q
Info: 0.9 1.4 Net SOC.Core.temp_address[0] (18,33) -> (16,33)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/core/core.v:62.47-62.59
Info: 0.2 1.6 Source SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_Z.F
Info: 1.3 2.9 Net SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C[0] (16,33) -> (34,30)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A.A
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 3.3 Source SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A.OFX
Info: 0.0 3.3 Net SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A_Z_PFUMX_BLUT_Z (34,30) -> (34,30)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A_Z_PFUMX_BLUT_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.54-157.56
Info: 0.2 3.6 Source SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A_Z_PFUMX_BLUT_ALUT_LUT4_Z.OFX
Info: 0.0 3.6 Net SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_D0 (34,30) -> (34,30)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.66-157.68
Info: 0.2 3.8 Source SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.7 4.5 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_3_C_LUT4_Z_D_LUT4_D_B_LUT4_Z_D_LUT4_Z_C_L6MUX21_SD_Z_PFUMX_Z_ALUT_LUT4_Z_D[4] (34,30) -> (30,30)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_3_C_LUT4_Z_D_LUT4_D_B_LUT4_Z_D_LUT4_Z_C_L6MUX21_SD_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 4.8 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_3_C_LUT4_Z_D_LUT4_D_B_LUT4_Z_D_LUT4_Z_C_L6MUX21_SD_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 1.9 6.6 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_3_C_LUT4_Z_D_LUT4_D_B_LUT4_Z_D_LUT4_Z_C_L6MUX21_SD_Z[3] (30,30) -> (14,26)
Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 6.9 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.7 7.6 Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_BLUT_Z[6] (14,26) -> (14,25)
Info: Sink SOC.Core.RegisterBank.registers.0.3_DO_2_LUT4_A_Z_PFUMX_BLUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 7.8 Source SOC.Core.RegisterBank.registers.0.3_DO_2_LUT4_A_Z_PFUMX_BLUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.6 8.4 Net SOC.Core.RegisterBank.registers.0.3_DO_2_LUT4_A_Z_PFUMX_BLUT_Z[5] (14,25) -> (15,25)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 8.7 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 8.7 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1 (15,25) -> (15,25)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 8.9 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 10.2 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z[1] (15,25) -> (21,20)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_D_LUT4_A.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.5 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_D_LUT4_A.F
Info: 1.4 11.9 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_D_LUT4_A_Z[5] (21,20) -> (22,29)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_C0_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 12.2 Source SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_C0_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 13.4 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_D_LUT4_C_Z_LUT4_C_1_Z[5] (22,29) -> (17,26)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_PFUMX_Z_C0_LUT4_Z_D_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 13.7 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_PFUMX_Z_C0_LUT4_Z_D_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.0 14.7 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_PFUMX_Z_C0_LUT4_Z_D[6] (17,26) -> (23,25)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z_C_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 14.9 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z_C_LUT4_Z_1.F
Info: 0.4 15.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z_C[2] (23,25) -> (23,25)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 15.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z.F
Info: 1.3 16.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z[3] (23,25) -> (18,28)
Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_BLUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 17.2 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_BLUT_LUT4_Z.OFX
Info: 1.2 18.5 Net SOC.Core.alu_out[11] (18,28) -> (17,33)
Info: Sink SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_C_1_D_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: Risco-5/src/core/core.v:58.31-58.38
Info: 0.3 18.8 Source SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_C_1_D_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.2 20.0 Net SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_C_1_D_LUT4_C_Z[1] (17,33) -> (20,27)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 20.2 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 20.2 Net SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT (20,27) -> (20,27)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.30-141.32
Info: 0.2 20.4 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 20.4 Net SOC.Core.Pc.load_L6MUX21_Z_D1 (20,27) -> (20,27)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 20.6 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.6 22.3 Net SOC.Core.pc_load (20,27) -> (30,35)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_9.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:50.32-50.39
Info: 0.0 22.3 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_9.CE
Info: 5.4 ns logic, 16.8 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[2]$tr_io.O
Info: 4.8 4.8 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (8,23)
Info: Sink SOC.GPIOS.Gpios[2].data_in_LUT4_B.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 5.0 Source SOC.GPIOS.Gpios[2].data_in_LUT4_B.F
Info: 0.9 5.9 Net SOC.GPIOS.Gpios[2].data_in_LUT4_B_Z[2] (8,23) -> (8,23)
Info: Sink SOC.Core.read_data_LUT4_Z_21.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.1 Source SOC.Core.read_data_LUT4_Z_21.F
Info: 1.5 7.6 Net SOC.read_data[2] (8,23) -> (17,20)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 7.6 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: 0.5 ns logic, 7.2 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info: 4.1 4.6 Net SOC.GPIOS.gpio_direction[2] (4,23) -> (72,23)
Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info: Defined in:
Info: Risco-5/src/peripheral/gpios.v:16.19-16.33
Info: 0.2 4.8 Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info: 1.2 6.1 Net gpios_$_TBUF__Y_3_E (72,23) -> (82,23)
Info: Sink gpios[2]$tr_io$invert_T.A
Info: 0.2 6.3 Source gpios[2]$tr_io$invert_T.F
Info: 1.0 7.2 Net gpios[2]$tr_io$invert_T$conn$Z (82,23) -> (90,23)
Info: Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 6.2 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 44.93 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.64 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.25 ns
Info: Slack histogram:
Info: legend: * represents 50 endpoint(s)
Info: + represents [1,50) endpoint(s)
Info: [ 17743, 18809) |+
Info: [ 18809, 19875) |*+
Info: [ 19875, 20941) |**+
Info: [ 20941, 22007) |********+
Info: [ 22007, 23073) |***+
Info: [ 23073, 24139) |*+
Info: [ 24139, 25205) |**+
Info: [ 25205, 26271) |*******************+
Info: [ 26271, 27337) |******+
Info: [ 27337, 28403) |***+
Info: [ 28403, 29469) |************************************************************
Info: [ 29469, 30535) |***********************+
Info: [ 30535, 31601) |*****************+
Info: [ 31601, 32667) |***+
Info: [ 32667, 33733) |**+
Info: [ 33733, 34799) |****+
Info: [ 34799, 35865) |******+
Info: [ 35865, 36931) |*************+
Info: [ 36931, 37997) |*****+
Info: [ 37997, 39063) |*******+
Info: Program finished normally.
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