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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2129.301 ; gain = 505.559 ; free physical = 4247 ; free virtual = 26094
---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2129.301 ; gain = 505.559 ; free physical = 4247 ; free virtual = 26094
---------------------------------------------------------------------------------
Info: at iteration #11, type ALL: wirelen solved = 14778, spread = 23288, legal = 24053; time = 0.13s
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2129.301 ; gain = 0.000 ; free physical = 4247 ; free virtual = 26094
Info: at iteration #12, type ALL: wirelen solved = 14978, spread = 23256, legal = 24071; time = 0.13s
Info: at iteration #13, type ALL: wirelen solved = 15755, spread = 23981, legal = 24824; time = 0.13s
Info: at iteration #14, type ALL: wirelen solved = 16613, spread = 23989, legal = 24688; time = 0.13s
Info: at iteration #15, type ALL: wirelen solved = 16789, spread = 22898, legal = 24053; time = 0.15s
Info: at iteration #16, type ALL: wirelen solved = 16996, spread = 23251, legal = 24149; time = 0.19s
Info: HeAP Placer Time: 3.98s
Info: of which solving equations: 2.47s
Info: of which spreading cells: 0.32s
Info: of which strict legalisation: 0.09s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1275, wirelen = 24053
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2286.051 ; gain = 0.000 ; free physical = 4183 ; free virtual = 26029
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2286.086 ; gain = 0.000 ; free physical = 4183 ; free virtual = 26029
Info: at iteration #5: temp = 0.000000, timing cost = 1176, wirelen = 21258
Info: at iteration #10: temp = 0.000000, timing cost = 1058, wirelen = 20472
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4181 ; free virtual = 26028
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Start Loading Part and Timing Information
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Loading part: xc7a100tcsg324-1
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4181 ; free virtual = 26028
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Start Applying 'set_property' XDC Constraints
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---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4181 ; free virtual = 26028
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 00000000000000000000000000000000000000000000001 | 000000
VALIDATE_FETCH | 00000000000000000000000000000000000000000000010 | 101110
DECODE | 00000000000000000000000000000000000000000000100 | 000001
MEMADR | 00000000000000000000000000000000000000000001000 | 000010
MEMREAD_UNALIGNED | 00000000000000000000000000000000000000000010000 | 010110
LOAD_FIRST_BLOCK | 00000000000000000000000000000000000000000100000 | 010000
SAVE_FIRST_BLOCK | 00000000000000000000000000000000000000001000000 | 010001
CALC_NEXT_ADDRESS | 00000000000000000000000000000000000000010000000 | 010010
READ_SECOND_BLOCK | 00000000000000000000000000000000000000100000000 | 010011
LOAD_SECOND_BLOCK | 00000000000000000000000000000000000001000000000 | 010100
MERGE_BLOCKS | 00000000000000000000000000000000000010000000000 | 010101
FILTER_ALU_WB | 00000000000000000000000000000000000100000000000 | 010111
MEMREAD | 00000000000000000000000000000000001000000000000 | 000011
MEMWB | 00000000000000000000000000000000010000000000000 | 000100
MEMWRITE_UNALIGNED | 00000000000000000000000000000000100000000000000 | 011000
GEN_FIRST_BLOCK_PART_1 | 00000000000000000000000000000001000000000000000 | 011001
GEN_FIRST_BLOCK_PART_2 | 00000000000000000000000000000010000000000000000 | 011010
GEN_SECOND_BLOCK_PART_1 | 00000000000000000000000000000100000000000000000 | 011011
GEN_SECOND_BLOCK_PART_2 | 00000000000000000000000000001000000000000000000 | 011100
MERGE_WRITE_BLOCKS | 00000000000000000000000000010000000000000000000 | 011101
SWAP_VALUE_DIRECTION | 00000000000000000000000000100000000000000000000 | 011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 00000000000000000000000001000000000000000000000 | 100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 00000000000000000000000010000000000000000000000 | 100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 00000000000000000000000100000000000000000000000 | 100100
CLEAR_VALUE | 00000000000000000000001000000000000000000000000 | 011111
MERGE_WRITE_VALUE_1 | 00000000000000000000010000000000000000000000000 | 100000
WRITE_VALUE_1 | 00000000000000000000100000000000000000000000000 | 100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 00000000000000000001000000000000000000000000000 | 100101
READ_SECOND_BLOCK_TO_WRITE | 00000000000000000010000000000000000000000000000 | 100110
LOAD_SECOND_BLOCK_TO_WRITE | 00000000000000000100000000000000000000000000000 | 100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 00000000000000001000000000000000000000000000000 | 101000
SWAP_VALUE_DIRECTION_2 | 00000000000000010000000000000000000000000000000 | 101001
CLEAR_VALUE_PART_2 | 00000000000000100000000000000000000000000000000 | 101010
CLEAR_VALUE_PART_2_1 | 00000000000001000000000000000000000000000000000 | 101011
MERGE_WRITE_VALUE_2 | 00000000000010000000000000000000000000000000000 | 101100
WRITE_VALUE_2 | 00000000000100000000000000000000000000000000000 | 101101
MEMWRITE | 00000000001000000000000000000000000000000000000 | 000101
EXECUTER | 00000000010000000000000000000000000000000000000 | 000110
EXECUTEI | 00000000100000000000000000000000000000000000000 | 001000
JAL | 00000001000000000000000000000000000000000000000 | 001001
BRANCH | 00000010000000000000000000000000000000000000000 | 001010
AUIPC | 00000100000000000000000000000000000000000000000 | 001100
LUI | 00001000000000000000000000000000000000000000000 | 001101
JALR_PC | 00010000000000000000000000000000000000000000000 | 001110
JALR | 00100000000000000000000000000000000000000000000 | 001011
ALUWB | 01000000000000000000000000000000000000000000000 | 000111
EXECUTECSR | 10000000000000000000000000000000000000000000000 | 001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
Info: at iteration #15: temp = 0.000000, timing cost = 972, wirelen = 20139
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 0000 | 0000
COPY_WRITE_BUFFER | 0001 | 0100
WRITE | 0010 | 0010
READ | 0011 | 0001
READ_RX_FIFO_EMPTY | 0100 | 0110
READ_TX_FIFO_EMPTY | 0101 | 0111
READ_RX_FIFO_FULL | 0110 | 1000
READ_TX_FIFO_FULL | 0111 | 1001
WB | 1000 | 0101
FINISH | 1001 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4171 ; free virtual = 26019
---------------------------------------------------------------------------------
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Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 2
3 Input 32 Bit Adders := 1
2 Input 10 Bit Adders := 2
2 Input 6 Bit Adders := 6
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 2
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
+---XORs :
2 Bit Wide XORs := 1
+---Registers :
64 Bit Registers := 2
32 Bit Registers := 52
16 Bit Registers := 4
10 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 5
4 Bit Registers := 2
3 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 15
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
128 Bit (16 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 1
47 Input 47 Bit Muxes := 1
2 Input 47 Bit Muxes := 17
11 Input 47 Bit Muxes := 1
2 Input 32 Bit Muxes := 8
8 Input 32 Bit Muxes := 1
15 Input 32 Bit Muxes := 1
6 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 1
10 Input 32 Bit Muxes := 2
2 Input 8 Bit Muxes := 3
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
47 Input 4 Bit Muxes := 1
9 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 2
23 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
6 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
4 Input 3 Bit Muxes := 2
47 Input 3 Bit Muxes := 3
10 Input 3 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 16
47 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 4
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 77
47 Input 1 Bit Muxes := 12
4 Input 1 Bit Muxes := 3
6 Input 1 Bit Muxes := 12
10 Input 1 Bit Muxes := 8
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
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Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
DSP Report: Generating DSP MDU_out_S0, operation Mode is: A*B.
DSP Report: operator MDU_out_S0 is absorbed into DSP MDU_out_S0.
DSP Report: operator MDU_out_S0 is absorbed into DSP MDU_out_S0.
DSP Report: Generating DSP MDU_out_S0, operation Mode is: A*B.
DSP Report: operator MDU_out_S0 is absorbed into DSP MDU_out_S0.
DSP Report: operator MDU_out_S0 is absorbed into DSP MDU_out_S0.
DSP Report: Generating DSP MDU_out_S0, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator MDU_out_S0 is absorbed into DSP MDU_out_S0.
DSP Report: operator MDU_out_S0 is absorbed into DSP MDU_out_S0.
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
Info: at iteration #20: temp = 0.000000, timing cost = 991, wirelen = 20026
Info: at iteration #25: temp = 0.000000, timing cost = 999, wirelen = 19989
Info: at iteration #27: temp = 0.000000, timing cost = 964, wirelen = 19983
Info: SA placement time 15.67s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 30.98 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.95 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.52 ns
Info: Slack histogram:
Info: legend: * represents 41 endpoint(s)
Info: + represents [1,41) endpoint(s)
Info: [ 7723, 9299) |+
Info: [ 9299, 10875) |+
Info: [ 10875, 12451) |
Info: [ 12451, 14027) |+
Info: [ 14027, 15603) |+
Info: [ 15603, 17179) |*+
Info: [ 17179, 18755) |*+
Info: [ 18755, 20331) |*********+
Info: [ 20331, 21907) |*******+
Info: [ 21907, 23483) |*******+
Info: [ 23483, 25059) |****************+
Info: [ 25059, 26635) |***********+
Info: [ 26635, 28211) |*******************************************+
Info: [ 28211, 29787) |************************************************************
Info: [ 29787, 31363) |*****************+
Info: [ 31363, 32939) |****************+
Info: [ 32939, 34515) |*****+
Info: [ 34515, 36091) |********************
Info: [ 36091, 37667) |**************+
Info: [ 37667, 39243) |**********+
Info: Checksum: 0x125daf43
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 25408 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 98 901 | 98 901 | 24561| 0.57 0.57|
Info: 2000 | 215 1784 | 117 883 | 23697| 0.25 0.82|
Info: 3000 | 299 2700 | 84 916 | 22844| 0.23 1.05|
Info: 4000 | 392 3607 | 93 907 | 21953| 0.24 1.30|
Info: 5000 | 499 4500 | 107 893 | 21267| 0.22 1.52|
Info: 6000 | 658 5341 | 159 841 | 20487| 0.25 1.77|
Info: 7000 | 857 6142 | 199 801 | 19735| 0.25 2.02|
Info: 8000 | 1059 6940 | 202 798 | 18993| 0.27 2.29|
Info: 9000 | 1246 7753 | 187 813 | 18308| 0.28 2.58|
Info: 10000 | 1474 8525 | 228 772 | 17676| 0.30 2.87|
Info: 11000 | 1732 9267 | 258 742 | 17041| 0.31 3.18|
Info: 12000 | 1995 10004 | 263 737 | 16405| 0.32 3.50|
Info: 13000 | 2256 10743 | 261 739 | 15744| 0.30 3.80|
Info: 14000 | 2552 11447 | 296 704 | 15112| 0.31 4.12|
Info: 15000 | 2896 12103 | 344 656 | 14567| 0.31 4.43|
Info: 16000 | 3228 12771 | 332 668 | 14016| 0.30 4.73|
Info: 17000 | 3537 13462 | 309 691 | 13426| 0.31 5.04|
Info: 18000 | 3866 14133 | 329 671 | 12910| 0.36 5.39|
Info: 19000 | 4264 14732 | 398 599 | 12409| 0.34 5.74|
Info: 20000 | 4789 15204 | 525 472 | 12033| 0.33 6.07|
Info: 21000 | 5216 15765 | 427 561 | 11593| 0.33 6.40|
Info: 22000 | 5689 16277 | 473 512 | 11180| 0.32 6.72|
Info: 23000 | 6095 16834 | 406 557 | 10640| 0.31 7.03|
Info: 24000 | 6455 17435 | 360 601 | 10060| 0.30 7.34|
Info: 25000 | 6776 18068 | 321 633 | 9529| 0.30 7.63|
Info: 26000 | 7152 18683 | 376 615 | 9003| 0.31 7.95|
Info: 27000 | 7382 19430 | 230 747 | 8325| 0.29 8.24|
Info: 28000 | 7666 20133 | 284 703 | 7695| 0.31 8.55|
Info: 29000 | 7988 20803 | 322 670 | 7051| 0.31 8.86|
Info: 30000 | 8218 21569 | 230 766 | 6363| 0.37 9.23|
Info: 31000 | 8263 22524 | 45 955 | 5440| 0.14 9.37|
Info: 32000 | 8289 23498 | 26 974 | 4468| 0.09 9.46|
Info: 33000 | 8358 24427 | 69 929 | 3568| 0.19 9.66|
Info: 34000 | 8420 25349 | 62 922 | 2644| 0.17 9.82|
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4147 ; free virtual = 26003
---------------------------------------------------------------------------------
Sort Area is MDU_out_S0_0 : 0 0 : 2701 4456 : Used 1 time 0
Sort Area is MDU_out_S0_0 : 0 1 : 1755 4456 : Used 1 time 0
Sort Area is MDU_out_S0_3 : 0 0 : 1755 1755 : Used 1 time 0
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|MDU | A*B | 15 | 15 | - | - | 15 | 0 | 0 | - | - | - | 0 | 0 |
|MDU | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|MDU | (PCIN>>17)+A*B | 15 | 15 | - | - | 15 | 0 | 0 | - | - | - | 0 | 0 |
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Info: 35000 | 8566 26163 | 146 814 | 1821| 0.31 10.13|
Info: 36000 | 8669 26949 | 103 786 | 942| 0.25 10.38|
Info: 37000 | 8791 27759 | 122 810 | 115| 0.30 10.68|
Info: 37120 | 8794 27847 | 3 88 | 0| 0.06 10.74|
Info: Routing complete.
Info: Router1 time 10.74s
Info: Checksum: 0xcde9e3a9
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info: 0.9 1.4 Net SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_C_LUT4_Z_B[1] (20,18) -> (19,18)
Info: Sink SOC.Uart.response_LUT4_B_Z_LUT4_Z_2_D_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 1.6 Source SOC.Uart.response_LUT4_B_Z_LUT4_Z_2_D_LUT4_Z_1.F
Info: 0.7 2.3 Net SOC.Uart.response_LUT4_B_Z_LUT4_Z_2_D[1] (19,18) -> (19,18)
Info: Sink SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_Z_D_LUT4_D_1_Z_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.5 Source SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_Z_D_LUT4_D_1_Z_LUT4_Z_1.F
Info: 0.2 2.8 Net SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_Z_D_LUT4_D_1_Z[2] (19,18) -> (19,18)
Info: Sink SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_Z_D_LUT4_D_1_Z_LUT4_D.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.0 Source SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_Z_D_LUT4_D_1_Z_LUT4_D.F
Info: 0.5 3.5 Net SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_Z_D_LUT4_D_1_Z_LUT4_D_Z[1] (19,18) -> (19,18)
Info: Sink SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.7 Source SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_D_Z_LUT4_Z.F
Info: 0.5 4.2 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_4_C_LUT4_Z_A[3] (19,18) -> (19,17)
Info: Sink SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_1_D_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.4 Source SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_1_D_LUT4_Z_1.F
Info: 0.9 5.3 Net SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_1_D[1] (19,17) -> (19,16)
Info: Sink SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.6 Source SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_2.F
Info: 1.1 6.7 Net SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z[3] (19,16) -> (15,16)
Info: Sink SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_1_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_B_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.9 Source SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_1_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_B_Z_LUT4_Z.F
Info: 0.3 7.2 Net SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_1_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_B_Z[1] (15,16) -> (15,18)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_LUT4_A_Z_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 7.4 Source SOC.Core.RegisterBank.registers.0.0_DO_LUT4_A_Z_LUT4_Z_C_LUT4_Z.F
Info: 0.0 7.5 Net SOC.Core.RegisterBank.registers.0.0_DO_LUT4_A_Z_LUT4_Z_C[1] (15,18) -> (15,18)
Info: Sink SOC.Core.RegisterBank.registers.0.4_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 7.7 Source SOC.Core.RegisterBank.registers.0.4_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2.F
Info: 1.0 8.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_8_C_CCU2C_S0_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_Z_A[2] (15,18) -> (17,14)
Info: Sink SOC.Core.RegisterBank.registers.0.4_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_C.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 9.0 Source SOC.Core.RegisterBank.registers.0.4_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_C.F
Info: 0.5 9.5 Net SOC.Core.RegisterBank.registers.0.6_DO_LUT4_A_Z_LUT4_Z_1_D[3] (17,14) -> (17,14)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_3_LUT4_A_Z_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 9.7 Source SOC.Core.RegisterBank.registers.0.7_DO_3_LUT4_A_Z_LUT4_Z_1.F
Info: 0.7 10.4 Net SOC.Core.RegisterBank.registers.0.7_DO_3_LUT4_A_Z[3] (17,14) -> (17,13)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_16_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_C_Z_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.7 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_16_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_C_Z_LUT4_Z_2.F
Info: 0.6 11.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_16_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_C_Z[3] (17,13) -> (17,13)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_LUT4_A_Z_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 11.5 Source SOC.Core.RegisterBank.registers.0.1_DO_LUT4_A_Z_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1.F
Info: 0.7 12.2 Net SOC.Core.RegisterBank.registers.0.1_DO_LUT4_A_Z_LUT4_B_Z_LUT4_D_Z[3] (17,13) -> (15,13)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_LUT4_A_Z_LUT4_Z_B_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 12.4 Source SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_LUT4_A_Z_LUT4_Z_B_LUT4_Z_1.F
Info: 1.6 14.0 Net SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_LUT4_A_Z_LUT4_Z_B[2] (15,13) -> (10,18)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_LUT4_A_Z_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 14.3 Source SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_LUT4_A_Z_LUT4_Z.F
Info: 1.0 15.2 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_15_C_CCU2C_S1_COUT_CCU2C_CIN_B1[3] (10,18) -> (10,21)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z_C_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 15.5 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z_C_LUT4_Z_1.F
Info: 0.9 16.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z_C[2] (10,21) -> (10,23)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 16.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z.F
Info: 0.4 17.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D[2] (10,23) -> (10,23)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_C.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 17.2 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_C.F
Info: 0.8 18.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_C_Z[4] (10,23) -> (8,24)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_Z_C_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 18.2 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_Z_C_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.7 19.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_Z_C[3] (8,24) -> (9,21)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 19.2 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_Z.F
Info: 0.6 19.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1_C[3] (9,21) -> (9,21)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 20.1 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1.F
Info: 0.8 20.9 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0[3] (9,21) -> (5,20)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 21.1 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_C_LUT4_Z.F
Info: 0.4 21.5 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_C[2] (5,20) -> (5,20)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 21.8 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3.F
Info: 0.7 22.4 Net SOC.Core.alu_out[4] (5,20) -> (5,20)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/core/core.v:60.31-60.38
Info: 0.2 22.7 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: 0.9 23.6 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D[3] (5,20) -> (6,19)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 23.8 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: 0.8 24.6 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D[3] (6,19) -> (9,19)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 24.9 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: 0.8 25.7 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D[3] (9,19) -> (11,17)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 25.9 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: 0.2 26.1 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D[3] (11,17) -> (11,17)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 26.3 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z.F
Info: 0.9 27.3 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D[3] (11,17) -> (13,16)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 27.5 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z.F
Info: 0.2 27.7 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D[3] (13,16) -> (13,16)
Info: Sink SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 28.0 Source SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: 0.6 28.6 Net SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_D[3] (13,16) -> (13,16)
Info: Sink SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 28.8 Source SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z.F
Info: 0.7 29.5 Net SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z_D[3] (13,16) -> (15,14)
Info: Sink SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 29.8 Source SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z.F
Info: 0.4 30.2 Net SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D[3] (15,14) -> (15,14)
Info: Sink SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 30.4 Source SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1.F
Info: 0.4 30.8 Net SOC.Core.Pc.load_LUT4_Z_B[3] (15,14) -> (15,14)
Info: Sink SOC.Core.Pc.load_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 31.1 Source SOC.Core.Pc.load_LUT4_Z.F
Info: 1.6 32.7 Net SOC.Core.pc_load (15,14) -> (5,21)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_27.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:52.32-52.39
Info: 0.0 32.7 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_27.CE
Info: 8.6 ns logic, 24.2 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[2]$tr_io.O
Info: 4.6 4.6 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (15,25)
Info: Sink SOC.GPIOS.Gpios[2].data_in_LUT4_C.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 4.8 Source SOC.GPIOS.Gpios[2].data_in_LUT4_C.F
Info: 0.4 5.2 Net SOC.GPIOS.Gpios[2].data_in_LUT4_C_Z[2] (15,25) -> (15,25)
Info: Sink SOC.Core.read_data_LUT4_Z_2.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.5 Source SOC.Core.read_data_LUT4_Z_2.F
Info: 1.0 6.5 Net SOC.read_data[2] (15,25) -> (16,21)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 6.5 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: 0.5 ns logic, 6.0 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info: 4.6 5.1 Net SOC.GPIOS.gpio_direction[2] (9,25) -> (86,24)
Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info: Defined in:
Info: Risco-5/src/peripheral/gpios.v:16.19-16.33
Info: 0.2 5.3 Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info: 0.4 5.8 Net gpios_$_TBUF__Y_3_E (86,24) -> (86,24)
Info: Sink gpios[2]$tr_io$invert_T.A
Info: 0.2 6.0 Source gpios[2]$tr_io$invert_T.F
Info: 1.1 7.1 Net gpios[2]$tr_io$invert_T$conn$Z (86,24) -> (90,23)
Info: Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 6.1 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 30.56 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.46 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.13 ns
Info: Slack histogram:
Info: legend: * represents 43 endpoint(s)
Info: + represents [1,43) endpoint(s)
Info: [ 7278, 8867) |+
Info: [ 8867, 10456) |
Info: [ 10456, 12045) |
Info: [ 12045, 13634) |
Info: [ 13634, 15223) |
Info: [ 15223, 16812) |+
Info: [ 16812, 18401) |*+
Info: [ 18401, 19990) |*+
Info: [ 19990, 21579) |*******+
Info: [ 21579, 23168) |*********+
Info: [ 23168, 24757) |***+
Info: [ 24757, 26346) |***********************+
Info: [ 26346, 27935) |********+
Info: [ 27935, 29524) |************************************************************
Info: [ 29524, 31113) |************************************+
Info: [ 31113, 32702) |************************+
Info: [ 32702, 34291) |***********+
Info: [ 34291, 35880) |*******+
Info: [ 35880, 37469) |**********************+
Info: [ 37469, 39058) |*************+
Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4385 ; free virtual = 26257
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4378 ; free virtual = 26250
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4344 ; free virtual = 26217
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4329 ; free virtual = 26204
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4329 ; free virtual = 26204
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4328 ; free virtual = 26203
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4328 ; free virtual = 26203
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4328 ; free virtual = 26203
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4328 ; free virtual = 26203
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
DSP Final Report (the ' indicates corresponding REG is set)
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|MDU | A'*B' | 15 | 18 | - | - | 15 | 1 | 1 | - | - | - | 0 | 0 |
|MDU | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|MDU | PCIN>>17+A'*B' | 30 | 15 | - | - | 15 | 1 | 1 | - | - | - | 0 | 0 |
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 651|
|3 |DSP48E1 | 3|
|4 |LUT1 | 138|
|5 |LUT2 | 306|
|6 |LUT3 | 2240|
|7 |LUT4 | 305|
|8 |LUT5 | 368|
|9 |LUT6 | 1651|
|10 |MUXF7 | 461|
|11 |MUXF8 | 2|
|12 |RAM256X1S | 64|
|13 |RAM32M | 2|
|14 |RAM32X1D | 4|
|15 |FDRE | 2120|
|16 |FDSE | 4|
|17 |LD | 4|
|18 |IBUF | 3|
|19 |IOBUF | 8|
|20 |OBUF | 9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4328 ; free virtual = 26203
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 64 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2286.086 ; gain = 505.559 ; free physical = 4307 ; free virtual = 26183
Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 2286.086 ; gain = 662.344 ; free physical = 4307 ; free virtual = 26183
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2286.086 ; gain = 0.000 ; free physical = 4549 ; free virtual = 26425
INFO: [Netlist 29-17] Analyzing 1199 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2358.082 ; gain = 0.000 ; free physical = 4549 ; free virtual = 26425
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 82 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 8 instances
LD => LDCE: 4 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 53f9636a
INFO: [Common 17-83] Releasing license: Synthesis
82 Infos, 112 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:01 ; elapsed = 00:00:58 . Memory (MB): peak = 2358.117 ; gain = 1083.383 ; free physical = 4549 ; free virtual = 26424
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2070.481; main = 1791.026; forked = 422.148
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3231.691; main = 2358.086; forked = 969.652
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.74 . Memory (MB): peak = 2422.113 ; gain = 63.996 ; free physical = 4545 ; free virtual = 26420
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 14f13d544
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2480.934 ; gain = 58.820 ; free physical = 4520 ; free virtual = 26395
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":250)
WARN (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":176)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 14f13d544
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2728.871 ; gain = 0.000 ; free physical = 4174 ; free virtual = 26050
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 14f13d544
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2728.871 ; gain = 0.000 ; free physical = 4174 ; free virtual = 26050
Phase 1 Initialization | Checksum: 14f13d544
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2728.871 ; gain = 0.000 ; free physical = 4174 ; free virtual = 26050
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 14f13d544
Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2728.871 ; gain = 0.000 ; free physical = 4173 ; free virtual = 26049
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 14f13d544
Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2728.871 ; gain = 0.000 ; free physical = 4173 ; free virtual = 26049
Phase 2 Timer Update And Timing Data Collection | Checksum: 14f13d544
Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2728.871 ; gain = 0.000 ; free physical = 4173 ; free virtual = 26049
Phase 3 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 14f13d544
Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2728.871 ; gain = 0.000 ; free physical = 4173 ; free virtual = 26049
Retarget | Checksum: 14f13d544
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 1271b301c
Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2728.871 ; gain = 0.000 ; free physical = 4173 ; free virtual = 26049
Constant propagation | Checksum: 1271b301c
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
[20%] Placement Phase 1 completed
Phase 5 Sweep | Checksum: 1138f6139
Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2728.871 ; gain = 0.000 ; free physical = 4173 ; free virtual = 26049
Sweep | Checksum: 1138f6139
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 1138f6139
Time (s): cpu = 00:00:00.85 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2760.887 ; gain = 32.016 ; free physical = 4173 ; free virtual = 26048
BUFG optimization | Checksum: 1138f6139
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 1138f6139
Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2760.887 ; gain = 32.016 ; free physical = 4173 ; free virtual = 26048
Shift Register Optimization | Checksum: 1138f6139
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1a4056baa
Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2760.887 ; gain = 32.016 ; free physical = 4173 ; free virtual = 26049
Post Processing Netlist | Checksum: 1a4056baa
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 195c5a17a
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.8 . Memory (MB): peak = 2760.887 ; gain = 32.016 ; free physical = 4168 ; free virtual = 26044
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2760.887 ; gain = 0.000 ; free physical = 4168 ; free virtual = 26044
Phase 9.2 Verifying Netlist Connectivity | Checksum: 195c5a17a
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2760.887 ; gain = 32.016 ; free physical = 4168 ; free virtual = 26044
Phase 9 Finalization | Checksum: 195c5a17a
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2760.887 ; gain = 32.016 ; free physical = 4168 ; free virtual = 26044
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 8 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 195c5a17a
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2760.887 ; gain = 32.016 ; free physical = 4168 ; free virtual = 26044
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2760.887 ; gain = 0.000 ; free physical = 4168 ; free virtual = 26044
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 195c5a17a
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2760.887 ; gain = 0.000 ; free physical = 4170 ; free virtual = 26046
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 195c5a17a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2760.887 ; gain = 0.000 ; free physical = 4170 ; free virtual = 26046
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2760.887 ; gain = 0.000 ; free physical = 4170 ; free virtual = 26046
Ending Netlist Obfuscation Task | Checksum: 195c5a17a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2760.887 ; gain = 0.000 ; free physical = 4170 ; free virtual = 26046
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2760.887 ; gain = 402.770 ; free physical = 4170 ; free virtual = 26046
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2792.902 ; gain = 0.000 ; free physical = 4171 ; free virtual = 26047
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 10f507fb6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2792.902 ; gain = 0.000 ; free physical = 4171 ; free virtual = 26047
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2792.902 ; gain = 0.000 ; free physical = 4171 ; free virtual = 26047
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f1d9d435
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.92 . Memory (MB): peak = 2792.902 ; gain = 0.000 ; free physical = 4171 ; free virtual = 26047
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1ddb05168
Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4160 ; free virtual = 26036
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1ddb05168
Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4159 ; free virtual = 26034
Phase 1 Placer Initialization | Checksum: 1ddb05168
Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4160 ; free virtual = 26036
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 13822326c
Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4161 ; free virtual = 26037
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 19061d073
Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4161 ; free virtual = 26037
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 19061d073
Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4161 ; free virtual = 26037
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 14befd1f2
Time (s): cpu = 00:00:23 ; elapsed = 00:00:06 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4159 ; free virtual = 26034
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 83 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 35 nets or LUTs. Breaked 0 LUT, combined 35 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4159 ; free virtual = 26034
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 35 | 35 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 35 | 35 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 161a56fa5
Time (s): cpu = 00:00:23 ; elapsed = 00:00:07 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4159 ; free virtual = 26034
Phase 2.4 Global Placement Core | Checksum: 151607f35
Time (s): cpu = 00:00:29 ; elapsed = 00:00:08 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4159 ; free virtual = 26034
Phase 2 Global Placement | Checksum: 151607f35
Time (s): cpu = 00:00:29 ; elapsed = 00:00:08 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4159 ; free virtual = 26034
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1ced11cb3
Time (s): cpu = 00:00:29 ; elapsed = 00:00:08 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4159 ; free virtual = 26034
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1432ccfab
Time (s): cpu = 00:00:29 ; elapsed = 00:00:08 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4154 ; free virtual = 26030
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1e374bb87
Time (s): cpu = 00:00:29 ; elapsed = 00:00:08 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4155 ; free virtual = 26031
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1b412e39c
Time (s): cpu = 00:00:29 ; elapsed = 00:00:08 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4157 ; free virtual = 26033
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 9bc79a9e
Time (s): cpu = 00:00:31 ; elapsed = 00:00:10 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4159 ; free virtual = 26035
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 18667abf3
Time (s): cpu = 00:00:31 ; elapsed = 00:00:10 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4159 ; free virtual = 26035
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 194c9540c
Time (s): cpu = 00:00:32 ; elapsed = 00:00:10 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4159 ; free virtual = 26035
Phase 3 Detail Placement | Checksum: 194c9540c
Time (s): cpu = 00:00:32 ; elapsed = 00:00:10 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4159 ; free virtual = 26035
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 21f39e694
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=9.013 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1cf82784e
Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4151 ; free virtual = 26026
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1cf82784e
Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4151 ; free virtual = 26026
Phase 4.1.1.1 BUFG Insertion | Checksum: 21f39e694
Time (s): cpu = 00:00:37 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4151 ; free virtual = 26026
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=9.013. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 219e69eb7
Time (s): cpu = 00:00:37 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4151 ; free virtual = 26026
Time (s): cpu = 00:00:37 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4151 ; free virtual = 26026
Phase 4.1 Post Commit Optimization | Checksum: 219e69eb7
Time (s): cpu = 00:00:37 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4151 ; free virtual = 26026
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 219e69eb7
Time (s): cpu = 00:00:37 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4151 ; free virtual = 26026
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 1x1|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 219e69eb7
Time (s): cpu = 00:00:37 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4151 ; free virtual = 26026
Phase 4.3 Placer Reporting | Checksum: 219e69eb7
Time (s): cpu = 00:00:37 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4151 ; free virtual = 26026
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4151 ; free virtual = 26026
Time (s): cpu = 00:00:37 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4151 ; free virtual = 26026
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 27b03cbff
Time (s): cpu = 00:00:37 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4151 ; free virtual = 26026
Ending Placer Task | Checksum: 1aa2a83d2
Time (s): cpu = 00:00:37 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.930 ; gain = 7.027 ; free physical = 4151 ; free virtual = 26026
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:39 ; elapsed = 00:00:13 . Memory (MB): peak = 2799.930 ; gain = 39.043 ; free physical = 4151 ; free virtual = 26026
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4149 ; free virtual = 26025
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4148 ; free virtual = 26024
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: f3c671c8 ConstDB: 0 ShapeSum: b664120a RouteDB: 0
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
Post Restoration Checksum: NetGraph: bb86d97f | NumContArr: 4eec5d6a | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 28fc52c23
Time (s): cpu = 00:00:35 ; elapsed = 00:00:27 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4085 ; free virtual = 25961
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 28fc52c23
Time (s): cpu = 00:00:35 ; elapsed = 00:00:27 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4085 ; free virtual = 25961
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 28fc52c23
Time (s): cpu = 00:00:35 ; elapsed = 00:00:27 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4085 ; free virtual = 25961
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 22ce1f81b
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4085 ; free virtual = 25961
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.928 | TNS=0.000 | WHS=-0.052 | THS=-0.052 |
Router Utilization Summary
Global Vertical Routing Utilization = 0.000348174 %
Global Horizontal Routing Utilization = 0.000284172 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 6889
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 6885
Number of Partially Routed Nets = 4
Number of Node Overlaps = 2
Phase 2 Router Initialization | Checksum: 2968c0a6b
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4082 ; free virtual = 25958
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2968c0a6b
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4082 ; free virtual = 25958
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 2a91d95a4
Time (s): cpu = 00:00:47 ; elapsed = 00:00:30 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4082 ; free virtual = 25958
Phase 3 Initial Routing | Checksum: 2a91d95a4
Time (s): cpu = 00:00:47 ; elapsed = 00:00:30 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4082 ; free virtual = 25958
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 559
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.614 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1e3d9a12d
Time (s): cpu = 00:00:51 ; elapsed = 00:00:32 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4079 ; free virtual = 25955
Phase 4 Rip-up And Reroute | Checksum: 1e3d9a12d
Time (s): cpu = 00:00:51 ; elapsed = 00:00:32 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4079 ; free virtual = 25955
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1e3d9a12d
Time (s): cpu = 00:00:51 ; elapsed = 00:00:32 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4069 ; free virtual = 25945
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1e3d9a12d
Time (s): cpu = 00:00:51 ; elapsed = 00:00:32 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4064 ; free virtual = 25940
Phase 5 Delay and Skew Optimization | Checksum: 1e3d9a12d
Time (s): cpu = 00:00:51 ; elapsed = 00:00:32 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4059 ; free virtual = 25935
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1daf4bc89
Time (s): cpu = 00:00:52 ; elapsed = 00:00:32 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4035 ; free virtual = 25911
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.710 | TNS=0.000 | WHS=0.305 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 1daf4bc89
Time (s): cpu = 00:00:52 ; elapsed = 00:00:32 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4035 ; free virtual = 25911
Phase 6 Post Hold Fix | Checksum: 1daf4bc89
Time (s): cpu = 00:00:52 ; elapsed = 00:00:32 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4035 ; free virtual = 25911
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 1.42329 %
Global Horizontal Routing Utilization = 1.78602 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1daf4bc89
Time (s): cpu = 00:00:52 ; elapsed = 00:00:33 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4032 ; free virtual = 25908
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1daf4bc89
Time (s): cpu = 00:00:52 ; elapsed = 00:00:33 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4047 ; free virtual = 25923
Phase 9 Depositing Routes
[60%] Routing Phase 0 completed
Phase 9 Depositing Routes | Checksum: 265b5df9b
Time (s): cpu = 00:00:53 ; elapsed = 00:00:33 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4042 ; free virtual = 25919
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.710 | TNS=0.000 | WHS=0.305 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 265b5df9b
Time (s): cpu = 00:00:54 ; elapsed = 00:00:33 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4042 ; free virtual = 25919
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 191765a97
Time (s): cpu = 00:00:54 ; elapsed = 00:00:34 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4042 ; free virtual = 25918
Ending Routing Task | Checksum: 191765a97
Time (s): cpu = 00:00:54 ; elapsed = 00:00:34 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4042 ; free virtual = 25918
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:35 . Memory (MB): peak = 2799.930 ; gain = 0.000 ; free physical = 4042 ; free virtual = 25918
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (2425)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (7786)
5. checking no_input_delay (10)
6. checking no_output_delay (17)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (2425)
---------------------------
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[37]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[38]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[40]/Q (HIGH)
There are 2413 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (7786)
---------------------------------------------------
There are 7786 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (10)
-------------------------------
There are 10 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (17)
--------------------------------
There are 17 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.734 0.000 0 1 0.321 0.000 0 1 4.500 0.000 0 3
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.734 0.000 0 1 0.321 0.000 0 1 4.500 0.000 0 3
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
[70%] Routing Phase 1 completed
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP SOC/Core/Mdu/MDU_out_S0 output SOC/Core/Mdu/MDU_out_S0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP SOC/Core/Mdu/MDU_out_S0__0 output SOC/Core/Mdu/MDU_out_S0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP SOC/Core/Mdu/MDU_out_S0__1 output SOC/Core/Mdu/MDU_out_S0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP SOC/Core/Mdu/MDU_out_S0 multiplier stage SOC/Core/Mdu/MDU_out_S0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP SOC/Core/Mdu/MDU_out_S0__0 multiplier stage SOC/Core/Mdu/MDU_out_S0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP SOC/Core/Mdu/MDU_out_S0__1 multiplier stage SOC/Core/Mdu/MDU_out_S0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[40]_1[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 8 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
[80%] Routing Phase 2 completed
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3136.250 ; gain = 247.559 ; free physical = 3675 ; free virtual = 25555
INFO: [Common 17-206] Exiting Vivado at Wed Jun 19 02:07:43 2024...
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Wed Jun 19 02:08:28 2024
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Open file DONE
Parse file DONE
load program
[Pipeline] }
Lock released on resource [tangnano20k]
Loading: [====== ] 11.66%[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
Load SRAM: [========= ] 18.00%[Pipeline] }
Loading: [============ ] 23.32%[Pipeline] // stage
[Pipeline] }
Loading: [================== ] 34.98%
Load SRAM: [=================== ] 38.00%
Loading: [======================== ] 46.64%
Load SRAM: [============================= ] 58.00%
Load SRAM: [======================================= ] 78.00%
Loading: [============================== ] 58.30%
Load SRAM: [================================================= ] 98.00%
Loading: [=================================== ] 69.96%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
Loading: [========================================= ] 81.62%[Pipeline] // stage
[Pipeline] }
Loading: [=============================================== ] 93.28%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
+ echo testando na tang nano
testando na tang nano
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
![[Jenkins]](/jenkins/static/b6fe011e/images/svgs/logo.svg){kind=logo}
