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Skipping 397 KB.. Full Log

_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74607'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74581_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74583'.
created $dff cell `$procdff$74633' with positive edge clock.
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74581_ADDR' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74583'.
created $dff cell `$procdff$74634' with positive edge clock.
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74581_DATA' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74583'.
created $dff cell `$procdff$74635' with positive edge clock.
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.\muxwre' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74582'.
created direct connection (no actual register cell created).

24.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74607'.
Found and cleaned up 1 empty switch in `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74583'.
Removing empty process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74582'.
Cleaned up 1 empty switch.

24.42.8.12. Executing OPT_EXPR pass (perform const folding).

24.42.9. Executing PROC pass (convert processes to netlists).

24.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74653'.
Cleaned up 1 empty switch.

24.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74654 in module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.9.4. Executing PROC_INIT pass (extract init attributes).

24.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
Creating decoders for process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74654'.
1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74652_EN[3:0]$74659
2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74652_DATA[3:0]$74658
3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74652_ADDR[3:0]$74660
Creating decoders for process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74653'.

24.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.\i' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74647_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74641_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74636_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74637_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74638_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74642_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74643_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74644_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74648_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74649_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74639_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74650_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74640_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74645_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74646_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74651_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74652_DATA' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74654'.
created $dff cell `$procdff$74704' with positive edge clock.
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74652_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74654'.
created $dff cell `$procdff$74705' with positive edge clock.
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74652_ADDR' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74654'.
created $dff cell `$procdff$74706' with positive edge clock.
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74653'.
created direct connection (no actual register cell created).

24.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74678'.
Found and cleaned up 1 empty switch in `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74654'.
Removing empty process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74653'.
Cleaned up 1 empty switch.

24.42.9.12. Executing OPT_EXPR pass (perform const folding).

24.42.10. Executing PROC pass (convert processes to netlists).

24.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74724'.
Cleaned up 1 empty switch.

24.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74725 in module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.10.4. Executing PROC_INIT pass (extract init attributes).

24.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
Creating decoders for process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74725'.
1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74723_EN[3:0]$74731
2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74723_DATA[3:0]$74730
3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74723_ADDR[3:0]$74729
Creating decoders for process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74724'.

24.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.\i' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74717_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74711_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74714_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74708_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74707_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74713_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74712_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74718_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74719_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74709_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74720_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74710_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74715_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74716_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74721_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74722_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74723_ADDR' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74725'.
created $dff cell `$procdff$74775' with positive edge clock.
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74723_DATA' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74725'.
created $dff cell `$procdff$74776' with positive edge clock.
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74723_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74725'.
created $dff cell `$procdff$74777' with positive edge clock.
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.\muxwre' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74724'.
created direct connection (no actual register cell created).

24.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74749'.
Found and cleaned up 1 empty switch in `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74725'.
Removing empty process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74724'.
Cleaned up 1 empty switch.

24.42.10.12. Executing OPT_EXPR pass (perform const folding).

24.42.11. Executing PROC pass (convert processes to netlists).

24.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74795'.
Cleaned up 1 empty switch.

24.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74796 in module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.11.4. Executing PROC_INIT pass (extract init attributes).

24.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
Creating decoders for process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74796'.
1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74794_EN[3:0]$74802
2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74794_DATA[3:0]$74801
3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74794_ADDR[3:0]$74800
Creating decoders for process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74795'.

24.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.\i' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74793_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74787_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74781_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74778_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74782_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74783_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74784_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74788_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74789_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74779_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74790_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74780_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74785_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74786_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74791_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74792_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74794_ADDR' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74796'.
created $dff cell `$procdff$74846' with positive edge clock.
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74794_DATA' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74796'.
created $dff cell `$procdff$74847' with positive edge clock.
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74794_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74796'.
created $dff cell `$procdff$74848' with positive edge clock.
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.\muxwre' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74795'.
created direct connection (no actual register cell created).

24.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74820'.
Found and cleaned up 1 empty switch in `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74796'.
Removing empty process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74795'.
Cleaned up 1 empty switch.

24.42.11.12. Executing OPT_EXPR pass (perform const folding).

24.42.12. Executing PROC pass (convert processes to netlists).

24.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74866'.
Cleaned up 1 empty switch.

24.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74867 in module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.12.4. Executing PROC_INIT pass (extract init attributes).

24.42.12.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.12.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
Creating decoders for process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74867'.
1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74865_EN[3:0]$74873
2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74865_DATA[3:0]$74872
3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74865_ADDR[3:0]$74871
Creating decoders for process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74866'.

24.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.\i' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74863_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74857_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74851_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74849_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74852_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74853_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74854_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74858_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74859_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74860_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74864_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74850_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74855_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74856_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74861_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$74862_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74865_ADDR' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74867'.
created $dff cell `$procdff$74917' with positive edge clock.
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74865_DATA' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74867'.
created $dff cell `$procdff$74918' with positive edge clock.
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$74865_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74867'.
created $dff cell `$procdff$74919' with positive edge clock.
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74866'.
created direct connection (no actual register cell created).

24.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$74891'.
Found and cleaned up 1 empty switch in `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$74867'.
Removing empty process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$74866'.
Cleaned up 1 empty switch.

24.42.12.12. Executing OPT_EXPR pass (perform const folding).

24.42.13. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$12731.$auto$simplemap.cc:267:simplemap_mux$74115
Found an SCC: $techmap$auto$ff.cc:266:slice$12730.$auto$simplemap.cc:267:simplemap_mux$74115
Found an SCC: $techmap$auto$ff.cc:266:slice$12729.$auto$simplemap.cc:267:simplemap_mux$74115
Found an SCC: $techmap$auto$ff.cc:266:slice$12728.$auto$simplemap.cc:267:simplemap_mux$74115
Found an SCC: $auto$ff.cc:266:slice$8852 $auto$ff.cc:266:slice$8851 $auto$simplemap.cc:126:simplemap_reduce$8988 $auto$opt_expr.cc:613:replace_const_cells$68196 $auto$simplemap.cc:126:simplemap_reduce$8973 $auto$ff.cc:266:slice$8853 $auto$simplemap.cc:225:simplemap_logbin$8962 $auto$simplemap.cc:196:simplemap_lognot$8977 $auto$simplemap.cc:126:simplemap_reduce$8975 $auto$simplemap.cc:126:simplemap_reduce$8972 $auto$opt_expr.cc:613:replace_const_cells$68920 $auto$opt_expr.cc:613:replace_const_cells$68894 $auto$simplemap.cc:267:simplemap_mux$16887 $auto$simplemap.cc:126:simplemap_reduce$16919 $auto$simplemap.cc:126:simplemap_reduce$16916 $auto$simplemap.cc:75:simplemap_bitop$16897 $auto$simplemap.cc:196:simplemap_lognot$8992 $auto$simplemap.cc:126:simplemap_reduce$8990 $auto$simplemap.cc:126:simplemap_reduce$8987 $auto$ff.cc:266:slice$8850 $auto$simplemap.cc:126:simplemap_reduce$7434 $auto$simplemap.cc:126:simplemap_reduce$7432 $auto$simplemap.cc:225:simplemap_logbin$8918 $auto$simplemap.cc:196:simplemap_lognot$8928 $auto$simplemap.cc:126:simplemap_reduce$8926 $auto$opt_expr.cc:613:replace_const_cells$68896 $auto$simplemap.cc:267:simplemap_mux$16888 $auto$simplemap.cc:126:simplemap_reduce$16925 $auto$simplemap.cc:126:simplemap_reduce$16922 $auto$simplemap.cc:75:simplemap_bitop$16889 $auto$simplemap.cc:267:simplemap_mux$8959
Found an SCC: $auto$simplemap.cc:75:simplemap_bitop$19383 $auto$simplemap.cc:38:simplemap_not$21092 $auto$ff.cc:266:slice$8344 $auto$simplemap.cc:75:simplemap_bitop$19380 $auto$simplemap.cc:38:simplemap_not$21089 $auto$ff.cc:266:slice$8341 $auto$alumacc.cc:485:replace_alu$4405.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7140 $auto$simplemap.cc:75:simplemap_bitop$19381 $auto$simplemap.cc:38:simplemap_not$21090 $auto$ff.cc:266:slice$8342 $auto$alumacc.cc:485:replace_alu$4405.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7157 $auto$simplemap.cc:126:simplemap_reduce$7141 $auto$simplemap.cc:75:simplemap_bitop$19382 $auto$simplemap.cc:38:simplemap_not$21091 $auto$ff.cc:266:slice$8343 $auto$simplemap.cc:75:simplemap_bitop$19384 $auto$simplemap.cc:38:simplemap_not$21093 $auto$ff.cc:266:slice$8345 $auto$alumacc.cc:485:replace_alu$4405.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7142 $auto$simplemap.cc:75:simplemap_bitop$19385 $auto$simplemap.cc:38:simplemap_not$21094 $auto$ff.cc:266:slice$8346 $auto$simplemap.cc:75:simplemap_bitop$19386 $auto$simplemap.cc:38:simplemap_not$21095 $auto$ff.cc:266:slice$8347 $auto$alumacc.cc:485:replace_alu$4405.slice[6].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7166 $auto$simplemap.cc:126:simplemap_reduce$7158 $auto$simplemap.cc:126:simplemap_reduce$7143 $auto$simplemap.cc:75:simplemap_bitop$19387 $auto$simplemap.cc:38:simplemap_not$21096 $auto$ff.cc:266:slice$8348 $auto$simplemap.cc:75:simplemap_bitop$19388 $auto$simplemap.cc:38:simplemap_not$21097 $auto$ff.cc:266:slice$8349 $auto$alumacc.cc:485:replace_alu$4405.slice[8].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7144 $auto$simplemap.cc:75:simplemap_bitop$19389 $auto$simplemap.cc:38:simplemap_not$21098 $auto$ff.cc:266:slice$8350 $auto$simplemap.cc:75:simplemap_bitop$19390 $auto$simplemap.cc:38:simplemap_not$21099 $auto$ff.cc:266:slice$8351 $auto$alumacc.cc:485:replace_alu$4405.slice[10].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7159 $auto$simplemap.cc:126:simplemap_reduce$7145 $auto$simplemap.cc:75:simplemap_bitop$19391 $auto$simplemap.cc:38:simplemap_not$21100 $auto$ff.cc:266:slice$8352 $auto$simplemap.cc:75:simplemap_bitop$19392 $auto$simplemap.cc:38:simplemap_not$21101 $auto$ff.cc:266:slice$8353 $auto$alumacc.cc:485:replace_alu$4405.slice[12].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7146 $auto$simplemap.cc:75:simplemap_bitop$19393 $auto$simplemap.cc:38:simplemap_not$21102 $auto$ff.cc:266:slice$8354 $auto$simplemap.cc:75:simplemap_bitop$19394 $auto$simplemap.cc:38:simplemap_not$21103 $auto$ff.cc:266:slice$8355 $auto$alumacc.cc:485:replace_alu$4405.slice[14].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7171 $auto$simplemap.cc:126:simplemap_reduce$7167 $auto$simplemap.cc:126:simplemap_reduce$7160 $auto$simplemap.cc:126:simplemap_reduce$7147 $auto$simplemap.cc:75:simplemap_bitop$19395 $auto$simplemap.cc:38:simplemap_not$21104 $auto$ff.cc:266:slice$8356 $auto$simplemap.cc:38:simplemap_not$21105 $auto$ff.cc:266:slice$8357 $auto$alumacc.cc:485:replace_alu$4405.slice[16].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7148 $auto$simplemap.cc:38:simplemap_not$21106 $auto$ff.cc:266:slice$8358 $auto$simplemap.cc:38:simplemap_not$21107 $auto$ff.cc:266:slice$8359 $auto$alumacc.cc:485:replace_alu$4405.slice[18].ccu2c_i $auto$ff.cc:266:slice$8360 $auto$simplemap.cc:38:simplemap_not$21109 $auto$ff.cc:266:slice$8361 $auto$alumacc.cc:485:replace_alu$4405.slice[20].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7150 $auto$simplemap.cc:38:simplemap_not$21110 $auto$ff.cc:266:slice$8362 $auto$simplemap.cc:38:simplemap_not$21111 $auto$ff.cc:266:slice$8363 $auto$alumacc.cc:485:replace_alu$4405.slice[22].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7162 $auto$simplemap.cc:126:simplemap_reduce$7151 $auto$simplemap.cc:38:simplemap_not$21112 $auto$ff.cc:266:slice$8364 $auto$simplemap.cc:38:simplemap_not$21113 $auto$ff.cc:266:slice$8365 $auto$alumacc.cc:485:replace_alu$4405.slice[24].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7152 $auto$simplemap.cc:38:simplemap_not$21114 $auto$ff.cc:266:slice$8366 $auto$simplemap.cc:38:simplemap_not$21115 $auto$ff.cc:266:slice$8367 $auto$alumacc.cc:485:replace_alu$4405.slice[26].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7163 $auto$simplemap.cc:126:simplemap_reduce$7153 $auto$simplemap.cc:38:simplemap_not$21116 $auto$ff.cc:266:slice$8368 $auto$simplemap.cc:38:simplemap_not$21117 $auto$ff.cc:266:slice$8369 $auto$alumacc.cc:485:replace_alu$4405.slice[28].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7154 $auto$simplemap.cc:38:simplemap_not$21118 $auto$ff.cc:266:slice$8370 $auto$simplemap.cc:38:simplemap_not$21119 $auto$ff.cc:266:slice$8371 $auto$simplemap.cc:38:simplemap_not$6079 $auto$alumacc.cc:485:replace_alu$4405.slice[30].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7169 $auto$simplemap.cc:126:simplemap_reduce$7164 $auto$simplemap.cc:126:simplemap_reduce$7155 $auto$simplemap.cc:38:simplemap_not$19347 $auto$ff.cc:266:slice$8372 $auto$simplemap.cc:126:simplemap_reduce$7314 $auto$simplemap.cc:75:simplemap_bitop$7459 $auto$simplemap.cc:126:simplemap_reduce$7174 $auto$simplemap.cc:126:simplemap_reduce$7172 $auto$simplemap.cc:126:simplemap_reduce$7168 $auto$simplemap.cc:126:simplemap_reduce$7161 $auto$simplemap.cc:126:simplemap_reduce$7149 $auto$simplemap.cc:38:simplemap_not$21108
Found an SCC: $auto$simplemap.cc:38:simplemap_not$17199 $auto$ff.cc:266:slice$8857 $auto$simplemap.cc:126:simplemap_reduce$9008 $auto$ff.cc:266:slice$8856 $auto$ff.cc:266:slice$8855 $auto$simplemap.cc:38:simplemap_not$17200 $auto$ff.cc:266:slice$8858 $auto$ff.cc:266:slice$8862 $auto$simplemap.cc:38:simplemap_not$17196 $auto$ff.cc:266:slice$8854 $auto$simplemap.cc:126:simplemap_reduce$9009 $auto$ff.cc:266:slice$8859 $auto$simplemap.cc:38:simplemap_not$17202 $auto$ff.cc:266:slice$8860 $auto$simplemap.cc:126:simplemap_reduce$9013 $auto$simplemap.cc:126:simplemap_reduce$9010 $auto$simplemap.cc:38:simplemap_not$17203 $auto$ff.cc:266:slice$8861 $auto$simplemap.cc:126:simplemap_reduce$7428 $auto$simplemap.cc:196:simplemap_lognot$9019 $auto$simplemap.cc:126:simplemap_reduce$9017 $auto$simplemap.cc:126:simplemap_reduce$9015 $auto$simplemap.cc:126:simplemap_reduce$9012 $auto$simplemap.cc:126:simplemap_reduce$9007
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$7224 $auto$simplemap.cc:38:simplemap_not$18527 $auto$ff.cc:266:slice$5546 $auto$ff.cc:479:convert_ce_over_srst$73052 $auto$simplemap.cc:126:simplemap_reduce$6083 $auto$ff.cc:266:slice$5545 $auto$ff.cc:479:convert_ce_over_srst$73050 $auto$simplemap.cc:38:simplemap_not$19279 $auto$ff.cc:266:slice$5544 $auto$ff.cc:479:convert_ce_over_srst$73048 $auto$simplemap.cc:126:simplemap_reduce$6082 $auto$ff.cc:266:slice$5543 $auto$ff.cc:479:convert_ce_over_srst$73046 $auto$simplemap.cc:38:simplemap_not$6075 $auto$alumacc.cc:485:replace_alu$4438.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$4438.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$4438.slice[0].ccu2c_i $auto$simplemap.cc:38:simplemap_not$19277 $auto$ff.cc:266:slice$5542 $auto$ff.cc:479:convert_ce_over_srst$73044 $auto$simplemap.cc:126:simplemap_reduce$7195 $auto$simplemap.cc:126:simplemap_reduce$7206 $auto$simplemap.cc:126:simplemap_reduce$7227 $auto$simplemap.cc:126:simplemap_reduce$7225 $auto$simplemap.cc:38:simplemap_not$6076 $auto$simplemap.cc:75:simplemap_bitop$6077 $auto$simplemap.cc:126:simplemap_reduce$6087 $auto$simplemap.cc:126:simplemap_reduce$6085 $auto$simplemap.cc:126:simplemap_reduce$6081 $auto$opt_expr.cc:613:replace_const_cells$71020 $auto$ff.cc:266:slice$5541 $auto$ff.cc:479:convert_ce_over_srst$73042 $auto$simplemap.cc:126:simplemap_reduce$7208
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$68914 $auto$ff.cc:266:slice$8710 $auto$simplemap.cc:126:simplemap_reduce$8832 $auto$simplemap.cc:126:simplemap_reduce$8805 $auto$ff.cc:266:slice$8711 $auto$simplemap.cc:38:simplemap_not$16969 $auto$ff.cc:266:slice$8712 $auto$simplemap.cc:126:simplemap_reduce$8837 $auto$simplemap.cc:126:simplemap_reduce$8833 $auto$simplemap.cc:126:simplemap_reduce$8806 $auto$simplemap.cc:38:simplemap_not$16970 $auto$ff.cc:266:slice$8713 $auto$simplemap.cc:38:simplemap_not$16971 $auto$ff.cc:266:slice$8714 $auto$simplemap.cc:126:simplemap_reduce$8834 $auto$simplemap.cc:126:simplemap_reduce$8807 $auto$simplemap.cc:38:simplemap_not$16972 $auto$ff.cc:266:slice$8715 $auto$simplemap.cc:38:simplemap_not$16973 $auto$ff.cc:266:slice$8716 $auto$simplemap.cc:126:simplemap_reduce$8811 $auto$simplemap.cc:126:simplemap_reduce$8808 $auto$simplemap.cc:126:simplemap_reduce$8840 $auto$simplemap.cc:126:simplemap_reduce$8838 $auto$simplemap.cc:126:simplemap_reduce$8835 $auto$simplemap.cc:38:simplemap_not$16974 $auto$ff.cc:266:slice$8717 $auto$simplemap.cc:196:simplemap_lognot$8844 $auto$simplemap.cc:126:simplemap_reduce$8842 $auto$ff.cc:266:slice$8718 $auto$simplemap.cc:167:logic_reduce$7439 $auto$simplemap.cc:225:simplemap_logbin$8789 $auto$simplemap.cc:225:simplemap_logbin$8790 $auto$simplemap.cc:196:simplemap_lognot$8817 $auto$simplemap.cc:126:simplemap_reduce$8815 $auto$simplemap.cc:126:simplemap_reduce$8813 $auto$simplemap.cc:126:simplemap_reduce$8810
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$7401 $auto$simplemap.cc:126:simplemap_reduce$7325 $auto$simplemap.cc:126:simplemap_reduce$7394 $auto$simplemap.cc:126:simplemap_reduce$7392 $auto$simplemap.cc:126:simplemap_reduce$7355 $auto$simplemap.cc:126:simplemap_reduce$7353 $auto$opt_expr.cc:613:replace_const_cells$70938 $auto$ff.cc:266:slice$11427 $auto$dfflegalize.cc:941:flip_pol$73040 $auto$ff.cc:485:convert_ce_over_srst$73038 $auto$ff.cc:266:slice$11426 $auto$dfflegalize.cc:941:flip_pol$73036 $auto$ff.cc:485:convert_ce_over_srst$73034 $auto$simplemap.cc:126:simplemap_reduce$8015 $auto$opt_expr.cc:613:replace_const_cells$71018 $auto$ff.cc:266:slice$11425 $auto$dfflegalize.cc:941:flip_pol$73032 $auto$ff.cc:485:convert_ce_over_srst$73030 $auto$simplemap.cc:126:simplemap_reduce$7329 $auto$simplemap.cc:126:simplemap_reduce$7327 $auto$simplemap.cc:126:simplemap_reduce$7324 $auto$simplemap.cc:126:simplemap_reduce$7362 $auto$simplemap.cc:126:simplemap_reduce$8017
Found an SCC: $auto$simplemap.cc:75:simplemap_bitop$19824 $auto$simplemap.cc:38:simplemap_not$19760 $auto$ff.cc:266:slice$7943 $auto$simplemap.cc:38:simplemap_not$19784 $auto$ff.cc:266:slice$7967 $auto$simplemap.cc:75:simplemap_bitop$19819 $auto$simplemap.cc:38:simplemap_not$19755 $auto$ff.cc:266:slice$7938 $auto$simplemap.cc:75:simplemap_bitop$19826 $auto$simplemap.cc:38:simplemap_not$19762 $auto$ff.cc:266:slice$7945 $auto$simplemap.cc:126:simplemap_reduce$6001 $auto$simplemap.cc:75:simplemap_bitop$19823 $auto$simplemap.cc:38:simplemap_not$19759 $auto$ff.cc:266:slice$7942 $auto$simplemap.cc:126:simplemap_reduce$6017 $auto$simplemap.cc:126:simplemap_reduce$6002 $auto$simplemap.cc:75:simplemap_bitop$19825 $auto$simplemap.cc:38:simplemap_not$19761 $auto$ff.cc:266:slice$7944 $auto$simplemap.cc:75:simplemap_bitop$19822 $auto$simplemap.cc:38:simplemap_not$19758 $auto$ff.cc:266:slice$7941 $auto$simplemap.cc:38:simplemap_not$19757 $auto$ff.cc:266:slice$7940 $auto$simplemap.cc:126:simplemap_reduce$5999 $auto$simplemap.cc:75:simplemap_bitop$19820 $auto$simplemap.cc:38:simplemap_not$19756 $auto$alumacc.cc:485:replace_alu$4427.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$4427.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$4427.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$4427.slice[0].ccu2c_i $auto$ff.cc:266:slice$7939 $auto$simplemap.cc:75:simplemap_bitop$19827 $auto$simplemap.cc:38:simplemap_not$19763 $auto$ff.cc:266:slice$7946 $auto$alumacc.cc:485:replace_alu$4427.slice[8].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6003 $auto$simplemap.cc:75:simplemap_bitop$19828 $auto$simplemap.cc:38:simplemap_not$19764 $auto$ff.cc:266:slice$7947 $auto$simplemap.cc:75:simplemap_bitop$19829 $auto$simplemap.cc:38:simplemap_not$19765 $auto$ff.cc:266:slice$7948 $auto$alumacc.cc:485:replace_alu$4427.slice[10].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6018 $auto$simplemap.cc:126:simplemap_reduce$6004 $auto$simplemap.cc:75:simplemap_bitop$19830 $auto$simplemap.cc:38:simplemap_not$19766 $auto$ff.cc:266:slice$7949 $auto$simplemap.cc:75:simplemap_bitop$19831 $auto$simplemap.cc:38:simplemap_not$19767 $auto$ff.cc:266:slice$7950 $auto$alumacc.cc:485:replace_alu$4427.slice[12].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6005 $auto$simplemap.cc:75:simplemap_bitop$19832 $auto$simplemap.cc:38:simplemap_not$19768 $auto$ff.cc:266:slice$7951 $auto$simplemap.cc:75:simplemap_bitop$19833 $auto$simplemap.cc:38:simplemap_not$19769 $auto$ff.cc:266:slice$7952 $auto$alumacc.cc:485:replace_alu$4427.slice[14].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6026 $auto$simplemap.cc:126:simplemap_reduce$6019 $auto$simplemap.cc:126:simplemap_reduce$6006 $auto$simplemap.cc:75:simplemap_bitop$19834 $auto$simplemap.cc:38:simplemap_not$19770 $auto$ff.cc:266:slice$7953 $auto$simplemap.cc:38:simplemap_not$19771 $auto$ff.cc:266:slice$7954 $auto$alumacc.cc:485:replace_alu$4427.slice[16].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$9663 $auto$simplemap.cc:38:simplemap_not$19772 $auto$ff.cc:266:slice$7955 $auto$simplemap.cc:38:simplemap_not$19773 $auto$ff.cc:266:slice$7956 $auto$alumacc.cc:485:replace_alu$4427.slice[18].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$9676 $auto$simplemap.cc:126:simplemap_reduce$9664 $auto$simplemap.cc:38:simplemap_not$19774 $auto$ff.cc:266:slice$7957 $auto$simplemap.cc:38:simplemap_not$19775 $auto$ff.cc:266:slice$7958 $auto$alumacc.cc:485:replace_alu$4427.slice[20].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$9665 $auto$simplemap.cc:38:simplemap_not$19776 $auto$ff.cc:266:slice$7959 $auto$simplemap.cc:38:simplemap_not$19777 $auto$ff.cc:266:slice$7960 $auto$alumacc.cc:485:replace_alu$4427.slice[22].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$9683 $auto$simplemap.cc:126:simplemap_reduce$9677 $auto$simplemap.cc:126:simplemap_reduce$9666 $auto$simplemap.cc:38:simplemap_not$19778 $auto$ff.cc:266:slice$7961 $auto$simplemap.cc:38:simplemap_not$19779 $auto$ff.cc:266:slice$7962 $auto$alumacc.cc:485:replace_alu$4427.slice[24].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$9667 $auto$simplemap.cc:38:simplemap_not$19780 $auto$ff.cc:266:slice$7963 $auto$simplemap.cc:38:simplemap_not$19781 $auto$ff.cc:266:slice$7964 $auto$alumacc.cc:485:replace_alu$4427.slice[26].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$9678 $auto$simplemap.cc:126:simplemap_reduce$9668 $auto$simplemap.cc:38:simplemap_not$19782 $auto$ff.cc:266:slice$7965 $auto$alumacc.cc:485:replace_alu$4427.slice[28].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$9669 $auto$simplemap.cc:38:simplemap_not$19783 $auto$ff.cc:266:slice$7966 $auto$simplemap.cc:38:simplemap_not$19785 $auto$ff.cc:266:slice$7968 $auto$simplemap.cc:38:simplemap_not$5832 $auto$alumacc.cc:485:replace_alu$4427.slice[30].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$9687 $auto$simplemap.cc:126:simplemap_reduce$9684 $auto$simplemap.cc:126:simplemap_reduce$9679 $auto$simplemap.cc:126:simplemap_reduce$9670 $auto$simplemap.cc:38:simplemap_not$17838 $auto$ff.cc:266:slice$7969 $auto$simplemap.cc:126:simplemap_reduce$7308 $auto$simplemap.cc:75:simplemap_bitop$5997 $auto$simplemap.cc:126:simplemap_reduce$6033 $auto$simplemap.cc:126:simplemap_reduce$6030 $auto$simplemap.cc:126:simplemap_reduce$6025 $auto$simplemap.cc:126:simplemap_reduce$6016 $auto$simplemap.cc:126:simplemap_reduce$6000 $auto$simplemap.cc:75:simplemap_bitop$19821
Found 11 SCCs in module top.
Found 11 SCCs.

24.42.14. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.15. Executing PROC pass (convert processes to netlists).

24.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

24.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

24.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

24.42.15.4. Executing PROC_INIT pass (extract init attributes).

24.42.15.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.15.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

24.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

24.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs).

24.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

24.42.15.12. Executing OPT_EXPR pass (perform const folding).

24.42.16. Executing TECHMAP pass (map to technology primitives).

24.42.16.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

24.42.16.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~180 debug messages>

24.42.17. Executing OPT pass (performing simple optimizations).

24.42.17.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.
Optimizing module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.
Optimizing module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.
Optimizing module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.
Optimizing module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.
Optimizing module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.
Optimizing module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.
Optimizing module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.

24.42.17.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

24.42.17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.

24.42.17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing cells in module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.
Optimizing cells in module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.
Optimizing cells in module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.
Optimizing cells in module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.
Optimizing cells in module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.
Optimizing cells in module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.
Optimizing cells in module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.
Optimizing cells in module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.
Performed a total of 0 changes.

24.42.17.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

24.42.17.6. Executing OPT_DFF pass (perform DFF optimizations).

24.42.17.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4..

24.42.17.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.
Optimizing module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.
Optimizing module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.
Optimizing module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.
Optimizing module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.
Optimizing module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.

24.42.17.9. Finished OPT passes. (There is nothing left to do.)

24.42.18. Executing TECHMAP pass (map to technology primitives).

24.42.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

24.42.18.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4 for cells of type $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.
Using template $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4 for cells of type $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.
Using template $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4 for cells of type $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.
Using template $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4 for cells of type $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.
Using template $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4 for cells of type $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.
Using template $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4 for cells of type $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.
Using template $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4 for cells of type $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.
Using template $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4 for cells of type $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~320 debug messages>

24.42.19. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

24.42.20. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

24.42.21. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.22. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

24.42.23. Executing TECHMAP pass (map to technology primitives).

24.42.23.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

24.42.23.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~219 debug messages>

24.42.24. Executing OPT pass (performing simple optimizations).

24.42.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

24.42.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

24.42.24.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.

24.42.24.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.

24.42.24.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.42.24.6. Executing OPT_DFF pass (perform DFF optimizations).

24.42.24.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

24.42.24.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.42.24.9. Rerunning OPT passes. (Maybe there is more to do..)

24.42.24.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.

24.42.24.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.

24.42.24.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.42.24.13. Executing OPT_DFF pass (perform DFF optimizations).

24.42.24.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

24.42.24.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.42.24.16. Finished OPT passes. (There is nothing left to do.)

24.42.25. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
replaced 3 cell types:
2 $_OR_
2 $_XOR_
14 $_MUX_
not replaced 3 cell types:
31 $specify2
4 $_NOT_
4 $_AND_

24.42.26. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 7963 cells with 50473 new cells, skipped 9385 cells.
replaced 4 cell types:
1752 $_OR_
1193 $_XOR_
3 $_ORNOT_
5015 $_MUX_
not replaced 28 cell types:
33 $scopeinfo
1615 $_NOT_
3311 $_AND_
6 $_TBUF_
1058 TRELLIS_FF
3 MULT18X18D
1 $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4
1 $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4
1 $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp
2742 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
1 $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp
1 $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp
1 $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp
1 $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp
1 $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp
1 $__ABC9_SCC_BREAKER
1 $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp
1 $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp
276 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp
24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4
276 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
1 $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4
1 $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4
1 $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4
1 $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4
1 $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4
1 $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4

24.42.26.1. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.26.2. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.26.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 23690 AND gates and 69754 wires from module `top' to a netlist network with 2370 inputs and 964 outputs.

24.42.26.4. Executing ABC9_EXE pass (technology mapping using ABC9).

24.42.26.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_lut <abc-temp-dir>/input.lut
ABC: + read_box <abc-temp-dir>/input.box
ABC: + &read <abc-temp-dir>/input.xaig
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 2370/ 964 and = 22007 lev = 386 (27.88) mem = 0.86 MB box = 3050 bb = 308
ABC: + &scorr
ABC: Warning: The network is combinational.
ABC: + &sweep
ABC: + &dc2
ABC: + &dch -f
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 2370/ 964 and = 16544 lev = 68 (2.59) mem = 0.48 MB ch = 1875 box = 1306 bb = 308
ABC: + &if -W 300 -v
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 64. Obj = 148. Set = 672. CutMin = no
ABC: Node = 16544. Ch = 1766. Total mem = 5.56 MB. Peak cut mem = 0.32 MB.
ABC: P: Del = 52716.00. Ar = 16602.0. Edge = 19686. Cut = 205467. T = 0.05 sec
ABC: P: Del = 52231.00. Ar = 16552.0. Edge = 19527. Cut = 200220. T = 0.05 sec
ABC: P: Del = 52231.00. Ar = 4544.0. Edge = 13132. Cut = 502054. T = 0.12 sec
ABC: F: Del = 52231.00. Ar = 3992.0. Edge = 12781. Cut = 505708. T = 0.12 sec
ABC: A: Del = 52231.00. Ar = 3867.0. Edge = 12195. Cut = 481062. T = 0.19 sec
ABC: A: Del = 52231.00. Ar = 3851.0. Edge = 12137. Cut = 482067. T = 0.19 sec
ABC: Total time = 0.72 sec
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &mfs
ABC: + &ps -l
ABC: <abc-temp-dir>/input : i/o = 2370/ 964 and = 10622 lev = 72 (2.62) mem = 0.41 MB box = 1306 bb = 308
ABC: Mapping (K=7) : lut = 3318 edge = 12028 lev = 34 (1.53) Boxes are not in a topological order. Switching to level computation without boxes.
ABC: levB = 72 mem = 0.18 MB
ABC: LUT = 3318 : 2=330 9.9 % 3=944 28.5 % 4=1763 53.1 % 5=238 7.2 % 6=7 0.2 % 7=36 1.1 % Ave = 3.63
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + time
ABC: elapse: 5.39 seconds, total: 5.39 seconds

24.42.26.6. Executing AIGER frontend.
<suppressed ~8424 debug messages>
Removed 15249 unused cells and 35906 unused wires.

24.42.26.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS: $lut cells: 3347
ABC RESULTS: $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp cells: 1
ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 998
ABC RESULTS: $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp cells: 1
ABC RESULTS: $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp cells: 1
ABC RESULTS: $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp cells: 1
ABC RESULTS: $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp cells: 1
ABC RESULTS: $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp cells: 1
ABC RESULTS: $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp cells: 1
ABC RESULTS: $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp cells: 1
ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 276
ABC RESULTS: $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells: 24
ABC RESULTS: input signals: 369
ABC RESULTS: output signals: 168
Removing temp directory.

24.42.27. Executing TECHMAP pass (map to technology primitives).

24.42.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

24.42.27.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4 for cells of type $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.
Using template $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4 for cells of type $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.
Using template $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4 for cells of type $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.
Using template $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4 for cells of type $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.
Using template $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4 for cells of type $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.
Using template $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4 for cells of type $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.
Using template $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4 for cells of type $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.
Using template $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4 for cells of type $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001011 for cells of type $__ABC9_SCC_BREAKER.
No more expansions possible.
<suppressed ~1652 debug messages>
Removed 1972 unused cells and 76318 unused wires.

24.43. Executing TECHMAP pass (map to technology primitives).

24.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

24.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut.
Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut.
Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$ea5280fce2698f0f291737e66fca69a1d9d058e1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$2844c7fef2a755a9af80c70990cd830291c4b71c\$lut for cells of type $lut.
Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut.
Using template $paramod$53aa4ed694a318d1c953f64ce655f506530d6819\$lut for cells of type $lut.
Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut.
Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$7927bcf0ebf9ad32c99c221ff948f324620c5795\$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef\$lut for cells of type $lut.
Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d\$lut for cells of type $lut.
Using template $paramod$1a10df59f43f252ae2ee713b788731ad5d18c6f5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$c854c5c77bc7c429c5b9cd582d4f32cbbcb4d3f0\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$37f494dcc63f6757d907b5936f5f221c6c5e4340\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$5f44007876998592e58b9bc671bd4c63c418cb05\$lut for cells of type $lut.
Using template $paramod$2645ed3928f2726e8ccb403cb23252de43b617d7\$lut for cells of type $lut.
Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$6a3d1b4c6389888034ca851571f0d03f46d1c4e9\$lut for cells of type $lut.
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut.
Using template $paramod$79fcd6877631f8ad66bc8725d8a5419347717758\$lut for cells of type $lut.
Using template $paramod$b009a26b33c3ca109c016cf968a774c0d66687bb\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$c958b3a888f937f082b94811ff62d71e32a2b4eb\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$cdedaeac136b0ddce26b73f942df5f4bec7d331c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
Using template $paramod$d497222f59d990d3f689ed9c6ac453ecc8a2f4b4\$lut for cells of type $lut.
Using template $paramod$8ac469b08ec304beefad090d643d1150a22311b3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod$8cac60f778d22518f85ff7609bd7e8781e91c16a\$lut for cells of type $lut.
Using template $paramod$33df0c7289d3974ca02629661ee48bb2471bdbe5\$lut for cells of type $lut.
Using template $paramod$56d36648044d0bf0f892c2050a60c21ad090a3b1\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$c8a407336a452d701a7954919bb30f0c97b9b3b8\$lut for cells of type $lut.
Using template $paramod$3ccc23db184ad4ca7ed34ebe2511de41d5d97e78\$lut for cells of type $lut.
Using template $paramod$f2597669050d64843182b33ad15d6b9eb290f236\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$2c1875de701f39453798b76f5b327fe456cc0991\$lut for cells of type $lut.
Using template $paramod$9405cf9985007177924ba2a7fefa37c0989708cb\$lut for cells of type $lut.
Using template $paramod$6e2b27a23561eba4d5d7a3612a01502854865858\$lut for cells of type $lut.
Using template $paramod$05c5f6a110cf1477117aed2d0c02c0941fa470d5\$lut for cells of type $lut.
Using template $paramod$4e549bd83d017aa5bcca14a32d293e8afc3c4e05\$lut for cells of type $lut.
Using template $paramod$8a77a4b825e7cd0e2a0cbe1bb8ec99794d7f5906\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010011 for cells of type $lut.
Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut.
Using template $paramod$1ddad4c9541ee709a9db41f36ddd1f4483e434a7\$lut for cells of type $lut.
Using template $paramod$d6d96cbce6a9f80962fa4999b2327b58643f013a\$lut for cells of type $lut.
Using template $paramod$6230360d3448cb863f2f259c28a1234ced7c698b\$lut for cells of type $lut.
Using template $paramod$7ef50fdb56c554ca9e0ed251f8adea3e5d724cae\$lut for cells of type $lut.
Using template $paramod$1d0525724ac068b5dfb483a798d6d5f207b20d29\$lut for cells of type $lut.
Using template $paramod$703a7ae3e3e987bf860b577048c8f35c4b341275\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$cd05caaf261e4148f336c0ecc488c806e4433d99\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut.
Using template $paramod$22dec7e8c4f4b1c3e62879fa2207e0c39047bbd3\$lut for cells of type $lut.
Using template $paramod$e85adda8ca03c59dd705bd345f58957b5394296c\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$99a730676ae1842a22fdc62de11e7b85bdd11948\$lut for cells of type $lut.
Using template $paramod$eb453e5c4284f97a8ffea70cb552841f9d2d6223\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$c9e3caba922487050cffdaccf2f3aa7a9d17ef25\$lut for cells of type $lut.
Using template $paramod$aabd7471e271b32a66521313541174fbb89658ea\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut.
Using template $paramod$adceb11ecdba48deee6fdb9cbec9e0a2b3e681aa\$lut for cells of type $lut.
Using template $paramod$2d70e360329f2b83357618532825d0cf30a325f3\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$15efa44280f2a77bf023b68f95d9df5681d9dd99\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$d64d7369831e9431598ee9c87b235e8134477da9\$lut for cells of type $lut.
Using template $paramod$92d3b086976ce77e65158c062812eb1264c2f288\$lut for cells of type $lut.
Using template $paramod$4a8ccde97ddf128ea155c6674e42e6e0c58748e2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut.
Using template $paramod$3e43adeb3ede3a26483f91ac08e8f65e90ce6447\$lut for cells of type $lut.
Using template $paramod$a50f1c411368f4b7b265d7b2b2e06d07b921e41d\$lut for cells of type $lut.
Using template $paramod$a977fb3a4e30b200887394f8ff6c3df1befab9e3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$059968be1ef12c596bb5d360a749040b6777bf4a\$lut for cells of type $lut.
Using template $paramod$adc0b354bb960519a616db7423a6274fc380540e\$lut for cells of type $lut.
Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut.
Using template $paramod$b080214c9db577129a222a846010b16fb02dd91d\$lut for cells of type $lut.
Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut.
Using template $paramod$833582361e14b3ee2e66ad676022ab35d7aa7e28\$lut for cells of type $lut.
Using template $paramod$4193f752b62feb0690f3938e21d1fa94f74b60ca\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut.
Using template $paramod$ee04a7397c7e60ad1a187fa314ed449c24407f97\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut.
Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut.
Using template $paramod$486d1e1cdd0727e7000b2a5997534189586e24cf\$lut for cells of type $lut.
Using template $paramod$25696d6b21c8ac3da9913114964545779e21cfa5\$lut for cells of type $lut.
Using template $paramod$0e7ce19e5da99c6675c7a5220f7cc55270b24ac0\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$880419446f3a2cf4c21cd526996c95ca29677c60\$lut for cells of type $lut.
Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$95993c7d70457a51738c6b0f8898a55038ff3107\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut.
Using template $paramod$fb4ed309581bcd972f41afa8566ae8b9812c7f6c\$lut for cells of type $lut.
Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e\$lut for cells of type $lut.
Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut.
Using template $paramod$f55f4b90ec8e3e648d5c29eab1fa5ddd64b3f973\$lut for cells of type $lut.
Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut.
Using template $paramod$1ad9ca75a5e52e69f39f16c0b8ffb14773a0b7f2\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut.
Using template $paramod$6cf3af45e53e3262a3cbe3667dbe8957fd5e9d12\$lut for cells of type $lut.
Using template $paramod$b68f9800cc1bf69afcfbc0567a25e43ebb01456c\$lut for cells of type $lut.
Using template $paramod$18df3812bc12364e5ebcb6c3ed05c0294e4c26fc\$lut for cells of type $lut.
Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut.
Using template $paramod$902ed43dcaa6101b2d051ad26600288d910a8996\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$707701b498a5cd123a043548b93e61e0b6bdc440\$lut for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$6a16e4fccb8eed964c3fc9fdc636ddabebf4f44e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$e9d317c55f397705fc52599574a03ca7c6820239\$lut for cells of type $lut.
Using template $paramod$a48d96b3084901aac1f541d9be59ab6aad37df36\$lut for cells of type $lut.
Using template $paramod$8b76a70a1f2550a9818889bc64ad11039c8093e0\$lut for cells of type $lut.
Using template $paramod$903b13a78e0201d81ee2cb5e579e213337de2eac\$lut for cells of type $lut.
Using template $paramod$a59854b679c443f21a6748ea460109b8241cb007\$lut for cells of type $lut.
Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut.
Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod$8f48eeacc58ae4e09511e9c70a1ce2f230f70139\$lut for cells of type $lut.
Using template $paramod$fe1497207981e9e4f2f9556fad9970ec052e0a6d\$lut for cells of type $lut.
Using template $paramod$9506ecf18c91672f3dae4008b6ad1f2863e8019f\$lut for cells of type $lut.
Using template $paramod$18455d4fd1270af2266bf4bb1c44971b2eb6b37a\$lut for cells of type $lut.
Using template $paramod$edb5e3f11a3d3283a20e1b8331e255940671d5c0\$lut for cells of type $lut.
Using template $paramod$636e52c16771372d071cc35f679040571dd4a61f\$lut for cells of type $lut.
Using template $paramod$526e4703e3f9e5bf75da836fd3d4410dd76747a6\$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$9dfe2a25d99d8640a9f67a2438aaca85b684d257\$lut for cells of type $lut.
Using template $paramod$64b84593fae19d6c4d7d26333a195e5cc6b30160\$lut for cells of type $lut.
Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$73311b45afe783964b8a99b303013155bf535006\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$ca2167e97c50792f5ced35a59198c1ac5e93e2b7\$lut for cells of type $lut.
Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707\$lut for cells of type $lut.
Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut.
Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da\$lut for cells of type $lut.
Using template $paramod$1b4f238a94d3bc162f2c99f5ddeee03b07e52edc\$lut for cells of type $lut.
Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed\$lut for cells of type $lut.
Using template $paramod$0d5e420ccfc2dddc13533c0817d1e17e68a2c136\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011100 for cells of type $lut.
Using template $paramod$8a36c081272474affa18f5450d51d09af3f63404\$lut for cells of type $lut.
Using template $paramod$b4d0f4738a5ce50c7f36c2aa2ecc09cfb874f2b6\$lut for cells of type $lut.
Using template $paramod$a75fe1683a97958e61513f004cf91c3458c2f88e\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$7ed3d685a887e531dc8f4f21b9907d4766cf861f\$lut for cells of type $lut.
Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut.
Using template $paramod$bea08a495d16293f8cc454a45845d26cde0762b6\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut.
Using template $paramod$d546db88fc169832512e499a9cdf9a41b89ab74e\$lut for cells of type $lut.
Using template $paramod$9fc14cb0ba5120a1da0c687a9fb19472f206fdfe\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod$b600d182ae966d09f33a746441e104587fe7a58f\$lut for cells of type $lut.
Using template $paramod$3dfdb778126ab011e4d5dd8bd717182a0c306ecc\$lut for cells of type $lut.
Using template $paramod$c600b4b1adc22857e1c1ba3b6aeb516fabe09da0\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut.
Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110011 for cells of type $lut.
Using template $paramod$1f313f85ef575d13bac75382f04905a8c8be8f57\$lut for cells of type $lut.
Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut.
Using template $paramod$52fa1b2073b9054923f466bbb768e0ea7c69c9e3\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$946e4ba6cc6d5f643745e6b56089375901ce6d2c\$lut for cells of type $lut.
Using template $paramod$734cd1512f671d92bc4f41153da0d9781801dd98\$lut for cells of type $lut.
Using template $paramod$f6f4335bacd365d464ceca142c167254a0ecca80\$lut for cells of type $lut.
Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut.
Using template $paramod$684b54388be6489c38743e4efd4f9fa13e760a4a\$lut for cells of type $lut.
Using template $paramod$4d256fbdc9e64053bf8437c1c851d487119b6909\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$117b4ac929d164ff303b0e43081fcca142b79922\$lut for cells of type $lut.
Using template $paramod$5307f40f1b453046eb68ee1a10c3f82d605af6fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010111 for cells of type $lut.
Using template $paramod$66a21d6ecac0a869f10dfeecf6235898a47b3b78\$lut for cells of type $lut.
Using template $paramod$8b5cd3db939d1b72145e634c68ab25658458fb1a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
Using template $paramod$899a7d400185b4f778bea81a50f62c95a0b19d77\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110011 for cells of type $lut.
Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut.
Using template $paramod$0939298d426d727b8afa3e9642d621400f6da76d\$lut for cells of type $lut.
Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut.
Using template $paramod$5637f6366c0fa622e75f886ee59706323e5fe6fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut.
Using template $paramod$bff60da521de773f8caf46fbc0845c3d7d3e2310\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$df208ff6c4621519a3b9ca6dd51a2309b7a22b96\$lut for cells of type $lut.
Using template $paramod$a05130630e3bd6f8c42c35e2bee91a8488080c81\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$3e63470ea7a06b3eefdfb990254dd83d20fa13a7\$lut for cells of type $lut.
Using template $paramod$fb5496753f4cd235e71c284b2ffee9d41a960ca2\$lut for cells of type $lut.
Using template $paramod$00dfa99b7aecc2e72490719b192118cbd6549a2c\$lut for cells of type $lut.
Using template $paramod$4721519bef85e75f87d1f147d88c627c84abf942\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~6449 debug messages>

24.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176782.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176837.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9667.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$176669$lut$aiger176668$8298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$13386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$10023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$10047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$10082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$10129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$12547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$12764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$12819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$13013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$13151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$13481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$13601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$13768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$13923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$13958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$14024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$14059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$14190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$14225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$14577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$14612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$14973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$15141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$15433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$15544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$15718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$15852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$15964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$16094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$16263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$16378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$16525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$16674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$16811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$16903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$6717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$6836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$6999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$7177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$7255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$7269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$7283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$7297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$7385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$7399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$7413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$7427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$7444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$7478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7556.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7593.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7633.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7651.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7710.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7773.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7813.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$auto$abc9_ops.cc:595:break_scc$75347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$7891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7891.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7949.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$7992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$7992.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$8014.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$8032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$8060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$8078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$8100.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$8118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$8143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$8161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$8183.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$8201.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$8230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8271.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$176669$lut$aiger176668$8447.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177157.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$176669$lut$aiger176668$8542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$176669$lut$aiger176668$8562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$8597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$8627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$8657.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$176669$lut$aiger176668$8922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$176669$lut$aiger176668$9217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176691.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177167.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$176669$lut$aiger176668$9262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176689.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$176669$lut$aiger176668$9466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$177159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$176669$lut$aiger176668$9502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$176669$lut$aiger176668$9516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$9698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$176669$lut$aiger176668$9735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176678.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176674.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176672.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$auto$abc9_ops.cc:595:break_scc$75347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$13266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$auto$opt_dff.cc:219:make_patterns_logic$4314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176679.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$auto$fsm_map.cc:170:map_fsm$4050[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$auto$rtlil.cc:2582:Mux$4611[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$176669$lut$aiger176668$9013.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176706.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$176669$lut$aiger176668$8332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176786.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176773.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176775.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176805.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$176820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Removed 0 unused cells and 7204 unused wires.

24.45. Executing AUTONAME pass.
Renamed 197564 objects in module top (216 iterations).
<suppressed ~7079 debug messages>

24.46. Executing HIERARCHY pass (managing design hierarchy).

24.46.1. Analyzing design hierarchy..
Top module: \top

24.46.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.

24.47. Printing statistics.

=== top ===

Number of wires: 2963
Number of wire bits: 12166
Number of public wires: 2963
Number of public wire bits: 12166
Number of ports: 6
Number of port bits: 18
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 4736
$_TBUF_ 6
$scopeinfo 33
CCU2C 212
L6MUX21 1
LUT4 2935
PFUMX 223
TRELLIS_DPR16X4 308
TRELLIS_FF 1018

24.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

24.49. Executing JSON backend.

Warnings: 2 unique messages, 3 total
End of script. Logfile hash: 41163a94d7, CPU: user 14.36s system 0.18s, MEM: 341.25 MB peak
Yosys 0.42+15 (git sha1 74a1dd99a, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
Time spent: 27% 1x abc9_exe (5 sec), 15% 11x techmap (3 sec), ...